1c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 2fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 339cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 45edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 57bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 639cb62cbSJoseph Lo 739cb62cbSJoseph Lo/ { 839cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 939cb62cbSJoseph Lo interrupt-parent = <&gic>; 1039cb62cbSJoseph Lo #address-cells = <2>; 1139cb62cbSJoseph Lo #size-cells = <2>; 1239cb62cbSJoseph Lo 13fc4bb754SThierry Reding gpio: gpio@2200000 { 14fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 15fc4bb754SThierry Reding reg-names = "security", "gpio"; 16fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 17fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 18fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 19fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 20fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 21fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 22fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 23fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 24fc4bb754SThierry Reding #interrupt-cells = <2>; 25fc4bb754SThierry Reding interrupt-controller; 26fc4bb754SThierry Reding #gpio-cells = <2>; 27fc4bb754SThierry Reding gpio-controller; 28fc4bb754SThierry Reding }; 29fc4bb754SThierry Reding 300caafbdeSThierry Reding ethernet@2490000 { 310caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 320caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 330caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 340caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 350caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 360caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 370caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 380caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 390caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 400caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 410caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 420caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 430caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 440caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 450caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 460caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 470caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 480caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 490caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 500caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 510caafbdeSThierry Reding reset-names = "eqos"; 520caafbdeSThierry Reding status = "disabled"; 530caafbdeSThierry Reding 540caafbdeSThierry Reding snps,write-requests = <1>; 550caafbdeSThierry Reding snps,read-requests = <3>; 560caafbdeSThierry Reding snps,burst-map = <0x7>; 570caafbdeSThierry Reding snps,txpbl = <32>; 580caafbdeSThierry Reding snps,rxpbl = <8>; 590caafbdeSThierry Reding }; 600caafbdeSThierry Reding 6139cb62cbSJoseph Lo uarta: serial@3100000 { 6239cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 6339cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 6439cb62cbSJoseph Lo reg-shift = <2>; 6539cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 66c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 67a7a77e2eSThierry Reding clock-names = "serial"; 687bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 69a7a77e2eSThierry Reding reset-names = "serial"; 70a7a77e2eSThierry Reding status = "disabled"; 71a7a77e2eSThierry Reding }; 72a7a77e2eSThierry Reding 73a7a77e2eSThierry Reding uartb: serial@3110000 { 74a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 75a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 76a7a77e2eSThierry Reding reg-shift = <2>; 77a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 78c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 79a7a77e2eSThierry Reding clock-names = "serial"; 807bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 81a7a77e2eSThierry Reding reset-names = "serial"; 82a7a77e2eSThierry Reding status = "disabled"; 83a7a77e2eSThierry Reding }; 84a7a77e2eSThierry Reding 85a7a77e2eSThierry Reding uartd: serial@3130000 { 86a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 87a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 88a7a77e2eSThierry Reding reg-shift = <2>; 89a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 90c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 91a7a77e2eSThierry Reding clock-names = "serial"; 927bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 93a7a77e2eSThierry Reding reset-names = "serial"; 94a7a77e2eSThierry Reding status = "disabled"; 95a7a77e2eSThierry Reding }; 96a7a77e2eSThierry Reding 97a7a77e2eSThierry Reding uarte: serial@3140000 { 98a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 99a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 100a7a77e2eSThierry Reding reg-shift = <2>; 101a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 102c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 103a7a77e2eSThierry Reding clock-names = "serial"; 1047bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 105a7a77e2eSThierry Reding reset-names = "serial"; 106a7a77e2eSThierry Reding status = "disabled"; 107a7a77e2eSThierry Reding }; 108a7a77e2eSThierry Reding 109a7a77e2eSThierry Reding uartf: serial@3150000 { 110a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 111a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 112a7a77e2eSThierry Reding reg-shift = <2>; 113a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 114c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 115a7a77e2eSThierry Reding clock-names = "serial"; 1167bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 117a7a77e2eSThierry Reding reset-names = "serial"; 11839cb62cbSJoseph Lo status = "disabled"; 11939cb62cbSJoseph Lo }; 12039cb62cbSJoseph Lo 12140cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 12240cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 12340cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 12440cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 12540cc83b3SThierry Reding #address-cells = <1>; 12640cc83b3SThierry Reding #size-cells = <0>; 127c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 12840cc83b3SThierry Reding clock-names = "div-clk"; 1297bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 13040cc83b3SThierry Reding reset-names = "i2c"; 13140cc83b3SThierry Reding status = "disabled"; 13240cc83b3SThierry Reding }; 13340cc83b3SThierry Reding 13440cc83b3SThierry Reding cam_i2c: i2c@3180000 { 13540cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 13640cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 13740cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 13840cc83b3SThierry Reding #address-cells = <1>; 13940cc83b3SThierry Reding #size-cells = <0>; 140c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 14140cc83b3SThierry Reding clock-names = "div-clk"; 1427bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 14340cc83b3SThierry Reding reset-names = "i2c"; 14440cc83b3SThierry Reding status = "disabled"; 14540cc83b3SThierry Reding }; 14640cc83b3SThierry Reding 14740cc83b3SThierry Reding /* shares pads with dpaux1 */ 14840cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 14940cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 15040cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 15140cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 15240cc83b3SThierry Reding #address-cells = <1>; 15340cc83b3SThierry Reding #size-cells = <0>; 154c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 15540cc83b3SThierry Reding clock-names = "div-clk"; 1567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 15740cc83b3SThierry Reding reset-names = "i2c"; 15840cc83b3SThierry Reding status = "disabled"; 15940cc83b3SThierry Reding }; 16040cc83b3SThierry Reding 16140cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 16240cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 16340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 16440cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 16540cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 16640cc83b3SThierry Reding #address-cells = <1>; 16740cc83b3SThierry Reding #size-cells = <0>; 168c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 16940cc83b3SThierry Reding clock-names = "div-clk"; 1707bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 17140cc83b3SThierry Reding reset-names = "i2c"; 17240cc83b3SThierry Reding status = "disabled"; 17340cc83b3SThierry Reding }; 17440cc83b3SThierry Reding 17540cc83b3SThierry Reding /* shares pads with dpaux0 */ 17640cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 17740cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 17840cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 17940cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 18040cc83b3SThierry Reding #address-cells = <1>; 18140cc83b3SThierry Reding #size-cells = <0>; 182c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 18340cc83b3SThierry Reding clock-names = "div-clk"; 1847bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 18540cc83b3SThierry Reding reset-names = "i2c"; 18640cc83b3SThierry Reding status = "disabled"; 18740cc83b3SThierry Reding }; 18840cc83b3SThierry Reding 18940cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 19040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 19140cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 19240cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 19340cc83b3SThierry Reding #address-cells = <1>; 19440cc83b3SThierry Reding #size-cells = <0>; 195c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 19640cc83b3SThierry Reding clock-names = "div-clk"; 1977bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 19840cc83b3SThierry Reding reset-names = "i2c"; 19940cc83b3SThierry Reding status = "disabled"; 20040cc83b3SThierry Reding }; 20140cc83b3SThierry Reding 20240cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 20340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 20440cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 20540cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 20640cc83b3SThierry Reding #address-cells = <1>; 20740cc83b3SThierry Reding #size-cells = <0>; 208c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 20940cc83b3SThierry Reding clock-names = "div-clk"; 2107bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 21140cc83b3SThierry Reding reset-names = "i2c"; 21240cc83b3SThierry Reding status = "disabled"; 21340cc83b3SThierry Reding }; 21440cc83b3SThierry Reding 21599425dfdSThierry Reding sdmmc1: sdhci@3400000 { 21699425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 21799425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 21899425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 219c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 22099425dfdSThierry Reding clock-names = "sdhci"; 2217bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 22299425dfdSThierry Reding reset-names = "sdhci"; 22399425dfdSThierry Reding status = "disabled"; 22499425dfdSThierry Reding }; 22599425dfdSThierry Reding 22699425dfdSThierry Reding sdmmc2: sdhci@3420000 { 22799425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 22899425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 22999425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 230c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 23199425dfdSThierry Reding clock-names = "sdhci"; 2327bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 23399425dfdSThierry Reding reset-names = "sdhci"; 23499425dfdSThierry Reding status = "disabled"; 23599425dfdSThierry Reding }; 23699425dfdSThierry Reding 23799425dfdSThierry Reding sdmmc3: sdhci@3440000 { 23899425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 23999425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 24099425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 241c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 24299425dfdSThierry Reding clock-names = "sdhci"; 2437bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 24499425dfdSThierry Reding reset-names = "sdhci"; 24599425dfdSThierry Reding status = "disabled"; 24699425dfdSThierry Reding }; 24799425dfdSThierry Reding 24899425dfdSThierry Reding sdmmc4: sdhci@3460000 { 24999425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 25099425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 25199425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 252c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 25399425dfdSThierry Reding clock-names = "sdhci"; 2547bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 25599425dfdSThierry Reding reset-names = "sdhci"; 25699425dfdSThierry Reding status = "disabled"; 25799425dfdSThierry Reding }; 25899425dfdSThierry Reding 25939cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 26039cb62cbSJoseph Lo compatible = "arm,gic-400"; 26139cb62cbSJoseph Lo #interrupt-cells = <3>; 26239cb62cbSJoseph Lo interrupt-controller; 26339cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 26439cb62cbSJoseph Lo <0x0 0x03882000 0x0 0x2000>; 26539cb62cbSJoseph Lo interrupts = <GIC_PPI 9 26639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 26739cb62cbSJoseph Lo interrupt-parent = <&gic>; 26839cb62cbSJoseph Lo }; 26939cb62cbSJoseph Lo 27039cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 27139cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 27239cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 27339cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 27439cb62cbSJoseph Lo interrupt-names = "doorbell"; 27539cb62cbSJoseph Lo #mbox-cells = <2>; 27639cb62cbSJoseph Lo status = "disabled"; 27739cb62cbSJoseph Lo }; 27839cb62cbSJoseph Lo 27940cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 28040cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 28140cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 28240cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 28340cc83b3SThierry Reding #address-cells = <1>; 28440cc83b3SThierry Reding #size-cells = <0>; 285c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 28640cc83b3SThierry Reding clock-names = "div-clk"; 2877bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 28840cc83b3SThierry Reding reset-names = "i2c"; 28940cc83b3SThierry Reding status = "disabled"; 29040cc83b3SThierry Reding }; 29140cc83b3SThierry Reding 29240cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 29340cc83b3SThierry Reding compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 29440cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 29540cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 29640cc83b3SThierry Reding #address-cells = <1>; 29740cc83b3SThierry Reding #size-cells = <0>; 298c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 29940cc83b3SThierry Reding clock-names = "div-clk"; 3007bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 30140cc83b3SThierry Reding reset-names = "i2c"; 30240cc83b3SThierry Reding status = "disabled"; 30340cc83b3SThierry Reding }; 30440cc83b3SThierry Reding 305a7a77e2eSThierry Reding uartc: serial@c280000 { 306a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 307a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 308a7a77e2eSThierry Reding reg-shift = <2>; 309a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 310c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 311a7a77e2eSThierry Reding clock-names = "serial"; 3127bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 313a7a77e2eSThierry Reding reset-names = "serial"; 314a7a77e2eSThierry Reding status = "disabled"; 315a7a77e2eSThierry Reding }; 316a7a77e2eSThierry Reding 317a7a77e2eSThierry Reding uartg: serial@c290000 { 318a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 319a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 320a7a77e2eSThierry Reding reg-shift = <2>; 321a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 322c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 323a7a77e2eSThierry Reding clock-names = "serial"; 3247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 325a7a77e2eSThierry Reding reset-names = "serial"; 326a7a77e2eSThierry Reding status = "disabled"; 327a7a77e2eSThierry Reding }; 328a7a77e2eSThierry Reding 329fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 330fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 331fc4bb754SThierry Reding reg-names = "security", "gpio"; 332fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 333fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 334fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 335fc4bb754SThierry Reding gpio-controller; 336fc4bb754SThierry Reding #gpio-cells = <2>; 337fc4bb754SThierry Reding interrupt-controller; 338fc4bb754SThierry Reding #interrupt-cells = <2>; 339fc4bb754SThierry Reding }; 340fc4bb754SThierry Reding 34173bf90d4SThierry Reding pmc@c360000 { 34273bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 34373bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 34473bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 34573bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 34673bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 34773bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 34873bf90d4SThierry Reding }; 34973bf90d4SThierry Reding 35039cb62cbSJoseph Lo sysram@30000000 { 35139cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 35239cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 35339cb62cbSJoseph Lo #address-cells = <2>; 35439cb62cbSJoseph Lo #size-cells = <2>; 35539cb62cbSJoseph Lo ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 35639cb62cbSJoseph Lo 35739cb62cbSJoseph Lo cpu_bpmp_tx: shmem@4e000 { 35839cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 35939cb62cbSJoseph Lo reg = <0x0 0x4e000 0x0 0x1000>; 36039cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 36139cb62cbSJoseph Lo pool; 36239cb62cbSJoseph Lo }; 36339cb62cbSJoseph Lo 36439cb62cbSJoseph Lo cpu_bpmp_rx: shmem@4f000 { 36539cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-shmem"; 36639cb62cbSJoseph Lo reg = <0x0 0x4f000 0x0 0x1000>; 36739cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 36839cb62cbSJoseph Lo pool; 36939cb62cbSJoseph Lo }; 37039cb62cbSJoseph Lo }; 37139cb62cbSJoseph Lo 372cd6fe32eSThierry Reding cpus { 373cd6fe32eSThierry Reding #address-cells = <1>; 374cd6fe32eSThierry Reding #size-cells = <0>; 375cd6fe32eSThierry Reding 376cd6fe32eSThierry Reding cpu@0 { 377cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 378cd6fe32eSThierry Reding device_type = "cpu"; 379cd6fe32eSThierry Reding reg = <0x000>; 380cd6fe32eSThierry Reding }; 381cd6fe32eSThierry Reding 382cd6fe32eSThierry Reding cpu@1 { 383cd6fe32eSThierry Reding compatible = "nvidia,tegra186-denver", "arm,armv8"; 384cd6fe32eSThierry Reding device_type = "cpu"; 385cd6fe32eSThierry Reding reg = <0x001>; 386cd6fe32eSThierry Reding }; 387cd6fe32eSThierry Reding 388cd6fe32eSThierry Reding cpu@2 { 389cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 390cd6fe32eSThierry Reding device_type = "cpu"; 391cd6fe32eSThierry Reding reg = <0x100>; 392cd6fe32eSThierry Reding }; 393cd6fe32eSThierry Reding 394cd6fe32eSThierry Reding cpu@3 { 395cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 396cd6fe32eSThierry Reding device_type = "cpu"; 397cd6fe32eSThierry Reding reg = <0x101>; 398cd6fe32eSThierry Reding }; 399cd6fe32eSThierry Reding 400cd6fe32eSThierry Reding cpu@4 { 401cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 402cd6fe32eSThierry Reding device_type = "cpu"; 403cd6fe32eSThierry Reding reg = <0x102>; 404cd6fe32eSThierry Reding }; 405cd6fe32eSThierry Reding 406cd6fe32eSThierry Reding cpu@5 { 407cd6fe32eSThierry Reding compatible = "arm,cortex-a57", "arm,armv8"; 408cd6fe32eSThierry Reding device_type = "cpu"; 409cd6fe32eSThierry Reding reg = <0x103>; 410cd6fe32eSThierry Reding }; 411cd6fe32eSThierry Reding }; 412cd6fe32eSThierry Reding 41339cb62cbSJoseph Lo bpmp: bpmp { 41439cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp"; 4155edcebb9SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 4165edcebb9SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 41739cb62cbSJoseph Lo shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 41839cb62cbSJoseph Lo #clock-cells = <1>; 41939cb62cbSJoseph Lo #reset-cells = <1>; 42039cb62cbSJoseph Lo 42139cb62cbSJoseph Lo bpmp_i2c: i2c { 42239cb62cbSJoseph Lo compatible = "nvidia,tegra186-bpmp-i2c"; 42339cb62cbSJoseph Lo nvidia,bpmp-bus-id = <5>; 42439cb62cbSJoseph Lo #address-cells = <1>; 42539cb62cbSJoseph Lo #size-cells = <0>; 42639cb62cbSJoseph Lo status = "disabled"; 42739cb62cbSJoseph Lo }; 42839cb62cbSJoseph Lo }; 42939cb62cbSJoseph Lo 43039cb62cbSJoseph Lo timer { 43139cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 43239cb62cbSJoseph Lo interrupts = <GIC_PPI 13 43339cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43439cb62cbSJoseph Lo <GIC_PPI 14 43539cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43639cb62cbSJoseph Lo <GIC_PPI 11 43739cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 43839cb62cbSJoseph Lo <GIC_PPI 10 43939cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 44039cb62cbSJoseph Lo interrupt-parent = <&gic>; 44139cb62cbSJoseph Lo }; 44239cb62cbSJoseph Lo}; 443