1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 2c58f5f88SThierry Reding#include <dt-bindings/clock/tegra186-clock.h> 3fc4bb754SThierry Reding#include <dt-bindings/gpio/tegra186-gpio.h> 439cb62cbSJoseph Lo#include <dt-bindings/interrupt-controller/arm-gic.h> 55edcebb9SThierry Reding#include <dt-bindings/mailbox/tegra186-hsp.h> 6d25a3bf1SThierry Reding#include <dt-bindings/memory/tegra186-mc.h> 724005fd1SAapo Vienamo#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8dfd7a384SAlexandre Courbot#include <dt-bindings/power/tegra186-powergate.h> 97bcf2664SThierry Reding#include <dt-bindings/reset/tegra186-reset.h> 1015274c23SMikko Perttunen#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 1139cb62cbSJoseph Lo 1239cb62cbSJoseph Lo/ { 1339cb62cbSJoseph Lo compatible = "nvidia,tegra186"; 1439cb62cbSJoseph Lo interrupt-parent = <&gic>; 1539cb62cbSJoseph Lo #address-cells = <2>; 1639cb62cbSJoseph Lo #size-cells = <2>; 1739cb62cbSJoseph Lo 1894e25dc3SThierry Reding misc@100000 { 1994e25dc3SThierry Reding compatible = "nvidia,tegra186-misc"; 2094e25dc3SThierry Reding reg = <0x0 0x00100000 0x0 0xf000>, 2194e25dc3SThierry Reding <0x0 0x0010f000 0x0 0x1000>; 2294e25dc3SThierry Reding }; 2394e25dc3SThierry Reding 24fc4bb754SThierry Reding gpio: gpio@2200000 { 25fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio"; 26fc4bb754SThierry Reding reg-names = "security", "gpio"; 27fc4bb754SThierry Reding reg = <0x0 0x2200000 0x0 0x10000>, 28fc4bb754SThierry Reding <0x0 0x2210000 0x0 0x10000>; 29fc4bb754SThierry Reding interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30fc4bb754SThierry Reding <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31fc4bb754SThierry Reding <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32fc4bb754SThierry Reding <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33fc4bb754SThierry Reding <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34fc4bb754SThierry Reding <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35fc4bb754SThierry Reding #interrupt-cells = <2>; 36fc4bb754SThierry Reding interrupt-controller; 37fc4bb754SThierry Reding #gpio-cells = <2>; 38fc4bb754SThierry Reding gpio-controller; 39fc4bb754SThierry Reding }; 40fc4bb754SThierry Reding 410caafbdeSThierry Reding ethernet@2490000 { 420caafbdeSThierry Reding compatible = "nvidia,tegra186-eqos", 430caafbdeSThierry Reding "snps,dwc-qos-ethernet-4.10"; 440caafbdeSThierry Reding reg = <0x0 0x02490000 0x0 0x10000>; 450caafbdeSThierry Reding interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 460caafbdeSThierry Reding <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 470caafbdeSThierry Reding <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 480caafbdeSThierry Reding <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 490caafbdeSThierry Reding <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 500caafbdeSThierry Reding <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 510caafbdeSThierry Reding <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 520caafbdeSThierry Reding <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 530caafbdeSThierry Reding <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 540caafbdeSThierry Reding <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 550caafbdeSThierry Reding clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 560caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_AXI>, 570caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_RX>, 580caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_TX>, 590caafbdeSThierry Reding <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 600caafbdeSThierry Reding clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 610caafbdeSThierry Reding resets = <&bpmp TEGRA186_RESET_EQOS>; 620caafbdeSThierry Reding reset-names = "eqos"; 63954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 66dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_EQOS>; 670caafbdeSThierry Reding status = "disabled"; 680caafbdeSThierry Reding 690caafbdeSThierry Reding snps,write-requests = <1>; 700caafbdeSThierry Reding snps,read-requests = <3>; 710caafbdeSThierry Reding snps,burst-map = <0x7>; 720caafbdeSThierry Reding snps,txpbl = <32>; 730caafbdeSThierry Reding snps,rxpbl = <8>; 740caafbdeSThierry Reding }; 750caafbdeSThierry Reding 76835553b3SAkhil R gpcdma: dma-controller@2600000 { 77835553b3SAkhil R compatible = "nvidia,tegra186-gpcdma"; 78835553b3SAkhil R reg = <0x0 0x2600000 0x0 0x210000>; 79835553b3SAkhil R resets = <&bpmp TEGRA186_RESET_GPCDMA>; 80835553b3SAkhil R reset-names = "gpcdma"; 81835553b3SAkhil R interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 82835553b3SAkhil R <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 83835553b3SAkhil R <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 84835553b3SAkhil R <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 85835553b3SAkhil R <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 86835553b3SAkhil R <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 87835553b3SAkhil R <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 88835553b3SAkhil R <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 89835553b3SAkhil R <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 90835553b3SAkhil R <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 91835553b3SAkhil R <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 92835553b3SAkhil R <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 93835553b3SAkhil R <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 94835553b3SAkhil R <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 95835553b3SAkhil R <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 96835553b3SAkhil R <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 97835553b3SAkhil R <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 98835553b3SAkhil R <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 99835553b3SAkhil R <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 100835553b3SAkhil R <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 101835553b3SAkhil R <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 102835553b3SAkhil R <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 103835553b3SAkhil R <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 104835553b3SAkhil R <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 105835553b3SAkhil R <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 106835553b3SAkhil R <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 107835553b3SAkhil R <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 108835553b3SAkhil R <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 109835553b3SAkhil R <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 110835553b3SAkhil R <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 111835553b3SAkhil R <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 112835553b3SAkhil R #dma-cells = <1>; 113835553b3SAkhil R iommus = <&smmu TEGRA186_SID_GPCDMA_0>; 114835553b3SAkhil R dma-coherent; 115835553b3SAkhil R status = "okay"; 116835553b3SAkhil R }; 117835553b3SAkhil R 1184b154b94SThierry Reding aconnect@2900000 { 1195d2249ddSSameer Pujar compatible = "nvidia,tegra186-aconnect", 1205d2249ddSSameer Pujar "nvidia,tegra210-aconnect"; 1215d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>, 1225d2249ddSSameer Pujar <&bpmp TEGRA186_CLK_APB2APE>; 1235d2249ddSSameer Pujar clock-names = "ape", "apb2ape"; 1245d2249ddSSameer Pujar power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 1255d2249ddSSameer Pujar #address-cells = <1>; 1265d2249ddSSameer Pujar #size-cells = <1>; 1275d2249ddSSameer Pujar ranges = <0x02900000 0x0 0x02900000 0x200000>; 1285d2249ddSSameer Pujar status = "disabled"; 1295d2249ddSSameer Pujar 130177208f7SSameer Pujar adma: dma-controller@2930000 { 1315d2249ddSSameer Pujar compatible = "nvidia,tegra186-adma"; 1325d2249ddSSameer Pujar reg = <0x02930000 0x20000>; 1335d2249ddSSameer Pujar interrupt-parent = <&agic>; 1345d2249ddSSameer Pujar interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1355d2249ddSSameer Pujar <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1365d2249ddSSameer Pujar <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1375d2249ddSSameer Pujar <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1385d2249ddSSameer Pujar <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1395d2249ddSSameer Pujar <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1405d2249ddSSameer Pujar <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1415d2249ddSSameer Pujar <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1425d2249ddSSameer Pujar <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1435d2249ddSSameer Pujar <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1445d2249ddSSameer Pujar <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1455d2249ddSSameer Pujar <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1465d2249ddSSameer Pujar <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1475d2249ddSSameer Pujar <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1485d2249ddSSameer Pujar <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1495d2249ddSSameer Pujar <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1505d2249ddSSameer Pujar <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1515d2249ddSSameer Pujar <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1525d2249ddSSameer Pujar <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1535d2249ddSSameer Pujar <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1545d2249ddSSameer Pujar <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1555d2249ddSSameer Pujar <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1565d2249ddSSameer Pujar <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1575d2249ddSSameer Pujar <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1585d2249ddSSameer Pujar <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1595d2249ddSSameer Pujar <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1605d2249ddSSameer Pujar <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1615d2249ddSSameer Pujar <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1625d2249ddSSameer Pujar <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1635d2249ddSSameer Pujar <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1645d2249ddSSameer Pujar <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1655d2249ddSSameer Pujar <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1665d2249ddSSameer Pujar #dma-cells = <1>; 1675d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 1685d2249ddSSameer Pujar clock-names = "d_audio"; 1695d2249ddSSameer Pujar status = "disabled"; 1705d2249ddSSameer Pujar }; 1715d2249ddSSameer Pujar 1725d2249ddSSameer Pujar agic: interrupt-controller@2a40000 { 1735d2249ddSSameer Pujar compatible = "nvidia,tegra186-agic", 1745d2249ddSSameer Pujar "nvidia,tegra210-agic"; 1755d2249ddSSameer Pujar #interrupt-cells = <3>; 1765d2249ddSSameer Pujar interrupt-controller; 1775d2249ddSSameer Pujar reg = <0x02a41000 0x1000>, 1785d2249ddSSameer Pujar <0x02a42000 0x2000>; 1795d2249ddSSameer Pujar interrupts = <GIC_SPI 145 1805d2249ddSSameer Pujar (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1815d2249ddSSameer Pujar clocks = <&bpmp TEGRA186_CLK_APE>; 1825d2249ddSSameer Pujar clock-names = "clk"; 1835d2249ddSSameer Pujar status = "disabled"; 1845d2249ddSSameer Pujar }; 185177208f7SSameer Pujar 186177208f7SSameer Pujar tegra_ahub: ahub@2900800 { 187177208f7SSameer Pujar compatible = "nvidia,tegra186-ahub"; 188177208f7SSameer Pujar reg = <0x02900800 0x800>; 189177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_AHUB>; 190177208f7SSameer Pujar clock-names = "ahub"; 191177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 192177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 193177208f7SSameer Pujar #address-cells = <1>; 194177208f7SSameer Pujar #size-cells = <1>; 195177208f7SSameer Pujar ranges = <0x02900800 0x02900800 0x11800>; 196177208f7SSameer Pujar status = "disabled"; 197177208f7SSameer Pujar 198177208f7SSameer Pujar tegra_admaif: admaif@290f000 { 199177208f7SSameer Pujar compatible = "nvidia,tegra186-admaif"; 200177208f7SSameer Pujar reg = <0x0290f000 0x1000>; 201177208f7SSameer Pujar dmas = <&adma 1>, <&adma 1>, 202177208f7SSameer Pujar <&adma 2>, <&adma 2>, 203177208f7SSameer Pujar <&adma 3>, <&adma 3>, 204177208f7SSameer Pujar <&adma 4>, <&adma 4>, 205177208f7SSameer Pujar <&adma 5>, <&adma 5>, 206177208f7SSameer Pujar <&adma 6>, <&adma 6>, 207177208f7SSameer Pujar <&adma 7>, <&adma 7>, 208177208f7SSameer Pujar <&adma 8>, <&adma 8>, 209177208f7SSameer Pujar <&adma 9>, <&adma 9>, 210177208f7SSameer Pujar <&adma 10>, <&adma 10>, 211177208f7SSameer Pujar <&adma 11>, <&adma 11>, 212177208f7SSameer Pujar <&adma 12>, <&adma 12>, 213177208f7SSameer Pujar <&adma 13>, <&adma 13>, 214177208f7SSameer Pujar <&adma 14>, <&adma 14>, 215177208f7SSameer Pujar <&adma 15>, <&adma 15>, 216177208f7SSameer Pujar <&adma 16>, <&adma 16>, 217177208f7SSameer Pujar <&adma 17>, <&adma 17>, 218177208f7SSameer Pujar <&adma 18>, <&adma 18>, 219177208f7SSameer Pujar <&adma 19>, <&adma 19>, 220177208f7SSameer Pujar <&adma 20>, <&adma 20>; 221177208f7SSameer Pujar dma-names = "rx1", "tx1", 222177208f7SSameer Pujar "rx2", "tx2", 223177208f7SSameer Pujar "rx3", "tx3", 224177208f7SSameer Pujar "rx4", "tx4", 225177208f7SSameer Pujar "rx5", "tx5", 226177208f7SSameer Pujar "rx6", "tx6", 227177208f7SSameer Pujar "rx7", "tx7", 228177208f7SSameer Pujar "rx8", "tx8", 229177208f7SSameer Pujar "rx9", "tx9", 230177208f7SSameer Pujar "rx10", "tx10", 231177208f7SSameer Pujar "rx11", "tx11", 232177208f7SSameer Pujar "rx12", "tx12", 233177208f7SSameer Pujar "rx13", "tx13", 234177208f7SSameer Pujar "rx14", "tx14", 235177208f7SSameer Pujar "rx15", "tx15", 236177208f7SSameer Pujar "rx16", "tx16", 237177208f7SSameer Pujar "rx17", "tx17", 238177208f7SSameer Pujar "rx18", "tx18", 239177208f7SSameer Pujar "rx19", "tx19", 240177208f7SSameer Pujar "rx20", "tx20"; 241177208f7SSameer Pujar status = "disabled"; 242177208f7SSameer Pujar }; 243177208f7SSameer Pujar 244177208f7SSameer Pujar tegra_i2s1: i2s@2901000 { 245177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 246177208f7SSameer Pujar "nvidia,tegra210-i2s"; 247177208f7SSameer Pujar reg = <0x2901000 0x100>; 248177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S1>, 249177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 250177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 251177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 252177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253177208f7SSameer Pujar assigned-clock-rates = <1536000>; 254177208f7SSameer Pujar sound-name-prefix = "I2S1"; 255177208f7SSameer Pujar status = "disabled"; 256177208f7SSameer Pujar }; 257177208f7SSameer Pujar 258177208f7SSameer Pujar tegra_i2s2: i2s@2901100 { 259177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 260177208f7SSameer Pujar "nvidia,tegra210-i2s"; 261177208f7SSameer Pujar reg = <0x2901100 0x100>; 262177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S2>, 263177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 264177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 265177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 266177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267177208f7SSameer Pujar assigned-clock-rates = <1536000>; 268177208f7SSameer Pujar sound-name-prefix = "I2S2"; 269177208f7SSameer Pujar status = "disabled"; 270177208f7SSameer Pujar }; 271177208f7SSameer Pujar 272177208f7SSameer Pujar tegra_i2s3: i2s@2901200 { 273177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 274177208f7SSameer Pujar "nvidia,tegra210-i2s"; 275177208f7SSameer Pujar reg = <0x2901200 0x100>; 276177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S3>, 277177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 278177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 279177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 280177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281177208f7SSameer Pujar assigned-clock-rates = <1536000>; 282177208f7SSameer Pujar sound-name-prefix = "I2S3"; 283177208f7SSameer Pujar status = "disabled"; 284177208f7SSameer Pujar }; 285177208f7SSameer Pujar 286177208f7SSameer Pujar tegra_i2s4: i2s@2901300 { 287177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 288177208f7SSameer Pujar "nvidia,tegra210-i2s"; 289177208f7SSameer Pujar reg = <0x2901300 0x100>; 290177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S4>, 291177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 292177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 293177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 294177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 295177208f7SSameer Pujar assigned-clock-rates = <1536000>; 296177208f7SSameer Pujar sound-name-prefix = "I2S4"; 297177208f7SSameer Pujar status = "disabled"; 298177208f7SSameer Pujar }; 299177208f7SSameer Pujar 300177208f7SSameer Pujar tegra_i2s5: i2s@2901400 { 301177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 302177208f7SSameer Pujar "nvidia,tegra210-i2s"; 303177208f7SSameer Pujar reg = <0x2901400 0x100>; 304177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S5>, 305177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 306177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 307177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 308177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 309177208f7SSameer Pujar assigned-clock-rates = <1536000>; 310177208f7SSameer Pujar sound-name-prefix = "I2S5"; 311177208f7SSameer Pujar status = "disabled"; 312177208f7SSameer Pujar }; 313177208f7SSameer Pujar 314177208f7SSameer Pujar tegra_i2s6: i2s@2901500 { 315177208f7SSameer Pujar compatible = "nvidia,tegra186-i2s", 316177208f7SSameer Pujar "nvidia,tegra210-i2s"; 317177208f7SSameer Pujar reg = <0x2901500 0x100>; 318177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_I2S6>, 319177208f7SSameer Pujar <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 320177208f7SSameer Pujar clock-names = "i2s", "sync_input"; 321177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 322177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 323177208f7SSameer Pujar assigned-clock-rates = <1536000>; 324177208f7SSameer Pujar sound-name-prefix = "I2S6"; 325177208f7SSameer Pujar status = "disabled"; 326177208f7SSameer Pujar }; 327177208f7SSameer Pujar 328177208f7SSameer Pujar tegra_dmic1: dmic@2904000 { 329177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 330177208f7SSameer Pujar reg = <0x2904000 0x100>; 331177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC1>; 332177208f7SSameer Pujar clock-names = "dmic"; 333177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 334177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 335177208f7SSameer Pujar assigned-clock-rates = <3072000>; 336177208f7SSameer Pujar sound-name-prefix = "DMIC1"; 337177208f7SSameer Pujar status = "disabled"; 338177208f7SSameer Pujar }; 339177208f7SSameer Pujar 340177208f7SSameer Pujar tegra_dmic2: dmic@2904100 { 341177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 342177208f7SSameer Pujar reg = <0x2904100 0x100>; 343177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC2>; 344177208f7SSameer Pujar clock-names = "dmic"; 345177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 346177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 347177208f7SSameer Pujar assigned-clock-rates = <3072000>; 348177208f7SSameer Pujar sound-name-prefix = "DMIC2"; 349177208f7SSameer Pujar status = "disabled"; 350177208f7SSameer Pujar }; 351177208f7SSameer Pujar 352177208f7SSameer Pujar tegra_dmic3: dmic@2904200 { 353177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 354177208f7SSameer Pujar reg = <0x2904200 0x100>; 355177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC3>; 356177208f7SSameer Pujar clock-names = "dmic"; 357177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 358177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 359177208f7SSameer Pujar assigned-clock-rates = <3072000>; 360177208f7SSameer Pujar sound-name-prefix = "DMIC3"; 361177208f7SSameer Pujar status = "disabled"; 362177208f7SSameer Pujar }; 363177208f7SSameer Pujar 364177208f7SSameer Pujar tegra_dmic4: dmic@2904300 { 365177208f7SSameer Pujar compatible = "nvidia,tegra210-dmic"; 366177208f7SSameer Pujar reg = <0x2904300 0x100>; 367177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DMIC4>; 368177208f7SSameer Pujar clock-names = "dmic"; 369177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 370177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 371177208f7SSameer Pujar assigned-clock-rates = <3072000>; 372177208f7SSameer Pujar sound-name-prefix = "DMIC4"; 373177208f7SSameer Pujar status = "disabled"; 374177208f7SSameer Pujar }; 375177208f7SSameer Pujar 376177208f7SSameer Pujar tegra_dspk1: dspk@2905000 { 377177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 378177208f7SSameer Pujar reg = <0x2905000 0x100>; 379177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK1>; 380177208f7SSameer Pujar clock-names = "dspk"; 381177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 382177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 383177208f7SSameer Pujar assigned-clock-rates = <12288000>; 384177208f7SSameer Pujar sound-name-prefix = "DSPK1"; 385177208f7SSameer Pujar status = "disabled"; 386177208f7SSameer Pujar }; 387177208f7SSameer Pujar 388177208f7SSameer Pujar tegra_dspk2: dspk@2905100 { 389177208f7SSameer Pujar compatible = "nvidia,tegra186-dspk"; 390177208f7SSameer Pujar reg = <0x2905100 0x100>; 391177208f7SSameer Pujar clocks = <&bpmp TEGRA186_CLK_DSPK2>; 392177208f7SSameer Pujar clock-names = "dspk"; 393177208f7SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 394177208f7SSameer Pujar assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 395177208f7SSameer Pujar assigned-clock-rates = <12288000>; 396177208f7SSameer Pujar sound-name-prefix = "DSPK2"; 397177208f7SSameer Pujar status = "disabled"; 398177208f7SSameer Pujar }; 399848f3290SSameer Pujar 400848f3290SSameer Pujar tegra_sfc1: sfc@2902000 { 401848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 402848f3290SSameer Pujar "nvidia,tegra210-sfc"; 403848f3290SSameer Pujar reg = <0x2902000 0x200>; 404848f3290SSameer Pujar sound-name-prefix = "SFC1"; 405848f3290SSameer Pujar status = "disabled"; 406848f3290SSameer Pujar }; 407848f3290SSameer Pujar 408848f3290SSameer Pujar tegra_sfc2: sfc@2902200 { 409848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 410848f3290SSameer Pujar "nvidia,tegra210-sfc"; 411848f3290SSameer Pujar reg = <0x2902200 0x200>; 412848f3290SSameer Pujar sound-name-prefix = "SFC2"; 413848f3290SSameer Pujar status = "disabled"; 414848f3290SSameer Pujar }; 415848f3290SSameer Pujar 416848f3290SSameer Pujar tegra_sfc3: sfc@2902400 { 417848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 418848f3290SSameer Pujar "nvidia,tegra210-sfc"; 419848f3290SSameer Pujar reg = <0x2902400 0x200>; 420848f3290SSameer Pujar sound-name-prefix = "SFC3"; 421848f3290SSameer Pujar status = "disabled"; 422848f3290SSameer Pujar }; 423848f3290SSameer Pujar 424848f3290SSameer Pujar tegra_sfc4: sfc@2902600 { 425848f3290SSameer Pujar compatible = "nvidia,tegra186-sfc", 426848f3290SSameer Pujar "nvidia,tegra210-sfc"; 427848f3290SSameer Pujar reg = <0x2902600 0x200>; 428848f3290SSameer Pujar sound-name-prefix = "SFC4"; 429848f3290SSameer Pujar status = "disabled"; 430848f3290SSameer Pujar }; 431848f3290SSameer Pujar 432848f3290SSameer Pujar tegra_mvc1: mvc@290a000 { 433848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 434848f3290SSameer Pujar "nvidia,tegra210-mvc"; 435848f3290SSameer Pujar reg = <0x290a000 0x200>; 436848f3290SSameer Pujar sound-name-prefix = "MVC1"; 437848f3290SSameer Pujar status = "disabled"; 438848f3290SSameer Pujar }; 439848f3290SSameer Pujar 440848f3290SSameer Pujar tegra_mvc2: mvc@290a200 { 441848f3290SSameer Pujar compatible = "nvidia,tegra186-mvc", 442848f3290SSameer Pujar "nvidia,tegra210-mvc"; 443848f3290SSameer Pujar reg = <0x290a200 0x200>; 444848f3290SSameer Pujar sound-name-prefix = "MVC2"; 445848f3290SSameer Pujar status = "disabled"; 446848f3290SSameer Pujar }; 447848f3290SSameer Pujar 448848f3290SSameer Pujar tegra_amx1: amx@2903000 { 449848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 450848f3290SSameer Pujar "nvidia,tegra210-amx"; 451848f3290SSameer Pujar reg = <0x2903000 0x100>; 452848f3290SSameer Pujar sound-name-prefix = "AMX1"; 453848f3290SSameer Pujar status = "disabled"; 454848f3290SSameer Pujar }; 455848f3290SSameer Pujar 456848f3290SSameer Pujar tegra_amx2: amx@2903100 { 457848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 458848f3290SSameer Pujar "nvidia,tegra210-amx"; 459848f3290SSameer Pujar reg = <0x2903100 0x100>; 460848f3290SSameer Pujar sound-name-prefix = "AMX2"; 461848f3290SSameer Pujar status = "disabled"; 462848f3290SSameer Pujar }; 463848f3290SSameer Pujar 464848f3290SSameer Pujar tegra_amx3: amx@2903200 { 465848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 466848f3290SSameer Pujar "nvidia,tegra210-amx"; 467848f3290SSameer Pujar reg = <0x2903200 0x100>; 468848f3290SSameer Pujar sound-name-prefix = "AMX3"; 469848f3290SSameer Pujar status = "disabled"; 470848f3290SSameer Pujar }; 471848f3290SSameer Pujar 472848f3290SSameer Pujar tegra_amx4: amx@2903300 { 473848f3290SSameer Pujar compatible = "nvidia,tegra186-amx", 474848f3290SSameer Pujar "nvidia,tegra210-amx"; 475848f3290SSameer Pujar reg = <0x2903300 0x100>; 476848f3290SSameer Pujar sound-name-prefix = "AMX4"; 477848f3290SSameer Pujar status = "disabled"; 478848f3290SSameer Pujar }; 479848f3290SSameer Pujar 480848f3290SSameer Pujar tegra_adx1: adx@2903800 { 481848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 482848f3290SSameer Pujar "nvidia,tegra210-adx"; 483848f3290SSameer Pujar reg = <0x2903800 0x100>; 484848f3290SSameer Pujar sound-name-prefix = "ADX1"; 485848f3290SSameer Pujar status = "disabled"; 486848f3290SSameer Pujar }; 487848f3290SSameer Pujar 488848f3290SSameer Pujar tegra_adx2: adx@2903900 { 489848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 490848f3290SSameer Pujar "nvidia,tegra210-adx"; 491848f3290SSameer Pujar reg = <0x2903900 0x100>; 492848f3290SSameer Pujar sound-name-prefix = "ADX2"; 493848f3290SSameer Pujar status = "disabled"; 494848f3290SSameer Pujar }; 495848f3290SSameer Pujar 496848f3290SSameer Pujar tegra_adx3: adx@2903a00 { 497848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 498848f3290SSameer Pujar "nvidia,tegra210-adx"; 499848f3290SSameer Pujar reg = <0x2903a00 0x100>; 500848f3290SSameer Pujar sound-name-prefix = "ADX3"; 501848f3290SSameer Pujar status = "disabled"; 502848f3290SSameer Pujar }; 503848f3290SSameer Pujar 504848f3290SSameer Pujar tegra_adx4: adx@2903b00 { 505848f3290SSameer Pujar compatible = "nvidia,tegra186-adx", 506848f3290SSameer Pujar "nvidia,tegra210-adx"; 507848f3290SSameer Pujar reg = <0x2903b00 0x100>; 508848f3290SSameer Pujar sound-name-prefix = "ADX4"; 509848f3290SSameer Pujar status = "disabled"; 510848f3290SSameer Pujar }; 511848f3290SSameer Pujar 512848f3290SSameer Pujar tegra_amixer: amixer@290bb00 { 513848f3290SSameer Pujar compatible = "nvidia,tegra186-amixer", 514848f3290SSameer Pujar "nvidia,tegra210-amixer"; 515848f3290SSameer Pujar reg = <0x290bb00 0x800>; 516848f3290SSameer Pujar sound-name-prefix = "MIXER1"; 517848f3290SSameer Pujar status = "disabled"; 518848f3290SSameer Pujar }; 51947a08153SSameer Pujar 52047a08153SSameer Pujar tegra_asrc: asrc@2910000 { 52147a08153SSameer Pujar compatible = "nvidia,tegra186-asrc"; 52247a08153SSameer Pujar reg = <0x2910000 0x2000>; 52347a08153SSameer Pujar sound-name-prefix = "ASRC1"; 52447a08153SSameer Pujar status = "disabled"; 52547a08153SSameer Pujar }; 526177208f7SSameer Pujar }; 5275d2249ddSSameer Pujar }; 5285d2249ddSSameer Pujar 529954490b3SThierry Reding mc: memory-controller@2c00000 { 530d25a3bf1SThierry Reding compatible = "nvidia,tegra186-mc"; 531*000b99e5SAshish Mhetre reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 532*000b99e5SAshish Mhetre <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ 533*000b99e5SAshish Mhetre <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 534*000b99e5SAshish Mhetre <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 535*000b99e5SAshish Mhetre <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 536*000b99e5SAshish Mhetre <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ 537*000b99e5SAshish Mhetre reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; 538b72d52a1SThierry Reding interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 539d25a3bf1SThierry Reding status = "disabled"; 5403f6eaef9SThierry Reding 541954490b3SThierry Reding #interconnect-cells = <1>; 5423f6eaef9SThierry Reding #address-cells = <2>; 5433f6eaef9SThierry Reding #size-cells = <2>; 5443f6eaef9SThierry Reding 5453f6eaef9SThierry Reding ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 5463f6eaef9SThierry Reding 5473f6eaef9SThierry Reding /* 5483f6eaef9SThierry Reding * Memory clients have access to all 40 bits that the memory 5493f6eaef9SThierry Reding * controller can address. 5503f6eaef9SThierry Reding */ 5513f6eaef9SThierry Reding dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 5523f6eaef9SThierry Reding 5533f6eaef9SThierry Reding emc: external-memory-controller@2c60000 { 5543f6eaef9SThierry Reding compatible = "nvidia,tegra186-emc"; 5553f6eaef9SThierry Reding reg = <0x0 0x02c60000 0x0 0x50000>; 5563f6eaef9SThierry Reding interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 5573f6eaef9SThierry Reding clocks = <&bpmp TEGRA186_CLK_EMC>; 5583f6eaef9SThierry Reding clock-names = "emc"; 5593f6eaef9SThierry Reding 560954490b3SThierry Reding #interconnect-cells = <0>; 561954490b3SThierry Reding 5623f6eaef9SThierry Reding nvidia,bpmp = <&bpmp>; 5633f6eaef9SThierry Reding }; 564d25a3bf1SThierry Reding }; 565d25a3bf1SThierry Reding 566bd1fefcbSThierry Reding timer@3010000 { 567bd1fefcbSThierry Reding compatible = "nvidia,tegra186-timer"; 568bd1fefcbSThierry Reding reg = <0x0 0x03010000 0x0 0x000e0000>; 569bd1fefcbSThierry Reding interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 570bd1fefcbSThierry Reding <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 571bd1fefcbSThierry Reding <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 572bd1fefcbSThierry Reding <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 573bd1fefcbSThierry Reding <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 574bd1fefcbSThierry Reding <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 575bd1fefcbSThierry Reding <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 576bd1fefcbSThierry Reding <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 577bd1fefcbSThierry Reding <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 578bd1fefcbSThierry Reding <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 579bd1fefcbSThierry Reding status = "disabled"; 580bd1fefcbSThierry Reding }; 581bd1fefcbSThierry Reding 58239cb62cbSJoseph Lo uarta: serial@3100000 { 58339cb62cbSJoseph Lo compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 58439cb62cbSJoseph Lo reg = <0x0 0x03100000 0x0 0x40>; 58539cb62cbSJoseph Lo reg-shift = <2>; 58639cb62cbSJoseph Lo interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 587c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTA>; 588a7a77e2eSThierry Reding clock-names = "serial"; 5897bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTA>; 590a7a77e2eSThierry Reding reset-names = "serial"; 591a7a77e2eSThierry Reding status = "disabled"; 592a7a77e2eSThierry Reding }; 593a7a77e2eSThierry Reding 594a7a77e2eSThierry Reding uartb: serial@3110000 { 595a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 596a7a77e2eSThierry Reding reg = <0x0 0x03110000 0x0 0x40>; 597a7a77e2eSThierry Reding reg-shift = <2>; 598a7a77e2eSThierry Reding interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 599c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTB>; 600a7a77e2eSThierry Reding clock-names = "serial"; 6017bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTB>; 602a7a77e2eSThierry Reding reset-names = "serial"; 603a7a77e2eSThierry Reding status = "disabled"; 604a7a77e2eSThierry Reding }; 605a7a77e2eSThierry Reding 606a7a77e2eSThierry Reding uartd: serial@3130000 { 607a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 608a7a77e2eSThierry Reding reg = <0x0 0x03130000 0x0 0x40>; 609a7a77e2eSThierry Reding reg-shift = <2>; 610a7a77e2eSThierry Reding interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 611c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTD>; 612a7a77e2eSThierry Reding clock-names = "serial"; 6137bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTD>; 614a7a77e2eSThierry Reding reset-names = "serial"; 615a7a77e2eSThierry Reding status = "disabled"; 616a7a77e2eSThierry Reding }; 617a7a77e2eSThierry Reding 618a7a77e2eSThierry Reding uarte: serial@3140000 { 619a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 620a7a77e2eSThierry Reding reg = <0x0 0x03140000 0x0 0x40>; 621a7a77e2eSThierry Reding reg-shift = <2>; 622a7a77e2eSThierry Reding interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 623c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTE>; 624a7a77e2eSThierry Reding clock-names = "serial"; 6257bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTE>; 626a7a77e2eSThierry Reding reset-names = "serial"; 627a7a77e2eSThierry Reding status = "disabled"; 628a7a77e2eSThierry Reding }; 629a7a77e2eSThierry Reding 630a7a77e2eSThierry Reding uartf: serial@3150000 { 631a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 632a7a77e2eSThierry Reding reg = <0x0 0x03150000 0x0 0x40>; 633a7a77e2eSThierry Reding reg-shift = <2>; 634a7a77e2eSThierry Reding interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 635c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTF>; 636a7a77e2eSThierry Reding clock-names = "serial"; 6377bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTF>; 638a7a77e2eSThierry Reding reset-names = "serial"; 63939cb62cbSJoseph Lo status = "disabled"; 64039cb62cbSJoseph Lo }; 64139cb62cbSJoseph Lo 64240cc83b3SThierry Reding gen1_i2c: i2c@3160000 { 643548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 64440cc83b3SThierry Reding reg = <0x0 0x03160000 0x0 0x10000>; 64540cc83b3SThierry Reding interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 64640cc83b3SThierry Reding #address-cells = <1>; 64740cc83b3SThierry Reding #size-cells = <0>; 648c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C1>; 64940cc83b3SThierry Reding clock-names = "div-clk"; 6507bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C1>; 65140cc83b3SThierry Reding reset-names = "i2c"; 65240cc83b3SThierry Reding status = "disabled"; 65340cc83b3SThierry Reding }; 65440cc83b3SThierry Reding 65540cc83b3SThierry Reding cam_i2c: i2c@3180000 { 656548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 65740cc83b3SThierry Reding reg = <0x0 0x03180000 0x0 0x10000>; 65840cc83b3SThierry Reding interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 65940cc83b3SThierry Reding #address-cells = <1>; 66040cc83b3SThierry Reding #size-cells = <0>; 661c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C3>; 66240cc83b3SThierry Reding clock-names = "div-clk"; 6637bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C3>; 66440cc83b3SThierry Reding reset-names = "i2c"; 66540cc83b3SThierry Reding status = "disabled"; 66640cc83b3SThierry Reding }; 66740cc83b3SThierry Reding 66840cc83b3SThierry Reding /* shares pads with dpaux1 */ 66940cc83b3SThierry Reding dp_aux_ch1_i2c: i2c@3190000 { 670548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 67140cc83b3SThierry Reding reg = <0x0 0x03190000 0x0 0x10000>; 67240cc83b3SThierry Reding interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 67340cc83b3SThierry Reding #address-cells = <1>; 67440cc83b3SThierry Reding #size-cells = <0>; 675c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C4>; 67640cc83b3SThierry Reding clock-names = "div-clk"; 6777bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C4>; 67840cc83b3SThierry Reding reset-names = "i2c"; 679846137c6SThierry Reding pinctrl-names = "default", "idle"; 680846137c6SThierry Reding pinctrl-0 = <&state_dpaux1_i2c>; 681846137c6SThierry Reding pinctrl-1 = <&state_dpaux1_off>; 68240cc83b3SThierry Reding status = "disabled"; 68340cc83b3SThierry Reding }; 68440cc83b3SThierry Reding 68540cc83b3SThierry Reding /* controlled by BPMP, should not be enabled */ 68640cc83b3SThierry Reding pwr_i2c: i2c@31a0000 { 687548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 68840cc83b3SThierry Reding reg = <0x0 0x031a0000 0x0 0x10000>; 68940cc83b3SThierry Reding interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 69040cc83b3SThierry Reding #address-cells = <1>; 69140cc83b3SThierry Reding #size-cells = <0>; 692c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C5>; 69340cc83b3SThierry Reding clock-names = "div-clk"; 6947bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C5>; 69540cc83b3SThierry Reding reset-names = "i2c"; 69640cc83b3SThierry Reding status = "disabled"; 69740cc83b3SThierry Reding }; 69840cc83b3SThierry Reding 69940cc83b3SThierry Reding /* shares pads with dpaux0 */ 70040cc83b3SThierry Reding dp_aux_ch0_i2c: i2c@31b0000 { 701548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 70240cc83b3SThierry Reding reg = <0x0 0x031b0000 0x0 0x10000>; 70340cc83b3SThierry Reding interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 70440cc83b3SThierry Reding #address-cells = <1>; 70540cc83b3SThierry Reding #size-cells = <0>; 706c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C6>; 70740cc83b3SThierry Reding clock-names = "div-clk"; 7087bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C6>; 70940cc83b3SThierry Reding reset-names = "i2c"; 710846137c6SThierry Reding pinctrl-names = "default", "idle"; 711846137c6SThierry Reding pinctrl-0 = <&state_dpaux_i2c>; 712846137c6SThierry Reding pinctrl-1 = <&state_dpaux_off>; 71340cc83b3SThierry Reding status = "disabled"; 71440cc83b3SThierry Reding }; 71540cc83b3SThierry Reding 71640cc83b3SThierry Reding gen7_i2c: i2c@31c0000 { 717548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 71840cc83b3SThierry Reding reg = <0x0 0x031c0000 0x0 0x10000>; 71940cc83b3SThierry Reding interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 72040cc83b3SThierry Reding #address-cells = <1>; 72140cc83b3SThierry Reding #size-cells = <0>; 722c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C7>; 72340cc83b3SThierry Reding clock-names = "div-clk"; 7247bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C7>; 72540cc83b3SThierry Reding reset-names = "i2c"; 72640cc83b3SThierry Reding status = "disabled"; 72740cc83b3SThierry Reding }; 72840cc83b3SThierry Reding 72940cc83b3SThierry Reding gen9_i2c: i2c@31e0000 { 730548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 73140cc83b3SThierry Reding reg = <0x0 0x031e0000 0x0 0x10000>; 73240cc83b3SThierry Reding interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 73340cc83b3SThierry Reding #address-cells = <1>; 73440cc83b3SThierry Reding #size-cells = <0>; 735c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C9>; 73640cc83b3SThierry Reding clock-names = "div-clk"; 7377bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C9>; 73840cc83b3SThierry Reding reset-names = "i2c"; 73940cc83b3SThierry Reding status = "disabled"; 74040cc83b3SThierry Reding }; 74140cc83b3SThierry Reding 742913f8ad4SThierry Reding pwm1: pwm@3280000 { 743913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 744913f8ad4SThierry Reding reg = <0x0 0x3280000 0x0 0x10000>; 745913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM1>; 746913f8ad4SThierry Reding clock-names = "pwm"; 747913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM1>; 748913f8ad4SThierry Reding reset-names = "pwm"; 749913f8ad4SThierry Reding status = "disabled"; 750913f8ad4SThierry Reding #pwm-cells = <2>; 751913f8ad4SThierry Reding }; 752913f8ad4SThierry Reding 753913f8ad4SThierry Reding pwm2: pwm@3290000 { 754913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 755913f8ad4SThierry Reding reg = <0x0 0x3290000 0x0 0x10000>; 756913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM2>; 757913f8ad4SThierry Reding clock-names = "pwm"; 758913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM2>; 759913f8ad4SThierry Reding reset-names = "pwm"; 760913f8ad4SThierry Reding status = "disabled"; 761913f8ad4SThierry Reding #pwm-cells = <2>; 762913f8ad4SThierry Reding }; 763913f8ad4SThierry Reding 764913f8ad4SThierry Reding pwm3: pwm@32a0000 { 765913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 766913f8ad4SThierry Reding reg = <0x0 0x32a0000 0x0 0x10000>; 767913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM3>; 768913f8ad4SThierry Reding clock-names = "pwm"; 769913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM3>; 770913f8ad4SThierry Reding reset-names = "pwm"; 771913f8ad4SThierry Reding status = "disabled"; 772913f8ad4SThierry Reding #pwm-cells = <2>; 773913f8ad4SThierry Reding }; 774913f8ad4SThierry Reding 775913f8ad4SThierry Reding pwm5: pwm@32c0000 { 776913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 777913f8ad4SThierry Reding reg = <0x0 0x32c0000 0x0 0x10000>; 778913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM5>; 779913f8ad4SThierry Reding clock-names = "pwm"; 780913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM5>; 781913f8ad4SThierry Reding reset-names = "pwm"; 782913f8ad4SThierry Reding status = "disabled"; 783913f8ad4SThierry Reding #pwm-cells = <2>; 784913f8ad4SThierry Reding }; 785913f8ad4SThierry Reding 786913f8ad4SThierry Reding pwm6: pwm@32d0000 { 787913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 788913f8ad4SThierry Reding reg = <0x0 0x32d0000 0x0 0x10000>; 789913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM6>; 790913f8ad4SThierry Reding clock-names = "pwm"; 791913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM6>; 792913f8ad4SThierry Reding reset-names = "pwm"; 793913f8ad4SThierry Reding status = "disabled"; 794913f8ad4SThierry Reding #pwm-cells = <2>; 795913f8ad4SThierry Reding }; 796913f8ad4SThierry Reding 797913f8ad4SThierry Reding pwm7: pwm@32e0000 { 798913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 799913f8ad4SThierry Reding reg = <0x0 0x32e0000 0x0 0x10000>; 800913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM7>; 801913f8ad4SThierry Reding clock-names = "pwm"; 802913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM7>; 803913f8ad4SThierry Reding reset-names = "pwm"; 804913f8ad4SThierry Reding status = "disabled"; 805913f8ad4SThierry Reding #pwm-cells = <2>; 806913f8ad4SThierry Reding }; 807913f8ad4SThierry Reding 808913f8ad4SThierry Reding pwm8: pwm@32f0000 { 809913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 810913f8ad4SThierry Reding reg = <0x0 0x32f0000 0x0 0x10000>; 811913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM8>; 812913f8ad4SThierry Reding clock-names = "pwm"; 813913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM8>; 814913f8ad4SThierry Reding reset-names = "pwm"; 815913f8ad4SThierry Reding status = "disabled"; 816913f8ad4SThierry Reding #pwm-cells = <2>; 817913f8ad4SThierry Reding }; 818913f8ad4SThierry Reding 81967bb17f6SThierry Reding sdmmc1: mmc@3400000 { 82099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 82199425dfdSThierry Reding reg = <0x0 0x03400000 0x0 0x10000>; 82299425dfdSThierry Reding interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 823baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 824baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 825baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8267bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC1>; 82799425dfdSThierry Reding reset-names = "sdhci"; 828954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 829954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 830954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8318589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC1>; 83224005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 83324005fd1SAapo Vienamo pinctrl-0 = <&sdmmc1_3v3>; 83424005fd1SAapo Vienamo pinctrl-1 = <&sdmmc1_1v8>; 83541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 83641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 83741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 83841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 83941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 84041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 8416f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8426f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 84398a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 84498a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLP_OUT0>; 84598a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 84699425dfdSThierry Reding status = "disabled"; 84799425dfdSThierry Reding }; 84899425dfdSThierry Reding 84967bb17f6SThierry Reding sdmmc2: mmc@3420000 { 85099425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 85199425dfdSThierry Reding reg = <0x0 0x03420000 0x0 0x10000>; 85299425dfdSThierry Reding interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 853baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC2>, 854baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 855baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8567bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC2>; 85799425dfdSThierry Reding reset-names = "sdhci"; 858954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 859954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 860954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8618589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC2>; 86224005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 86324005fd1SAapo Vienamo pinctrl-0 = <&sdmmc2_3v3>; 86424005fd1SAapo Vienamo pinctrl-1 = <&sdmmc2_1v8>; 86541408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 86641408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 86741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 86841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8696f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8706f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 87199425dfdSThierry Reding status = "disabled"; 87299425dfdSThierry Reding }; 87399425dfdSThierry Reding 87467bb17f6SThierry Reding sdmmc3: mmc@3440000 { 87599425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 87699425dfdSThierry Reding reg = <0x0 0x03440000 0x0 0x10000>; 87799425dfdSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 878baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC3>, 879baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 880baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 8817bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC3>; 88299425dfdSThierry Reding reset-names = "sdhci"; 883954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 884954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 885954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 8868589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC3>; 88724005fd1SAapo Vienamo pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 88824005fd1SAapo Vienamo pinctrl-0 = <&sdmmc3_3v3>; 88924005fd1SAapo Vienamo pinctrl-1 = <&sdmmc3_1v8>; 89041408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 89141408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 89241408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 89341408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 89441408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 89541408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 8966f90c6f0SAapo Vienamo nvidia,default-tap = <0x5>; 8976f90c6f0SAapo Vienamo nvidia,default-trim = <0xb>; 89899425dfdSThierry Reding status = "disabled"; 89999425dfdSThierry Reding }; 90099425dfdSThierry Reding 90167bb17f6SThierry Reding sdmmc4: mmc@3460000 { 90299425dfdSThierry Reding compatible = "nvidia,tegra186-sdhci"; 90399425dfdSThierry Reding reg = <0x0 0x03460000 0x0 0x10000>; 90499425dfdSThierry Reding interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 905baba217dSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 906baba217dSSowjanya Komatineni <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>; 907baba217dSSowjanya Komatineni clock-names = "sdhci", "tmclk"; 90898a2494fSAapo Vienamo assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 90998a2494fSAapo Vienamo <&bpmp TEGRA186_CLK_PLLC4_VCO>; 91098a2494fSAapo Vienamo assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 9117bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_SDMMC4>; 91299425dfdSThierry Reding reset-names = "sdhci"; 913954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 914954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 915954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 9168589a649SKrishna Reddy iommus = <&smmu TEGRA186_SID_SDMMC4>; 91741408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 91841408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 91941408c21SAapo Vienamo nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 92041408c21SAapo Vienamo nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 9214e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 9224e0f1229SSowjanya Komatineni nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 923e9b00196SSowjanya Komatineni nvidia,default-tap = <0x9>; 924e9b00196SSowjanya Komatineni nvidia,default-trim = <0x5>; 92522248e91SAapo Vienamo nvidia,dqs-trim = <63>; 926207f60baSAapo Vienamo mmc-hs400-1_8v; 927c4307836SSowjanya Komatineni supports-cqe; 92899425dfdSThierry Reding status = "disabled"; 92999425dfdSThierry Reding }; 93099425dfdSThierry Reding 931b066a310SThierry Reding hda@3510000 { 932b066a310SThierry Reding compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 933b066a310SThierry Reding reg = <0x0 0x03510000 0x0 0x10000>; 934b066a310SThierry Reding interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 935b066a310SThierry Reding clocks = <&bpmp TEGRA186_CLK_HDA>, 936b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 937b066a310SThierry Reding <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 938b066a310SThierry Reding clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 939b066a310SThierry Reding resets = <&bpmp TEGRA186_RESET_HDA>, 940b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 941b066a310SThierry Reding <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 942b066a310SThierry Reding reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 943b066a310SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 944954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 945954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 946954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 947dfdbf16cSJonathan Hunter iommus = <&smmu TEGRA186_SID_HDA>; 948b066a310SThierry Reding status = "disabled"; 949b066a310SThierry Reding }; 950b066a310SThierry Reding 9518bfde518SThierry Reding padctl: padctl@3520000 { 9528bfde518SThierry Reding compatible = "nvidia,tegra186-xusb-padctl"; 9538bfde518SThierry Reding reg = <0x0 0x03520000 0x0 0x1000>, 9548bfde518SThierry Reding <0x0 0x03540000 0x0 0x1000>; 9558bfde518SThierry Reding reg-names = "padctl", "ao"; 9566450da3dSJC Kuo interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 9578bfde518SThierry Reding 9588bfde518SThierry Reding resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 9598bfde518SThierry Reding reset-names = "padctl"; 9608bfde518SThierry Reding 9618bfde518SThierry Reding status = "disabled"; 9628bfde518SThierry Reding 9638bfde518SThierry Reding pads { 9648bfde518SThierry Reding usb2 { 9658bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 9668bfde518SThierry Reding clock-names = "trk"; 9678bfde518SThierry Reding status = "disabled"; 9688bfde518SThierry Reding 9698bfde518SThierry Reding lanes { 9708bfde518SThierry Reding usb2-0 { 9718bfde518SThierry Reding status = "disabled"; 9728bfde518SThierry Reding #phy-cells = <0>; 9738bfde518SThierry Reding }; 9748bfde518SThierry Reding 9758bfde518SThierry Reding usb2-1 { 9768bfde518SThierry Reding status = "disabled"; 9778bfde518SThierry Reding #phy-cells = <0>; 9788bfde518SThierry Reding }; 9798bfde518SThierry Reding 9808bfde518SThierry Reding usb2-2 { 9818bfde518SThierry Reding status = "disabled"; 9828bfde518SThierry Reding #phy-cells = <0>; 9838bfde518SThierry Reding }; 9848bfde518SThierry Reding }; 9858bfde518SThierry Reding }; 9868bfde518SThierry Reding 9878bfde518SThierry Reding hsic { 9888bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 9898bfde518SThierry Reding clock-names = "trk"; 9908bfde518SThierry Reding status = "disabled"; 9918bfde518SThierry Reding 9928bfde518SThierry Reding lanes { 9938bfde518SThierry Reding hsic-0 { 9948bfde518SThierry Reding status = "disabled"; 9958bfde518SThierry Reding #phy-cells = <0>; 9968bfde518SThierry Reding }; 9978bfde518SThierry Reding }; 9988bfde518SThierry Reding }; 9998bfde518SThierry Reding 10008bfde518SThierry Reding usb3 { 10018bfde518SThierry Reding status = "disabled"; 10028bfde518SThierry Reding 10038bfde518SThierry Reding lanes { 10048bfde518SThierry Reding usb3-0 { 10058bfde518SThierry Reding status = "disabled"; 10068bfde518SThierry Reding #phy-cells = <0>; 10078bfde518SThierry Reding }; 10088bfde518SThierry Reding 10098bfde518SThierry Reding usb3-1 { 10108bfde518SThierry Reding status = "disabled"; 10118bfde518SThierry Reding #phy-cells = <0>; 10128bfde518SThierry Reding }; 10138bfde518SThierry Reding 10148bfde518SThierry Reding usb3-2 { 10158bfde518SThierry Reding status = "disabled"; 10168bfde518SThierry Reding #phy-cells = <0>; 10178bfde518SThierry Reding }; 10188bfde518SThierry Reding }; 10198bfde518SThierry Reding }; 10208bfde518SThierry Reding }; 10218bfde518SThierry Reding 10228bfde518SThierry Reding ports { 10238bfde518SThierry Reding usb2-0 { 10248bfde518SThierry Reding status = "disabled"; 10258bfde518SThierry Reding }; 10268bfde518SThierry Reding 10278bfde518SThierry Reding usb2-1 { 10288bfde518SThierry Reding status = "disabled"; 10298bfde518SThierry Reding }; 10308bfde518SThierry Reding 10318bfde518SThierry Reding usb2-2 { 10328bfde518SThierry Reding status = "disabled"; 10338bfde518SThierry Reding }; 10348bfde518SThierry Reding 10358bfde518SThierry Reding hsic-0 { 10368bfde518SThierry Reding status = "disabled"; 10378bfde518SThierry Reding }; 10388bfde518SThierry Reding 10398bfde518SThierry Reding usb3-0 { 10408bfde518SThierry Reding status = "disabled"; 10418bfde518SThierry Reding }; 10428bfde518SThierry Reding 10438bfde518SThierry Reding usb3-1 { 10448bfde518SThierry Reding status = "disabled"; 10458bfde518SThierry Reding }; 10468bfde518SThierry Reding 10478bfde518SThierry Reding usb3-2 { 10488bfde518SThierry Reding status = "disabled"; 10498bfde518SThierry Reding }; 10508bfde518SThierry Reding }; 10518bfde518SThierry Reding }; 10528bfde518SThierry Reding 10538bfde518SThierry Reding usb@3530000 { 10548bfde518SThierry Reding compatible = "nvidia,tegra186-xusb"; 10558bfde518SThierry Reding reg = <0x0 0x03530000 0x0 0x8000>, 10568bfde518SThierry Reding <0x0 0x03538000 0x0 0x1000>; 10578bfde518SThierry Reding reg-names = "hcd", "fpci"; 10588bfde518SThierry Reding interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1059a5742139SThierry Reding <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 10608bfde518SThierry Reding clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 10618bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FALCON>, 10628bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_SS>, 10638bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 10648bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10658bfde518SThierry Reding <&bpmp TEGRA186_CLK_XUSB_FS>, 10668bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLU>, 10678bfde518SThierry Reding <&bpmp TEGRA186_CLK_CLK_M>, 10688bfde518SThierry Reding <&bpmp TEGRA186_CLK_PLLE>; 10698bfde518SThierry Reding clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 10708bfde518SThierry Reding "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 10718bfde518SThierry Reding "pll_u_480m", "clk_m", "pll_e"; 10728bfde518SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 10738bfde518SThierry Reding <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 10748bfde518SThierry Reding power-domain-names = "xusb_host", "xusb_ss"; 1075954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1076954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1077954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 107806c6b06fSThierry Reding iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 10798bfde518SThierry Reding #address-cells = <1>; 10808bfde518SThierry Reding #size-cells = <0>; 108106c6b06fSThierry Reding status = "disabled"; 108206c6b06fSThierry Reding 108306c6b06fSThierry Reding nvidia,xusb-padctl = <&padctl>; 10848bfde518SThierry Reding }; 10858bfde518SThierry Reding 1086584f800cSNagarjuna Kristam usb@3550000 { 1087584f800cSNagarjuna Kristam compatible = "nvidia,tegra186-xudc"; 1088584f800cSNagarjuna Kristam reg = <0x0 0x03550000 0x0 0x8000>, 1089584f800cSNagarjuna Kristam <0x0 0x03558000 0x0 0x1000>; 1090584f800cSNagarjuna Kristam reg-names = "base", "fpci"; 1091584f800cSNagarjuna Kristam interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1092584f800cSNagarjuna Kristam clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 1093584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_SS>, 1094584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 1095584f800cSNagarjuna Kristam <&bpmp TEGRA186_CLK_XUSB_FS>; 1096584f800cSNagarjuna Kristam clock-names = "dev", "ss", "ss_src", "fs_src"; 1097d6ff10e0SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>, 1098d6ff10e0SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>; 1099d6ff10e0SThierry Reding interconnect-names = "dma-mem", "write"; 1100584f800cSNagarjuna Kristam iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 1101584f800cSNagarjuna Kristam power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 1102584f800cSNagarjuna Kristam <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 1103584f800cSNagarjuna Kristam power-domain-names = "dev", "ss"; 1104584f800cSNagarjuna Kristam nvidia,xusb-padctl = <&padctl>; 1105584f800cSNagarjuna Kristam status = "disabled"; 1106584f800cSNagarjuna Kristam }; 1107584f800cSNagarjuna Kristam 110885593b75SThierry Reding fuse@3820000 { 110985593b75SThierry Reding compatible = "nvidia,tegra186-efuse"; 111085593b75SThierry Reding reg = <0x0 0x03820000 0x0 0x10000>; 111185593b75SThierry Reding clocks = <&bpmp TEGRA186_CLK_FUSE>; 111285593b75SThierry Reding clock-names = "fuse"; 111385593b75SThierry Reding }; 111485593b75SThierry Reding 111539cb62cbSJoseph Lo gic: interrupt-controller@3881000 { 111639cb62cbSJoseph Lo compatible = "arm,gic-400"; 111739cb62cbSJoseph Lo #interrupt-cells = <3>; 111839cb62cbSJoseph Lo interrupt-controller; 111939cb62cbSJoseph Lo reg = <0x0 0x03881000 0x0 0x1000>, 1120776a3c04SMarc Zyngier <0x0 0x03882000 0x0 0x2000>, 1121776a3c04SMarc Zyngier <0x0 0x03884000 0x0 0x2000>, 1122776a3c04SMarc Zyngier <0x0 0x03886000 0x0 0x2000>; 112339cb62cbSJoseph Lo interrupts = <GIC_PPI 9 112439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 112539cb62cbSJoseph Lo interrupt-parent = <&gic>; 112639cb62cbSJoseph Lo }; 112739cb62cbSJoseph Lo 112897cf683cSThierry Reding cec@3960000 { 112997cf683cSThierry Reding compatible = "nvidia,tegra186-cec"; 113097cf683cSThierry Reding reg = <0x0 0x03960000 0x0 0x10000>; 113197cf683cSThierry Reding interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 113297cf683cSThierry Reding clocks = <&bpmp TEGRA186_CLK_CEC>; 113397cf683cSThierry Reding clock-names = "cec"; 113497cf683cSThierry Reding status = "disabled"; 113597cf683cSThierry Reding }; 113697cf683cSThierry Reding 113739cb62cbSJoseph Lo hsp_top0: hsp@3c00000 { 113839cb62cbSJoseph Lo compatible = "nvidia,tegra186-hsp"; 113939cb62cbSJoseph Lo reg = <0x0 0x03c00000 0x0 0xa0000>; 114039cb62cbSJoseph Lo interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 114139cb62cbSJoseph Lo interrupt-names = "doorbell"; 114239cb62cbSJoseph Lo #mbox-cells = <2>; 114339cb62cbSJoseph Lo status = "disabled"; 114439cb62cbSJoseph Lo }; 114539cb62cbSJoseph Lo 114640cc83b3SThierry Reding gen2_i2c: i2c@c240000 { 1147548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 114840cc83b3SThierry Reding reg = <0x0 0x0c240000 0x0 0x10000>; 114940cc83b3SThierry Reding interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 115040cc83b3SThierry Reding #address-cells = <1>; 115140cc83b3SThierry Reding #size-cells = <0>; 1152c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C2>; 115340cc83b3SThierry Reding clock-names = "div-clk"; 11547bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C2>; 115540cc83b3SThierry Reding reset-names = "i2c"; 115640cc83b3SThierry Reding status = "disabled"; 115740cc83b3SThierry Reding }; 115840cc83b3SThierry Reding 115940cc83b3SThierry Reding gen8_i2c: i2c@c250000 { 1160548c9c5aSThierry Reding compatible = "nvidia,tegra186-i2c"; 116140cc83b3SThierry Reding reg = <0x0 0x0c250000 0x0 0x10000>; 116240cc83b3SThierry Reding interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 116340cc83b3SThierry Reding #address-cells = <1>; 116440cc83b3SThierry Reding #size-cells = <0>; 1165c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_I2C8>; 116640cc83b3SThierry Reding clock-names = "div-clk"; 11677bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_I2C8>; 116840cc83b3SThierry Reding reset-names = "i2c"; 116940cc83b3SThierry Reding status = "disabled"; 117040cc83b3SThierry Reding }; 117140cc83b3SThierry Reding 1172a7a77e2eSThierry Reding uartc: serial@c280000 { 1173a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1174a7a77e2eSThierry Reding reg = <0x0 0x0c280000 0x0 0x40>; 1175a7a77e2eSThierry Reding reg-shift = <2>; 1176a7a77e2eSThierry Reding interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1177c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTC>; 1178a7a77e2eSThierry Reding clock-names = "serial"; 11797bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTC>; 1180a7a77e2eSThierry Reding reset-names = "serial"; 1181a7a77e2eSThierry Reding status = "disabled"; 1182a7a77e2eSThierry Reding }; 1183a7a77e2eSThierry Reding 1184a7a77e2eSThierry Reding uartg: serial@c290000 { 1185a7a77e2eSThierry Reding compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 1186a7a77e2eSThierry Reding reg = <0x0 0x0c290000 0x0 0x40>; 1187a7a77e2eSThierry Reding reg-shift = <2>; 1188a7a77e2eSThierry Reding interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1189c58f5f88SThierry Reding clocks = <&bpmp TEGRA186_CLK_UARTG>; 1190a7a77e2eSThierry Reding clock-names = "serial"; 11917bcf2664SThierry Reding resets = <&bpmp TEGRA186_RESET_UARTG>; 1192a7a77e2eSThierry Reding reset-names = "serial"; 1193a7a77e2eSThierry Reding status = "disabled"; 1194a7a77e2eSThierry Reding }; 1195a7a77e2eSThierry Reding 11969733a251SThierry Reding rtc: rtc@c2a0000 { 11979733a251SThierry Reding compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 11989733a251SThierry Reding reg = <0 0x0c2a0000 0 0x10000>; 11999733a251SThierry Reding interrupt-parent = <&pmc>; 12009733a251SThierry Reding interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 12019733a251SThierry Reding clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 12029733a251SThierry Reding clock-names = "rtc"; 12039733a251SThierry Reding status = "disabled"; 12049733a251SThierry Reding }; 12059733a251SThierry Reding 1206fc4bb754SThierry Reding gpio_aon: gpio@c2f0000 { 1207fc4bb754SThierry Reding compatible = "nvidia,tegra186-gpio-aon"; 1208fc4bb754SThierry Reding reg-names = "security", "gpio"; 1209fc4bb754SThierry Reding reg = <0x0 0xc2f0000 0x0 0x1000>, 1210fc4bb754SThierry Reding <0x0 0xc2f1000 0x0 0x1000>; 1211fc4bb754SThierry Reding interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1212fc4bb754SThierry Reding gpio-controller; 1213fc4bb754SThierry Reding #gpio-cells = <2>; 1214fc4bb754SThierry Reding interrupt-controller; 1215fc4bb754SThierry Reding #interrupt-cells = <2>; 1216fc4bb754SThierry Reding }; 1217fc4bb754SThierry Reding 1218913f8ad4SThierry Reding pwm4: pwm@c340000 { 1219913f8ad4SThierry Reding compatible = "nvidia,tegra186-pwm"; 1220913f8ad4SThierry Reding reg = <0x0 0xc340000 0x0 0x10000>; 1221913f8ad4SThierry Reding clocks = <&bpmp TEGRA186_CLK_PWM4>; 1222913f8ad4SThierry Reding clock-names = "pwm"; 1223913f8ad4SThierry Reding resets = <&bpmp TEGRA186_RESET_PWM4>; 1224913f8ad4SThierry Reding reset-names = "pwm"; 1225913f8ad4SThierry Reding status = "disabled"; 1226913f8ad4SThierry Reding #pwm-cells = <2>; 1227913f8ad4SThierry Reding }; 1228913f8ad4SThierry Reding 122932e66e46SThierry Reding pmc: pmc@c360000 { 123073bf90d4SThierry Reding compatible = "nvidia,tegra186-pmc"; 123173bf90d4SThierry Reding reg = <0 0x0c360000 0 0x10000>, 123273bf90d4SThierry Reding <0 0x0c370000 0 0x10000>, 123373bf90d4SThierry Reding <0 0x0c380000 0 0x10000>, 123473bf90d4SThierry Reding <0 0x0c390000 0 0x10000>; 123573bf90d4SThierry Reding reg-names = "pmc", "wake", "aotag", "scratch"; 123624005fd1SAapo Vienamo 123732e66e46SThierry Reding #interrupt-cells = <2>; 123832e66e46SThierry Reding interrupt-controller; 123932e66e46SThierry Reding 124024005fd1SAapo Vienamo sdmmc1_3v3: sdmmc1-3v3 { 124124005fd1SAapo Vienamo pins = "sdmmc1-hv"; 124224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 124324005fd1SAapo Vienamo }; 124424005fd1SAapo Vienamo 124524005fd1SAapo Vienamo sdmmc1_1v8: sdmmc1-1v8 { 124624005fd1SAapo Vienamo pins = "sdmmc1-hv"; 124724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 124824005fd1SAapo Vienamo }; 124924005fd1SAapo Vienamo 125024005fd1SAapo Vienamo sdmmc2_3v3: sdmmc2-3v3 { 125124005fd1SAapo Vienamo pins = "sdmmc2-hv"; 125224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 125324005fd1SAapo Vienamo }; 125424005fd1SAapo Vienamo 125524005fd1SAapo Vienamo sdmmc2_1v8: sdmmc2-1v8 { 125624005fd1SAapo Vienamo pins = "sdmmc2-hv"; 125724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 125824005fd1SAapo Vienamo }; 125924005fd1SAapo Vienamo 126024005fd1SAapo Vienamo sdmmc3_3v3: sdmmc3-3v3 { 126124005fd1SAapo Vienamo pins = "sdmmc3-hv"; 126224005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 126324005fd1SAapo Vienamo }; 126424005fd1SAapo Vienamo 126524005fd1SAapo Vienamo sdmmc3_1v8: sdmmc3-1v8 { 126624005fd1SAapo Vienamo pins = "sdmmc3-hv"; 126724005fd1SAapo Vienamo power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 126824005fd1SAapo Vienamo }; 126973bf90d4SThierry Reding }; 127073bf90d4SThierry Reding 12717b7ef494SMikko Perttunen ccplex@e000000 { 12727b7ef494SMikko Perttunen compatible = "nvidia,tegra186-ccplex-cluster"; 12732b14cbd6SThierry Reding reg = <0x0 0x0e000000 0x0 0x400000>; 12747b7ef494SMikko Perttunen 12757b7ef494SMikko Perttunen nvidia,bpmp = <&bpmp>; 12767b7ef494SMikko Perttunen }; 12777b7ef494SMikko Perttunen 1278f8973cf4SManikanta Maddireddy pcie@10003000 { 1279f8973cf4SManikanta Maddireddy compatible = "nvidia,tegra186-pcie"; 1280f8973cf4SManikanta Maddireddy power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 1281f8973cf4SManikanta Maddireddy device_type = "pci"; 1282644c569dSThierry Reding reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 1283644c569dSThierry Reding <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 1284644c569dSThierry Reding <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 1285f8973cf4SManikanta Maddireddy reg-names = "pads", "afi", "cs"; 1286f8973cf4SManikanta Maddireddy 1287f8973cf4SManikanta Maddireddy interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1288f8973cf4SManikanta Maddireddy <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1289f8973cf4SManikanta Maddireddy interrupt-names = "intr", "msi"; 1290f8973cf4SManikanta Maddireddy 1291f8973cf4SManikanta Maddireddy #interrupt-cells = <1>; 1292f8973cf4SManikanta Maddireddy interrupt-map-mask = <0 0 0 0>; 1293f8973cf4SManikanta Maddireddy interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1294f8973cf4SManikanta Maddireddy 1295f8973cf4SManikanta Maddireddy bus-range = <0x00 0xff>; 1296f8973cf4SManikanta Maddireddy #address-cells = <3>; 1297f8973cf4SManikanta Maddireddy #size-cells = <2>; 1298f8973cf4SManikanta Maddireddy 1299644c569dSThierry Reding ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1300644c569dSThierry Reding <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1301644c569dSThierry Reding <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1302644c569dSThierry Reding <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1303644c569dSThierry Reding <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1304644c569dSThierry Reding <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1305f8973cf4SManikanta Maddireddy 130678b9bad6SThierry Reding clocks = <&bpmp TEGRA186_CLK_PCIE>, 130778b9bad6SThierry Reding <&bpmp TEGRA186_CLK_AFI>, 1308f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_CLK_PLLE>; 130978b9bad6SThierry Reding clock-names = "pex", "afi", "pll_e"; 1310f8973cf4SManikanta Maddireddy 131178b9bad6SThierry Reding resets = <&bpmp TEGRA186_RESET_PCIE>, 131278b9bad6SThierry Reding <&bpmp TEGRA186_RESET_AFI>, 1313f8973cf4SManikanta Maddireddy <&bpmp TEGRA186_RESET_PCIEXCLK>; 131478b9bad6SThierry Reding reset-names = "pex", "afi", "pcie_x"; 1315f8973cf4SManikanta Maddireddy 1316954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1317954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1318954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 1319954490b3SThierry Reding 1320f2a465e7SThierry Reding iommus = <&smmu TEGRA186_SID_AFI>; 1321f2a465e7SThierry Reding iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1322f2a465e7SThierry Reding iommu-map-mask = <0x0>; 1323f2a465e7SThierry Reding 1324f8973cf4SManikanta Maddireddy status = "disabled"; 1325f8973cf4SManikanta Maddireddy 1326f8973cf4SManikanta Maddireddy pci@1,0 { 1327f8973cf4SManikanta Maddireddy device_type = "pci"; 1328f8973cf4SManikanta Maddireddy assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1329f8973cf4SManikanta Maddireddy reg = <0x000800 0 0 0 0>; 1330f8973cf4SManikanta Maddireddy status = "disabled"; 1331f8973cf4SManikanta Maddireddy 1332f8973cf4SManikanta Maddireddy #address-cells = <3>; 1333f8973cf4SManikanta Maddireddy #size-cells = <2>; 1334f8973cf4SManikanta Maddireddy ranges; 1335f8973cf4SManikanta Maddireddy 1336f8973cf4SManikanta Maddireddy nvidia,num-lanes = <2>; 1337f8973cf4SManikanta Maddireddy }; 1338f8973cf4SManikanta Maddireddy 1339f8973cf4SManikanta Maddireddy pci@2,0 { 1340f8973cf4SManikanta Maddireddy device_type = "pci"; 1341f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1342f8973cf4SManikanta Maddireddy reg = <0x001000 0 0 0 0>; 1343f8973cf4SManikanta Maddireddy status = "disabled"; 1344f8973cf4SManikanta Maddireddy 1345f8973cf4SManikanta Maddireddy #address-cells = <3>; 1346f8973cf4SManikanta Maddireddy #size-cells = <2>; 1347f8973cf4SManikanta Maddireddy ranges; 1348f8973cf4SManikanta Maddireddy 1349f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1350f8973cf4SManikanta Maddireddy }; 1351f8973cf4SManikanta Maddireddy 1352f8973cf4SManikanta Maddireddy pci@3,0 { 1353f8973cf4SManikanta Maddireddy device_type = "pci"; 1354f8973cf4SManikanta Maddireddy assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1355f8973cf4SManikanta Maddireddy reg = <0x001800 0 0 0 0>; 1356f8973cf4SManikanta Maddireddy status = "disabled"; 1357f8973cf4SManikanta Maddireddy 1358f8973cf4SManikanta Maddireddy #address-cells = <3>; 1359f8973cf4SManikanta Maddireddy #size-cells = <2>; 1360f8973cf4SManikanta Maddireddy ranges; 1361f8973cf4SManikanta Maddireddy 1362f8973cf4SManikanta Maddireddy nvidia,num-lanes = <1>; 1363f8973cf4SManikanta Maddireddy }; 1364f8973cf4SManikanta Maddireddy }; 1365f8973cf4SManikanta Maddireddy 1366b30a8e61SThierry Reding smmu: iommu@12000000 { 1367bb84a31bSThierry Reding compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500"; 1368b30a8e61SThierry Reding reg = <0 0x12000000 0 0x800000>; 1369b30a8e61SThierry Reding interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1386b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1387b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1388b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1389b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1391b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1392b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433b30a8e61SThierry Reding <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1434b30a8e61SThierry Reding stream-match-mask = <0x7f80>; 1435b30a8e61SThierry Reding #global-interrupts = <1>; 1436b30a8e61SThierry Reding #iommu-cells = <1>; 1437b966d2dbSThierry Reding 1438b966d2dbSThierry Reding nvidia,memory-controller = <&mc>; 1439b30a8e61SThierry Reding }; 1440b30a8e61SThierry Reding 14415524c61fSMikko Perttunen host1x@13e00000 { 1442ef126bc4SThierry Reding compatible = "nvidia,tegra186-host1x"; 14435524c61fSMikko Perttunen reg = <0x0 0x13e00000 0x0 0x10000>, 14445524c61fSMikko Perttunen <0x0 0x13e10000 0x0 0x10000>; 14455524c61fSMikko Perttunen reg-names = "hypervisor", "vm"; 14465524c61fSMikko Perttunen interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 14475524c61fSMikko Perttunen <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1448052d3f65SThierry Reding interrupt-names = "syncpt", "host1x"; 14495524c61fSMikko Perttunen clocks = <&bpmp TEGRA186_CLK_HOST1X>; 14505524c61fSMikko Perttunen clock-names = "host1x"; 14515524c61fSMikko Perttunen resets = <&bpmp TEGRA186_RESET_HOST1X>; 14525524c61fSMikko Perttunen reset-names = "host1x"; 14535524c61fSMikko Perttunen 14545524c61fSMikko Perttunen #address-cells = <1>; 14555524c61fSMikko Perttunen #size-cells = <1>; 14565524c61fSMikko Perttunen 14575524c61fSMikko Perttunen ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1458954490b3SThierry Reding 1459954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1460954490b3SThierry Reding interconnect-names = "dma-mem"; 1461954490b3SThierry Reding 1462c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_HOST1X>; 1463c2599da7SThierry Reding 1464c2599da7SThierry Reding dpaux1: dpaux@15040000 { 1465c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1466c2599da7SThierry Reding reg = <0x15040000 0x10000>; 1467c2599da7SThierry Reding interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1468c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1469c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1470c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1471c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1472c2599da7SThierry Reding reset-names = "dpaux"; 1473c2599da7SThierry Reding status = "disabled"; 1474c2599da7SThierry Reding 1475c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1476c2599da7SThierry Reding 1477c2599da7SThierry Reding state_dpaux1_aux: pinmux-aux { 1478c2599da7SThierry Reding groups = "dpaux-io"; 1479c2599da7SThierry Reding function = "aux"; 1480c2599da7SThierry Reding }; 1481c2599da7SThierry Reding 1482c2599da7SThierry Reding state_dpaux1_i2c: pinmux-i2c { 1483c2599da7SThierry Reding groups = "dpaux-io"; 1484c2599da7SThierry Reding function = "i2c"; 1485c2599da7SThierry Reding }; 1486c2599da7SThierry Reding 1487c2599da7SThierry Reding state_dpaux1_off: pinmux-off { 1488c2599da7SThierry Reding groups = "dpaux-io"; 1489c2599da7SThierry Reding function = "off"; 1490c2599da7SThierry Reding }; 1491c2599da7SThierry Reding 1492c2599da7SThierry Reding i2c-bus { 1493c2599da7SThierry Reding #address-cells = <1>; 1494c2599da7SThierry Reding #size-cells = <0>; 1495c2599da7SThierry Reding }; 1496c2599da7SThierry Reding }; 1497c2599da7SThierry Reding 1498c2599da7SThierry Reding display-hub@15200000 { 1499aa342b53SThierry Reding compatible = "nvidia,tegra186-display"; 1500ffa1ad89SThierry Reding reg = <0x15200000 0x00040000>; 1501c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1502c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1503c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1504c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1505c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1506c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1507c2599da7SThierry Reding <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1508c2599da7SThierry Reding reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1509c2599da7SThierry Reding "wgrp3", "wgrp4", "wgrp5"; 1510c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1511c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1512c2599da7SThierry Reding <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1513c2599da7SThierry Reding clock-names = "disp", "dsc", "hub"; 1514c2599da7SThierry Reding status = "disabled"; 1515c2599da7SThierry Reding 1516c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1517c2599da7SThierry Reding 1518c2599da7SThierry Reding #address-cells = <1>; 1519c2599da7SThierry Reding #size-cells = <1>; 1520c2599da7SThierry Reding 1521c2599da7SThierry Reding ranges = <0x15200000 0x15200000 0x40000>; 1522c2599da7SThierry Reding 1523c2599da7SThierry Reding display@15200000 { 1524c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1525c2599da7SThierry Reding reg = <0x15200000 0x10000>; 1526c2599da7SThierry Reding interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1527c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1528c2599da7SThierry Reding clock-names = "dc"; 1529c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1530c2599da7SThierry Reding reset-names = "dc"; 1531c2599da7SThierry Reding 1532c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1533954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1534954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1535954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1536c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1537c2599da7SThierry Reding 1538c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1539c2599da7SThierry Reding nvidia,head = <0>; 1540c2599da7SThierry Reding }; 1541c2599da7SThierry Reding 1542c2599da7SThierry Reding display@15210000 { 1543c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1544c2599da7SThierry Reding reg = <0x15210000 0x10000>; 1545c2599da7SThierry Reding interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1546c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1547c2599da7SThierry Reding clock-names = "dc"; 1548c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1549c2599da7SThierry Reding reset-names = "dc"; 1550c2599da7SThierry Reding 1551c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1552954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1553954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1554954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1555c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1556c2599da7SThierry Reding 1557c2599da7SThierry Reding nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1558c2599da7SThierry Reding nvidia,head = <1>; 1559c2599da7SThierry Reding }; 1560c2599da7SThierry Reding 1561c2599da7SThierry Reding display@15220000 { 1562c2599da7SThierry Reding compatible = "nvidia,tegra186-dc"; 1563c2599da7SThierry Reding reg = <0x15220000 0x10000>; 1564c2599da7SThierry Reding interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1565c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1566c2599da7SThierry Reding clock-names = "dc"; 1567c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1568c2599da7SThierry Reding reset-names = "dc"; 1569c2599da7SThierry Reding 1570c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1571954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1572954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1573954490b3SThierry Reding interconnect-names = "dma-mem", "read-1"; 1574c2599da7SThierry Reding iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1575c2599da7SThierry Reding 1576c2599da7SThierry Reding nvidia,outputs = <&sor0 &sor1>; 1577c2599da7SThierry Reding nvidia,head = <2>; 1578c2599da7SThierry Reding }; 1579c2599da7SThierry Reding }; 1580c2599da7SThierry Reding 1581c2599da7SThierry Reding dsia: dsi@15300000 { 1582c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1583c2599da7SThierry Reding reg = <0x15300000 0x10000>; 1584c2599da7SThierry Reding interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1585c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSI>, 1586c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIA_LP>, 1587c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1588c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1589c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1590c2599da7SThierry Reding reset-names = "dsi"; 1591c2599da7SThierry Reding status = "disabled"; 1592c2599da7SThierry Reding 1593c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1594c2599da7SThierry Reding }; 1595effc4b44SMikko Perttunen 1596effc4b44SMikko Perttunen vic@15340000 { 1597effc4b44SMikko Perttunen compatible = "nvidia,tegra186-vic"; 1598effc4b44SMikko Perttunen reg = <0x15340000 0x40000>; 1599effc4b44SMikko Perttunen interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1600effc4b44SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_VIC>; 1601effc4b44SMikko Perttunen clock-names = "vic"; 1602effc4b44SMikko Perttunen resets = <&bpmp TEGRA186_RESET_VIC>; 1603effc4b44SMikko Perttunen reset-names = "vic"; 1604effc4b44SMikko Perttunen 1605effc4b44SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1606954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1607954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1608954490b3SThierry Reding interconnect-names = "dma-mem", "write"; 160929ef1f4dSThierry Reding iommus = <&smmu TEGRA186_SID_VIC>; 1610effc4b44SMikko Perttunen }; 1611c2599da7SThierry Reding 1612f7eb2785SJon Hunter nvjpg@15380000 { 1613f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvjpg"; 1614f7eb2785SJon Hunter reg = <0x15380000 0x40000>; 1615f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVJPG>; 1616f7eb2785SJon Hunter clock-names = "nvjpg"; 1617f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVJPG>; 1618f7eb2785SJon Hunter reset-names = "nvjpg"; 1619f7eb2785SJon Hunter 1620f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>; 1621f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>, 1622f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>; 1623f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1624f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVJPG>; 1625f7eb2785SJon Hunter }; 1626f7eb2785SJon Hunter 1627c2599da7SThierry Reding dsib: dsi@15400000 { 1628c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1629c2599da7SThierry Reding reg = <0x15400000 0x10000>; 1630c2599da7SThierry Reding interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1631c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIB>, 1632c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIB_LP>, 1633c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1634c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1635c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIB>; 1636c2599da7SThierry Reding reset-names = "dsi"; 1637c2599da7SThierry Reding status = "disabled"; 1638c2599da7SThierry Reding 1639c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1640c2599da7SThierry Reding }; 1641c2599da7SThierry Reding 164278a05873SMikko Perttunen nvdec@15480000 { 164378a05873SMikko Perttunen compatible = "nvidia,tegra186-nvdec"; 164478a05873SMikko Perttunen reg = <0x15480000 0x40000>; 164578a05873SMikko Perttunen clocks = <&bpmp TEGRA186_CLK_NVDEC>; 164678a05873SMikko Perttunen clock-names = "nvdec"; 164778a05873SMikko Perttunen resets = <&bpmp TEGRA186_RESET_NVDEC>; 164878a05873SMikko Perttunen reset-names = "nvdec"; 164978a05873SMikko Perttunen 165078a05873SMikko Perttunen power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>; 165178a05873SMikko Perttunen interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>, 165278a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>, 165378a05873SMikko Perttunen <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>; 165478a05873SMikko Perttunen interconnect-names = "dma-mem", "read-1", "write"; 165578a05873SMikko Perttunen iommus = <&smmu TEGRA186_SID_NVDEC>; 165678a05873SMikko Perttunen }; 165778a05873SMikko Perttunen 1658f7eb2785SJon Hunter nvenc@154c0000 { 1659f7eb2785SJon Hunter compatible = "nvidia,tegra186-nvenc"; 1660f7eb2785SJon Hunter reg = <0x154c0000 0x40000>; 1661f7eb2785SJon Hunter clocks = <&bpmp TEGRA186_CLK_NVENC>; 1662f7eb2785SJon Hunter clock-names = "nvenc"; 1663f7eb2785SJon Hunter resets = <&bpmp TEGRA186_RESET_NVENC>; 1664f7eb2785SJon Hunter reset-names = "nvenc"; 1665f7eb2785SJon Hunter 1666f7eb2785SJon Hunter power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>; 1667f7eb2785SJon Hunter interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>, 1668f7eb2785SJon Hunter <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>; 1669f7eb2785SJon Hunter interconnect-names = "dma-mem", "write"; 1670f7eb2785SJon Hunter iommus = <&smmu TEGRA186_SID_NVENC>; 1671f7eb2785SJon Hunter }; 1672f7eb2785SJon Hunter 1673c2599da7SThierry Reding sor0: sor@15540000 { 1674c2599da7SThierry Reding compatible = "nvidia,tegra186-sor"; 1675c2599da7SThierry Reding reg = <0x15540000 0x10000>; 1676c2599da7SThierry Reding interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1677c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR0>, 1678c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_OUT>, 1679c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD2>, 1680c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1681c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1682c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1683c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1684c2599da7SThierry Reding "pad"; 1685c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR0>; 1686c2599da7SThierry Reding reset-names = "sor"; 1687c2599da7SThierry Reding pinctrl-0 = <&state_dpaux_aux>; 1688c2599da7SThierry Reding pinctrl-1 = <&state_dpaux_i2c>; 1689c2599da7SThierry Reding pinctrl-2 = <&state_dpaux_off>; 1690c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1691c2599da7SThierry Reding status = "disabled"; 1692c2599da7SThierry Reding 1693c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1694c2599da7SThierry Reding nvidia,interface = <0>; 1695c2599da7SThierry Reding }; 1696c2599da7SThierry Reding 1697c2599da7SThierry Reding sor1: sor@15580000 { 1698d46d1eb3SThierry Reding compatible = "nvidia,tegra186-sor"; 1699c2599da7SThierry Reding reg = <0x15580000 0x10000>; 1700c2599da7SThierry Reding interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1701c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_SOR1>, 1702c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_OUT>, 1703c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD3>, 1704c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>, 1705c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR_SAFE>, 1706c2599da7SThierry Reding <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1707c2599da7SThierry Reding clock-names = "sor", "out", "parent", "dp", "safe", 1708c2599da7SThierry Reding "pad"; 1709c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_SOR1>; 1710c2599da7SThierry Reding reset-names = "sor"; 1711c2599da7SThierry Reding pinctrl-0 = <&state_dpaux1_aux>; 1712c2599da7SThierry Reding pinctrl-1 = <&state_dpaux1_i2c>; 1713c2599da7SThierry Reding pinctrl-2 = <&state_dpaux1_off>; 1714c2599da7SThierry Reding pinctrl-names = "aux", "i2c", "off"; 1715c2599da7SThierry Reding status = "disabled"; 1716c2599da7SThierry Reding 1717c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1718c2599da7SThierry Reding nvidia,interface = <1>; 1719c2599da7SThierry Reding }; 1720c2599da7SThierry Reding 1721c2599da7SThierry Reding dpaux: dpaux@155c0000 { 1722c2599da7SThierry Reding compatible = "nvidia,tegra186-dpaux"; 1723c2599da7SThierry Reding reg = <0x155c0000 0x10000>; 1724c2599da7SThierry Reding interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1725c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1726c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLDP>; 1727c2599da7SThierry Reding clock-names = "dpaux", "parent"; 1728c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DPAUX>; 1729c2599da7SThierry Reding reset-names = "dpaux"; 1730c2599da7SThierry Reding status = "disabled"; 1731c2599da7SThierry Reding 1732c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1733c2599da7SThierry Reding 1734c2599da7SThierry Reding state_dpaux_aux: pinmux-aux { 1735c2599da7SThierry Reding groups = "dpaux-io"; 1736c2599da7SThierry Reding function = "aux"; 1737c2599da7SThierry Reding }; 1738c2599da7SThierry Reding 1739c2599da7SThierry Reding state_dpaux_i2c: pinmux-i2c { 1740c2599da7SThierry Reding groups = "dpaux-io"; 1741c2599da7SThierry Reding function = "i2c"; 1742c2599da7SThierry Reding }; 1743c2599da7SThierry Reding 1744c2599da7SThierry Reding state_dpaux_off: pinmux-off { 1745c2599da7SThierry Reding groups = "dpaux-io"; 1746c2599da7SThierry Reding function = "off"; 1747c2599da7SThierry Reding }; 1748c2599da7SThierry Reding 1749c2599da7SThierry Reding i2c-bus { 1750c2599da7SThierry Reding #address-cells = <1>; 1751c2599da7SThierry Reding #size-cells = <0>; 1752c2599da7SThierry Reding }; 1753c2599da7SThierry Reding }; 1754c2599da7SThierry Reding 1755c2599da7SThierry Reding padctl@15880000 { 1756c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi-padctl"; 1757c2599da7SThierry Reding reg = <0x15880000 0x10000>; 1758c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSI>; 1759c2599da7SThierry Reding reset-names = "dsi"; 1760c2599da7SThierry Reding status = "disabled"; 1761c2599da7SThierry Reding }; 1762c2599da7SThierry Reding 1763c2599da7SThierry Reding dsic: dsi@15900000 { 1764c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1765c2599da7SThierry Reding reg = <0x15900000 0x10000>; 1766c2599da7SThierry Reding interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1767c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSIC>, 1768c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSIC_LP>, 1769c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1770c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1771c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSIC>; 1772c2599da7SThierry Reding reset-names = "dsi"; 1773c2599da7SThierry Reding status = "disabled"; 1774c2599da7SThierry Reding 1775c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1776c2599da7SThierry Reding }; 1777c2599da7SThierry Reding 1778c2599da7SThierry Reding dsid: dsi@15940000 { 1779c2599da7SThierry Reding compatible = "nvidia,tegra186-dsi"; 1780c2599da7SThierry Reding reg = <0x15940000 0x10000>; 1781c2599da7SThierry Reding interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1782c2599da7SThierry Reding clocks = <&bpmp TEGRA186_CLK_DSID>, 1783c2599da7SThierry Reding <&bpmp TEGRA186_CLK_DSID_LP>, 1784c2599da7SThierry Reding <&bpmp TEGRA186_CLK_PLLD>; 1785c2599da7SThierry Reding clock-names = "dsi", "lp", "parent"; 1786c2599da7SThierry Reding resets = <&bpmp TEGRA186_RESET_DSID>; 1787c2599da7SThierry Reding reset-names = "dsi"; 1788c2599da7SThierry Reding status = "disabled"; 1789c2599da7SThierry Reding 1790c2599da7SThierry Reding power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1791c2599da7SThierry Reding }; 17925524c61fSMikko Perttunen }; 17935524c61fSMikko Perttunen 1794dfd7a384SAlexandre Courbot gpu@17000000 { 1795dfd7a384SAlexandre Courbot compatible = "nvidia,gp10b"; 1796dfd7a384SAlexandre Courbot reg = <0x0 0x17000000 0x0 0x1000000>, 1797dfd7a384SAlexandre Courbot <0x0 0x18000000 0x0 0x1000000>; 179859a9dd64SThierry Reding interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 179959a9dd64SThierry Reding <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1800dfd7a384SAlexandre Courbot interrupt-names = "stall", "nonstall"; 1801dfd7a384SAlexandre Courbot 1802dfd7a384SAlexandre Courbot clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1803dfd7a384SAlexandre Courbot <&bpmp TEGRA186_CLK_GPU>; 1804dfd7a384SAlexandre Courbot clock-names = "gpu", "pwr"; 1805dfd7a384SAlexandre Courbot resets = <&bpmp TEGRA186_RESET_GPU>; 1806dfd7a384SAlexandre Courbot reset-names = "gpu"; 1807dfd7a384SAlexandre Courbot status = "disabled"; 1808dfd7a384SAlexandre Courbot 1809dfd7a384SAlexandre Courbot power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1810954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1811954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1812954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1813954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1814954490b3SThierry Reding interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1815dfd7a384SAlexandre Courbot }; 1816dfd7a384SAlexandre Courbot 1817e867fe41SThierry Reding sram@30000000 { 181839cb62cbSJoseph Lo compatible = "nvidia,tegra186-sysram", "mmio-sram"; 181939cb62cbSJoseph Lo reg = <0x0 0x30000000 0x0 0x50000>; 1820aa78032cSThierry Reding #address-cells = <1>; 1821aa78032cSThierry Reding #size-cells = <1>; 1822aa78032cSThierry Reding ranges = <0x0 0x0 0x30000000 0x50000>; 182339cb62cbSJoseph Lo 1824e867fe41SThierry Reding cpu_bpmp_tx: sram@4e000 { 1825aa78032cSThierry Reding reg = <0x4e000 0x1000>; 182639cb62cbSJoseph Lo label = "cpu-bpmp-tx"; 182739cb62cbSJoseph Lo pool; 182839cb62cbSJoseph Lo }; 182939cb62cbSJoseph Lo 1830e867fe41SThierry Reding cpu_bpmp_rx: sram@4f000 { 1831aa78032cSThierry Reding reg = <0x4f000 0x1000>; 183239cb62cbSJoseph Lo label = "cpu-bpmp-rx"; 183339cb62cbSJoseph Lo pool; 183439cb62cbSJoseph Lo }; 183539cb62cbSJoseph Lo }; 183639cb62cbSJoseph Lo 1837e061fbdfSSowjanya Komatineni sata@3507000 { 1838e061fbdfSSowjanya Komatineni compatible = "nvidia,tegra186-ahci"; 1839e061fbdfSSowjanya Komatineni reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ 1840e061fbdfSSowjanya Komatineni <0x0 0x03500000 0x0 0x00007000>, /* SATA */ 1841e061fbdfSSowjanya Komatineni <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ 1842e061fbdfSSowjanya Komatineni interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1843e061fbdfSSowjanya Komatineni 1844e061fbdfSSowjanya Komatineni power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; 1845e061fbdfSSowjanya Komatineni interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, 1846e061fbdfSSowjanya Komatineni <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; 1847e061fbdfSSowjanya Komatineni interconnect-names = "dma-mem", "write"; 1848e061fbdfSSowjanya Komatineni iommus = <&smmu TEGRA186_SID_SATA>; 1849e061fbdfSSowjanya Komatineni 1850e061fbdfSSowjanya Komatineni clocks = <&bpmp TEGRA186_CLK_SATA>, 1851e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1852e061fbdfSSowjanya Komatineni clock-names = "sata", "sata-oob"; 1853e061fbdfSSowjanya Komatineni assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, 1854e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_SATA_OOB>; 1855e061fbdfSSowjanya Komatineni assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, 1856e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_CLK_PLLP>; 1857e061fbdfSSowjanya Komatineni assigned-clock-rates = <102000000>, 1858e061fbdfSSowjanya Komatineni <204000000>; 1859e061fbdfSSowjanya Komatineni resets = <&bpmp TEGRA186_RESET_SATA>, 1860e061fbdfSSowjanya Komatineni <&bpmp TEGRA186_RESET_SATACOLD>; 1861e061fbdfSSowjanya Komatineni reset-names = "sata", "sata-cold"; 1862e061fbdfSSowjanya Komatineni status = "disabled"; 1863e061fbdfSSowjanya Komatineni }; 1864e061fbdfSSowjanya Komatineni 1865541d7c44SThierry Reding bpmp: bpmp { 1866541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp"; 1867954490b3SThierry Reding interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1868954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1869954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1870954490b3SThierry Reding <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1871954490b3SThierry Reding interconnect-names = "read", "write", "dma-mem", "dma-write"; 1872541d7c44SThierry Reding iommus = <&smmu TEGRA186_SID_BPMP>; 1873541d7c44SThierry Reding mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1874541d7c44SThierry Reding TEGRA_HSP_DB_MASTER_BPMP>; 18757fa30752SThierry Reding shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1876541d7c44SThierry Reding #clock-cells = <1>; 1877541d7c44SThierry Reding #reset-cells = <1>; 1878541d7c44SThierry Reding #power-domain-cells = <1>; 1879541d7c44SThierry Reding 1880541d7c44SThierry Reding bpmp_i2c: i2c { 1881541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-i2c"; 1882541d7c44SThierry Reding nvidia,bpmp-bus-id = <5>; 1883541d7c44SThierry Reding #address-cells = <1>; 1884541d7c44SThierry Reding #size-cells = <0>; 1885541d7c44SThierry Reding status = "disabled"; 1886541d7c44SThierry Reding }; 1887541d7c44SThierry Reding 1888541d7c44SThierry Reding bpmp_thermal: thermal { 1889541d7c44SThierry Reding compatible = "nvidia,tegra186-bpmp-thermal"; 1890541d7c44SThierry Reding #thermal-sensor-cells = <1>; 1891541d7c44SThierry Reding }; 1892541d7c44SThierry Reding }; 1893541d7c44SThierry Reding 1894cd6fe32eSThierry Reding cpus { 1895cd6fe32eSThierry Reding #address-cells = <1>; 1896cd6fe32eSThierry Reding #size-cells = <0>; 1897cd6fe32eSThierry Reding 18983b4c1378SMarc Zyngier denver_0: cpu@0 { 189931af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1900cd6fe32eSThierry Reding device_type = "cpu"; 19015298166dSJoseph Lo i-cache-size = <0x20000>; 19025298166dSJoseph Lo i-cache-line-size = <64>; 19035298166dSJoseph Lo i-cache-sets = <512>; 19045298166dSJoseph Lo d-cache-size = <0x10000>; 19055298166dSJoseph Lo d-cache-line-size = <64>; 19065298166dSJoseph Lo d-cache-sets = <256>; 19075298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1908cd6fe32eSThierry Reding reg = <0x000>; 1909cd6fe32eSThierry Reding }; 1910cd6fe32eSThierry Reding 19113b4c1378SMarc Zyngier denver_1: cpu@1 { 191231af04cdSRob Herring compatible = "nvidia,tegra186-denver"; 1913cd6fe32eSThierry Reding device_type = "cpu"; 19145298166dSJoseph Lo i-cache-size = <0x20000>; 19155298166dSJoseph Lo i-cache-line-size = <64>; 19165298166dSJoseph Lo i-cache-sets = <512>; 19175298166dSJoseph Lo d-cache-size = <0x10000>; 19185298166dSJoseph Lo d-cache-line-size = <64>; 19195298166dSJoseph Lo d-cache-sets = <256>; 19205298166dSJoseph Lo next-level-cache = <&L2_DENVER>; 1921cd6fe32eSThierry Reding reg = <0x001>; 1922cd6fe32eSThierry Reding }; 1923cd6fe32eSThierry Reding 19243b4c1378SMarc Zyngier ca57_0: cpu@2 { 192531af04cdSRob Herring compatible = "arm,cortex-a57"; 1926cd6fe32eSThierry Reding device_type = "cpu"; 19275298166dSJoseph Lo i-cache-size = <0xC000>; 19285298166dSJoseph Lo i-cache-line-size = <64>; 19295298166dSJoseph Lo i-cache-sets = <256>; 19305298166dSJoseph Lo d-cache-size = <0x8000>; 19315298166dSJoseph Lo d-cache-line-size = <64>; 19325298166dSJoseph Lo d-cache-sets = <256>; 19335298166dSJoseph Lo next-level-cache = <&L2_A57>; 1934cd6fe32eSThierry Reding reg = <0x100>; 1935cd6fe32eSThierry Reding }; 1936cd6fe32eSThierry Reding 19373b4c1378SMarc Zyngier ca57_1: cpu@3 { 193831af04cdSRob Herring compatible = "arm,cortex-a57"; 1939cd6fe32eSThierry Reding device_type = "cpu"; 19405298166dSJoseph Lo i-cache-size = <0xC000>; 19415298166dSJoseph Lo i-cache-line-size = <64>; 19425298166dSJoseph Lo i-cache-sets = <256>; 19435298166dSJoseph Lo d-cache-size = <0x8000>; 19445298166dSJoseph Lo d-cache-line-size = <64>; 19455298166dSJoseph Lo d-cache-sets = <256>; 19465298166dSJoseph Lo next-level-cache = <&L2_A57>; 1947cd6fe32eSThierry Reding reg = <0x101>; 1948cd6fe32eSThierry Reding }; 1949cd6fe32eSThierry Reding 19503b4c1378SMarc Zyngier ca57_2: cpu@4 { 195131af04cdSRob Herring compatible = "arm,cortex-a57"; 1952cd6fe32eSThierry Reding device_type = "cpu"; 19535298166dSJoseph Lo i-cache-size = <0xC000>; 19545298166dSJoseph Lo i-cache-line-size = <64>; 19555298166dSJoseph Lo i-cache-sets = <256>; 19565298166dSJoseph Lo d-cache-size = <0x8000>; 19575298166dSJoseph Lo d-cache-line-size = <64>; 19585298166dSJoseph Lo d-cache-sets = <256>; 19595298166dSJoseph Lo next-level-cache = <&L2_A57>; 1960cd6fe32eSThierry Reding reg = <0x102>; 1961cd6fe32eSThierry Reding }; 1962cd6fe32eSThierry Reding 19633b4c1378SMarc Zyngier ca57_3: cpu@5 { 196431af04cdSRob Herring compatible = "arm,cortex-a57"; 1965cd6fe32eSThierry Reding device_type = "cpu"; 19665298166dSJoseph Lo i-cache-size = <0xC000>; 19675298166dSJoseph Lo i-cache-line-size = <64>; 19685298166dSJoseph Lo i-cache-sets = <256>; 19695298166dSJoseph Lo d-cache-size = <0x8000>; 19705298166dSJoseph Lo d-cache-line-size = <64>; 19715298166dSJoseph Lo d-cache-sets = <256>; 19725298166dSJoseph Lo next-level-cache = <&L2_A57>; 1973cd6fe32eSThierry Reding reg = <0x103>; 1974cd6fe32eSThierry Reding }; 19755298166dSJoseph Lo 19765298166dSJoseph Lo L2_DENVER: l2-cache0 { 19775298166dSJoseph Lo compatible = "cache"; 19785298166dSJoseph Lo cache-unified; 19795298166dSJoseph Lo cache-level = <2>; 19805298166dSJoseph Lo cache-size = <0x200000>; 19815298166dSJoseph Lo cache-line-size = <64>; 19825298166dSJoseph Lo cache-sets = <2048>; 19835298166dSJoseph Lo }; 19845298166dSJoseph Lo 19855298166dSJoseph Lo L2_A57: l2-cache1 { 19865298166dSJoseph Lo compatible = "cache"; 19875298166dSJoseph Lo cache-unified; 19885298166dSJoseph Lo cache-level = <2>; 19895298166dSJoseph Lo cache-size = <0x200000>; 19905298166dSJoseph Lo cache-line-size = <64>; 19915298166dSJoseph Lo cache-sets = <2048>; 19925298166dSJoseph Lo }; 1993cd6fe32eSThierry Reding }; 1994cd6fe32eSThierry Reding 19953b4c1378SMarc Zyngier pmu_denver { 1996f0a48120SThierry Reding compatible = "nvidia,denver-pmu"; 19973b4c1378SMarc Zyngier interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 19983b4c1378SMarc Zyngier <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 19993b4c1378SMarc Zyngier interrupt-affinity = <&denver_0 &denver_1>; 20003b4c1378SMarc Zyngier }; 20013b4c1378SMarc Zyngier 20023b4c1378SMarc Zyngier pmu_a57 { 2003f0a48120SThierry Reding compatible = "arm,cortex-a57-pmu"; 20043b4c1378SMarc Zyngier interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 20053b4c1378SMarc Zyngier <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 20063b4c1378SMarc Zyngier <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 20073b4c1378SMarc Zyngier <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 20083b4c1378SMarc Zyngier interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; 20093b4c1378SMarc Zyngier }; 20103b4c1378SMarc Zyngier 2011e4710376SSameer Pujar sound { 2012e4710376SSameer Pujar status = "disabled"; 2013e4710376SSameer Pujar 2014e4710376SSameer Pujar clocks = <&bpmp TEGRA186_CLK_PLLA>, 2015e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2016e4710376SSameer Pujar clock-names = "pll_a", "plla_out0"; 2017e4710376SSameer Pujar assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>, 2018e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>, 2019e4710376SSameer Pujar <&bpmp TEGRA186_CLK_AUD_MCLK>; 2020e4710376SSameer Pujar assigned-clock-parents = <0>, 2021e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLLA>, 2022e4710376SSameer Pujar <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 2023e4710376SSameer Pujar /* 2024e4710376SSameer Pujar * PLLA supports dynamic ramp. Below initial rate is chosen 2025e4710376SSameer Pujar * for this to work and oscillate between base rates required 2026e4710376SSameer Pujar * for 8x and 11.025x sample rate streams. 2027e4710376SSameer Pujar */ 2028e4710376SSameer Pujar assigned-clock-rates = <258000000>; 2029e4710376SSameer Pujar 2030e4710376SSameer Pujar iommus = <&smmu TEGRA186_SID_APE>; 2031e4710376SSameer Pujar }; 2032e4710376SSameer Pujar 203315274c23SMikko Perttunen thermal-zones { 2034fe57ff53SThierry Reding /* Cortex-A57 cluster */ 2035fe57ff53SThierry Reding cpu-thermal { 203615274c23SMikko Perttunen polling-delay = <0>; 203715274c23SMikko Perttunen polling-delay-passive = <1000>; 203815274c23SMikko Perttunen 2039fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 204015274c23SMikko Perttunen 204115274c23SMikko Perttunen trips { 204215274c23SMikko Perttunen critical { 204315274c23SMikko Perttunen temperature = <101000>; 204415274c23SMikko Perttunen hysteresis = <0>; 204515274c23SMikko Perttunen type = "critical"; 204615274c23SMikko Perttunen }; 204715274c23SMikko Perttunen }; 204815274c23SMikko Perttunen 204915274c23SMikko Perttunen cooling-maps { 205015274c23SMikko Perttunen }; 205115274c23SMikko Perttunen }; 205215274c23SMikko Perttunen 2053fe57ff53SThierry Reding /* Denver cluster */ 2054fe57ff53SThierry Reding aux-thermal { 205515274c23SMikko Perttunen polling-delay = <0>; 205615274c23SMikko Perttunen polling-delay-passive = <1000>; 205715274c23SMikko Perttunen 2058fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 205915274c23SMikko Perttunen 206015274c23SMikko Perttunen trips { 206115274c23SMikko Perttunen critical { 206215274c23SMikko Perttunen temperature = <101000>; 206315274c23SMikko Perttunen hysteresis = <0>; 206415274c23SMikko Perttunen type = "critical"; 206515274c23SMikko Perttunen }; 206615274c23SMikko Perttunen }; 206715274c23SMikko Perttunen 206815274c23SMikko Perttunen cooling-maps { 206915274c23SMikko Perttunen }; 207015274c23SMikko Perttunen }; 207115274c23SMikko Perttunen 2072fe57ff53SThierry Reding gpu-thermal { 207315274c23SMikko Perttunen polling-delay = <0>; 207415274c23SMikko Perttunen polling-delay-passive = <1000>; 207515274c23SMikko Perttunen 2076fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 207715274c23SMikko Perttunen 207815274c23SMikko Perttunen trips { 207915274c23SMikko Perttunen critical { 208015274c23SMikko Perttunen temperature = <101000>; 208115274c23SMikko Perttunen hysteresis = <0>; 208215274c23SMikko Perttunen type = "critical"; 208315274c23SMikko Perttunen }; 208415274c23SMikko Perttunen }; 208515274c23SMikko Perttunen 208615274c23SMikko Perttunen cooling-maps { 208715274c23SMikko Perttunen }; 208815274c23SMikko Perttunen }; 208915274c23SMikko Perttunen 2090fe57ff53SThierry Reding pll-thermal { 209115274c23SMikko Perttunen polling-delay = <0>; 209215274c23SMikko Perttunen polling-delay-passive = <1000>; 209315274c23SMikko Perttunen 2094fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 209515274c23SMikko Perttunen 209615274c23SMikko Perttunen trips { 209715274c23SMikko Perttunen critical { 209815274c23SMikko Perttunen temperature = <101000>; 209915274c23SMikko Perttunen hysteresis = <0>; 210015274c23SMikko Perttunen type = "critical"; 210115274c23SMikko Perttunen }; 210215274c23SMikko Perttunen }; 210315274c23SMikko Perttunen 210415274c23SMikko Perttunen cooling-maps { 210515274c23SMikko Perttunen }; 210615274c23SMikko Perttunen }; 210715274c23SMikko Perttunen 2108fe57ff53SThierry Reding ao-thermal { 210915274c23SMikko Perttunen polling-delay = <0>; 211015274c23SMikko Perttunen polling-delay-passive = <1000>; 211115274c23SMikko Perttunen 2112fe57ff53SThierry Reding thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 211315274c23SMikko Perttunen 211415274c23SMikko Perttunen trips { 211515274c23SMikko Perttunen critical { 211615274c23SMikko Perttunen temperature = <101000>; 211715274c23SMikko Perttunen hysteresis = <0>; 211815274c23SMikko Perttunen type = "critical"; 211915274c23SMikko Perttunen }; 212015274c23SMikko Perttunen }; 212115274c23SMikko Perttunen 212215274c23SMikko Perttunen cooling-maps { 212315274c23SMikko Perttunen }; 212415274c23SMikko Perttunen }; 212539cb62cbSJoseph Lo }; 212639cb62cbSJoseph Lo 212739cb62cbSJoseph Lo timer { 212839cb62cbSJoseph Lo compatible = "arm,armv8-timer"; 212939cb62cbSJoseph Lo interrupts = <GIC_PPI 13 213039cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 213139cb62cbSJoseph Lo <GIC_PPI 14 213239cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 213339cb62cbSJoseph Lo <GIC_PPI 11 213439cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 213539cb62cbSJoseph Lo <GIC_PPI 10 213639cb62cbSJoseph Lo (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 213739cb62cbSJoseph Lo interrupt-parent = <&gic>; 2138b30be673SThierry Reding always-on; 213939cb62cbSJoseph Lo }; 214039cb62cbSJoseph Lo}; 2141