18aeca97bSGrzegorz Jaszczyk// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28aeca97bSGrzegorz Jaszczyk/* 38aeca97bSGrzegorz Jaszczyk * Copyright (C) 2019 Marvell International Ltd. 48aeca97bSGrzegorz Jaszczyk * 58aeca97bSGrzegorz Jaszczyk * Device tree for the CN9130-DB board. 68aeca97bSGrzegorz Jaszczyk */ 78aeca97bSGrzegorz Jaszczyk 8*4c43a41eSKonstantin Porotchkin#include "cn9130-db.dtsi" 98aeca97bSGrzegorz Jaszczyk 108aeca97bSGrzegorz Jaszczyk/ { 11*4c43a41eSKonstantin Porotchkin model = "Marvell Armada CN9130-DB setup A"; 128aeca97bSGrzegorz Jaszczyk}; 138aeca97bSGrzegorz Jaszczyk 14*4c43a41eSKonstantin Porotchkin/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. 15*4c43a41eSKonstantin Porotchkin * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated 16*4c43a41eSKonstantin Porotchkin * simultaneously. When SPI controller is enabled, NAND should be disabled. 178aeca97bSGrzegorz Jaszczyk */ 188aeca97bSGrzegorz Jaszczyk 198aeca97bSGrzegorz Jaszczyk&cp0_spi1 { 208aeca97bSGrzegorz Jaszczyk status = "okay"; 218aeca97bSGrzegorz Jaszczyk}; 228aeca97bSGrzegorz Jaszczyk 23