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Revision tags: v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49 |
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| #
4c43a41e |
| 08-Jul-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arm64: dts: cn913x: add device trees for topology B boards
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are b
arm64: dts: cn913x: add device trees for topology B boards
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
show more ...
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Revision tags: v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15 |
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| #
e3850467 |
| 09-Feb-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
show more ...
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| #
99fa8ac5 |
| 07-Mar-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arm64: dts: marvell: enable CP110 UTMI PHY usage
Enable support for CP110 UTMI PHY in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-b
arm64: dts: marvell: enable CP110 UTMI PHY usage
Enable support for CP110 UTMI PHY in Armada SoC family platform
device trees.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
show more ...
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Revision tags: v5.10.14 |
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| #
e8ff9d59 |
| 12-Jan-2021 |
Marcin Wojtas <mw@semihalf.com> |
arm64: dts: cn913x-db: enable MMC HS400
This patch adds necessary flags in the device tree
which enable HS400 mode on AP807 MMC controller
on the CN913x-DB board.
Signed-off-by: Marcin Wojtas <mw@s
arm64: dts: cn913x-db: enable MMC HS400
This patch adds necessary flags in the device tree
which enable HS400 mode on AP807 MMC controller
on the CN913x-DB board.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
show more ...
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| #
d3ba15fb |
| 09-Feb-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
[ Upstream commit e3850467bf8c82de4a052619136839fe8054b774 ]
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Kon
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
[ Upstream commit e3850467bf8c82de4a052619136839fe8054b774 ]
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
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| #
8aeca97b |
| 04-Oct-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
arm64: dts: marvell: Add support for Marvell CN9130-DB
Add basic support for the Marvell CN9130 modular development board. It
is based on a CN9130 SoC (one AP807 and one internal CP115), extended
vi
arm64: dts: marvell: Add support for Marvell CN9130-DB
Add basic support for the Marvell CN9130 modular development board. It
is based on a CN9130 SoC (one AP807 and one internal CP115), extended
via 2xMoCi interface to possibly add up to two more external CP115
(one located on the main board and the other on the board extension).
Available interfaces:
* AP UART
* AP eMMC
* AP SDHCI (disabled)
* CPO GPIO-0
* CPO GPIO-1
* CP0 CRYPTO-0 (disabled)
* CP0 I2C-0
* CP0 I2C-1
* CP0 SDHCI-0
* CP0 NAND-0
* CP0 SPI-1
* CP0 ETH-0 (SFI with SFP cage not working yet, disabled)
* CP0 ETH-1 (RGMII)
* CP0 ETH-2 (RGMII)
* CP0 SATA-0-1
* CP0 USB3-0 (High-speed only)
* CP0 USB3-1 (High-speed only)
* CP0 PCIe-0 x4
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
show more ...
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| #
d3ba15fb |
| 09-Feb-2021 |
Konstantin Porotchkin <kostap@marvell.com> |
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
[ Upstream commit e3850467bf8c82de4a052619136839fe8054b774 ]
Eliminate 1MB gap between Linux and filesystem partitions.
arch/arm64/boot/dts/marvell: fix NAND partitioning scheme
[ Upstream commit e3850467bf8c82de4a052619136839fe8054b774 ]
Eliminate 1MB gap between Linux and filesystem partitions.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
|
|
Revision tags: v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
|
| #
8aeca97b |
| 04-Oct-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
arm64: dts: marvell: Add support for Marvell CN9130-DB
Add basic support for the Marvell CN9130 modular development board. It
is based on a CN9130 SoC (one AP807 and one internal CP115),
arm64: dts: marvell: Add support for Marvell CN9130-DB
Add basic support for the Marvell CN9130 modular development board. It
is based on a CN9130 SoC (one AP807 and one internal CP115), extended
via 2xMoCi interface to possibly add up to two more external CP115
(one located on the main board and the other on the board extension).
Available interfaces:
* AP UART
* AP eMMC
* AP SDHCI (disabled)
* CPO GPIO-0
* CPO GPIO-1
* CP0 CRYPTO-0 (disabled)
* CP0 I2C-0
* CP0 I2C-1
* CP0 SDHCI-0
* CP0 NAND-0
* CP0 SPI-1
* CP0 ETH-0 (SFI with SFP cage not working yet, disabled)
* CP0 ETH-1 (RGMII)
* CP0 ETH-2 (RGMII)
* CP0 SATA-0-1
* CP0 USB3-0 (High-speed only)
* CP0 USB3-1 (High-speed only)
* CP0 PCIe-0 x4
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
show more ...
|