1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22		mmc0 = &sdhci0;
23		mmc1 = &sdhci1;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@0 {
31		device_type = "memory";
32		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
33	};
34
35	leds {
36		compatible = "gpio-leds";
37		red {
38			label = "mox:red:activity";
39			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
40			linux,default-trigger = "default-on";
41		};
42	};
43
44	gpio-keys {
45		compatible = "gpio-keys";
46
47		reset {
48			label = "reset";
49			linux,code = <KEY_RESTART>;
50			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
51			debounce-interval = <60>;
52		};
53	};
54
55	exp_usb3_vbus: usb3-vbus {
56		compatible = "regulator-fixed";
57		regulator-name = "usb3-vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		enable-active-high;
61		regulator-always-on;
62		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
63	};
64
65	vsdc_reg: vsdc-reg {
66		compatible = "regulator-gpio";
67		regulator-name = "vsdc";
68		regulator-min-microvolt = <1800000>;
69		regulator-max-microvolt = <3300000>;
70		regulator-boot-on;
71
72		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
73		gpios-states = <0>;
74		states = <1800000 0x1
75			  3300000 0x0>;
76		enable-active-high;
77	};
78
79	vsdio_reg: vsdio-reg {
80		compatible = "regulator-gpio";
81		regulator-name = "vsdio";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <3300000>;
84		regulator-boot-on;
85
86		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
87		gpios-states = <0>;
88		states = <1800000 0x1
89			  3300000 0x0>;
90		enable-active-high;
91	};
92
93	sdhci1_pwrseq: sdhci1-pwrseq {
94		compatible = "mmc-pwrseq-simple";
95		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
96		status = "okay";
97	};
98
99	sfp: sfp {
100		compatible = "sff,sfp";
101		i2c-bus = <&i2c0>;
102		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
103		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
104		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
105		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
106		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
107		maximum-power-milliwatt = <3000>;
108
109		/* enabled by U-Boot if SFP module is present */
110		status = "disabled";
111	};
112
113	firmware {
114		armada-3700-rwtm {
115			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
116		};
117	};
118};
119
120&i2c0 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&i2c1_pins>;
123	clock-frequency = <100000>;
124	/delete-property/ mrvl,i2c-fast-mode;
125	status = "okay";
126
127	rtc@6f {
128		compatible = "microchip,mcp7940x";
129		reg = <0x6f>;
130	};
131};
132
133&pcie0 {
134	pinctrl-names = "default";
135	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
136	status = "okay";
137	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
138
139	/* enabled by U-Boot if PCIe module is present */
140	status = "disabled";
141};
142
143&uart0 {
144	status = "okay";
145};
146
147&eth0 {
148	pinctrl-names = "default";
149	pinctrl-0 = <&rgmii_pins>;
150	phy-mode = "rgmii-id";
151	phy-handle = <&phy1>;
152	status = "okay";
153};
154
155&eth1 {
156	phy-mode = "2500base-x";
157	managed = "in-band-status";
158	phys = <&comphy0 1>;
159};
160
161&sdhci0 {
162	wp-inverted;
163	bus-width = <4>;
164	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
165	vqmmc-supply = <&vsdc_reg>;
166	marvell,pad-type = "sd";
167	status = "okay";
168};
169
170&sdhci1 {
171	pinctrl-names = "default";
172	pinctrl-0 = <&sdio_pins>;
173	non-removable;
174	bus-width = <4>;
175	marvell,pad-type = "sd";
176	vqmmc-supply = <&vsdio_reg>;
177	mmc-pwrseq = <&sdhci1_pwrseq>;
178	/* forbid SDR104 for FCC purposes */
179	sdhci-caps-mask = <0x2 0x0>;
180	status = "okay";
181};
182
183&spi0 {
184	status = "okay";
185	pinctrl-names = "default";
186	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
187	assigned-clocks = <&nb_periph_clk 7>;
188	assigned-clock-parents = <&tbg 1>;
189	assigned-clock-rates = <20000000>;
190
191	spi-flash@0 {
192		#address-cells = <1>;
193		#size-cells = <1>;
194		compatible = "jedec,spi-nor";
195		reg = <0>;
196		spi-max-frequency = <20000000>;
197
198		partitions {
199			compatible = "fixed-partitions";
200			#address-cells = <1>;
201			#size-cells = <1>;
202
203			partition@0 {
204				label = "secure-firmware";
205				reg = <0x0 0x20000>;
206			};
207
208			partition@20000 {
209				label = "a53-firmware";
210				reg = <0x20000 0x160000>;
211			};
212
213			partition@180000 {
214				label = "u-boot-env";
215				reg = <0x180000 0x10000>;
216			};
217
218			partition@190000 {
219				label = "Rescue system";
220				reg = <0x190000 0x660000>;
221			};
222
223			partition@7f0000 {
224				label = "dtb";
225				reg = <0x7f0000 0x10000>;
226			};
227		};
228	};
229
230	moxtet: moxtet@1 {
231		#address-cells = <1>;
232		#size-cells = <0>;
233		compatible = "cznic,moxtet";
234		reg = <1>;
235		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
236		spi-max-frequency = <10000000>;
237		spi-cpol;
238		spi-cpha;
239		interrupt-controller;
240		#interrupt-cells = <1>;
241		interrupt-parent = <&gpiosb>;
242		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
243		status = "okay";
244
245		moxtet_sfp: gpio@0 {
246			compatible = "cznic,moxtet-gpio";
247			gpio-controller;
248			#gpio-cells = <2>;
249			reg = <0>;
250			status = "disabled";
251		};
252	};
253};
254
255&usb2 {
256	status = "okay";
257};
258
259&comphy2 {
260	connector {
261		compatible = "usb-a-connector";
262		phy-supply = <&exp_usb3_vbus>;
263	};
264};
265
266&usb3 {
267	status = "okay";
268	phys = <&comphy2 0>;
269};
270
271&mdio {
272	pinctrl-names = "default";
273	pinctrl-0 = <&smi_pins>;
274	status = "okay";
275
276	phy1: ethernet-phy@1 {
277		reg = <1>;
278	};
279
280	/* switch nodes are enabled by U-Boot if modules are present */
281	switch0@10 {
282		compatible = "marvell,mv88e6190";
283		reg = <0x10 0>;
284		dsa,member = <0 0>;
285		interrupt-parent = <&moxtet>;
286		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
287		status = "disabled";
288
289		mdio {
290			#address-cells = <1>;
291			#size-cells = <0>;
292
293			switch0phy1: switch0phy1@1 {
294				reg = <0x1>;
295			};
296
297			switch0phy2: switch0phy2@2 {
298				reg = <0x2>;
299			};
300
301			switch0phy3: switch0phy3@3 {
302				reg = <0x3>;
303			};
304
305			switch0phy4: switch0phy4@4 {
306				reg = <0x4>;
307			};
308
309			switch0phy5: switch0phy5@5 {
310				reg = <0x5>;
311			};
312
313			switch0phy6: switch0phy6@6 {
314				reg = <0x6>;
315			};
316
317			switch0phy7: switch0phy7@7 {
318				reg = <0x7>;
319			};
320
321			switch0phy8: switch0phy8@8 {
322				reg = <0x8>;
323			};
324		};
325
326		ports {
327			#address-cells = <1>;
328			#size-cells = <0>;
329
330			port@1 {
331				reg = <0x1>;
332				label = "lan1";
333				phy-handle = <&switch0phy1>;
334			};
335
336			port@2 {
337				reg = <0x2>;
338				label = "lan2";
339				phy-handle = <&switch0phy2>;
340			};
341
342			port@3 {
343				reg = <0x3>;
344				label = "lan3";
345				phy-handle = <&switch0phy3>;
346			};
347
348			port@4 {
349				reg = <0x4>;
350				label = "lan4";
351				phy-handle = <&switch0phy4>;
352			};
353
354			port@5 {
355				reg = <0x5>;
356				label = "lan5";
357				phy-handle = <&switch0phy5>;
358			};
359
360			port@6 {
361				reg = <0x6>;
362				label = "lan6";
363				phy-handle = <&switch0phy6>;
364			};
365
366			port@7 {
367				reg = <0x7>;
368				label = "lan7";
369				phy-handle = <&switch0phy7>;
370			};
371
372			port@8 {
373				reg = <0x8>;
374				label = "lan8";
375				phy-handle = <&switch0phy8>;
376			};
377
378			port@9 {
379				reg = <0x9>;
380				label = "cpu";
381				ethernet = <&eth1>;
382				phy-mode = "2500base-x";
383				managed = "in-band-status";
384			};
385
386			switch0port10: port@a {
387				reg = <0xa>;
388				label = "dsa";
389				phy-mode = "2500base-x";
390				managed = "in-band-status";
391				link = <&switch1port9 &switch2port9>;
392				status = "disabled";
393			};
394
395			port-sfp@a {
396				reg = <0xa>;
397				label = "sfp";
398				sfp = <&sfp>;
399				phy-mode = "sgmii";
400				managed = "in-band-status";
401				status = "disabled";
402			};
403		};
404	};
405
406	switch0@2 {
407		compatible = "marvell,mv88e6085";
408		reg = <0x2 0>;
409		dsa,member = <0 0>;
410		interrupt-parent = <&moxtet>;
411		interrupts = <MOXTET_IRQ_TOPAZ>;
412		status = "disabled";
413
414		mdio {
415			#address-cells = <1>;
416			#size-cells = <0>;
417
418			switch0phy1_topaz: switch0phy1@11 {
419				reg = <0x11>;
420			};
421
422			switch0phy2_topaz: switch0phy2@12 {
423				reg = <0x12>;
424			};
425
426			switch0phy3_topaz: switch0phy3@13 {
427				reg = <0x13>;
428			};
429
430			switch0phy4_topaz: switch0phy4@14 {
431				reg = <0x14>;
432			};
433		};
434
435		ports {
436			#address-cells = <1>;
437			#size-cells = <0>;
438
439			port@1 {
440				reg = <0x1>;
441				label = "lan1";
442				phy-handle = <&switch0phy1_topaz>;
443			};
444
445			port@2 {
446				reg = <0x2>;
447				label = "lan2";
448				phy-handle = <&switch0phy2_topaz>;
449			};
450
451			port@3 {
452				reg = <0x3>;
453				label = "lan3";
454				phy-handle = <&switch0phy3_topaz>;
455			};
456
457			port@4 {
458				reg = <0x4>;
459				label = "lan4";
460				phy-handle = <&switch0phy4_topaz>;
461			};
462
463			port@5 {
464				reg = <0x5>;
465				label = "cpu";
466				phy-mode = "2500base-x";
467				managed = "in-band-status";
468				ethernet = <&eth1>;
469			};
470		};
471	};
472
473	switch1@11 {
474		compatible = "marvell,mv88e6190";
475		reg = <0x11 0>;
476		dsa,member = <0 1>;
477		interrupt-parent = <&moxtet>;
478		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
479		status = "disabled";
480
481		mdio {
482			#address-cells = <1>;
483			#size-cells = <0>;
484
485			switch1phy1: switch1phy1@1 {
486				reg = <0x1>;
487			};
488
489			switch1phy2: switch1phy2@2 {
490				reg = <0x2>;
491			};
492
493			switch1phy3: switch1phy3@3 {
494				reg = <0x3>;
495			};
496
497			switch1phy4: switch1phy4@4 {
498				reg = <0x4>;
499			};
500
501			switch1phy5: switch1phy5@5 {
502				reg = <0x5>;
503			};
504
505			switch1phy6: switch1phy6@6 {
506				reg = <0x6>;
507			};
508
509			switch1phy7: switch1phy7@7 {
510				reg = <0x7>;
511			};
512
513			switch1phy8: switch1phy8@8 {
514				reg = <0x8>;
515			};
516		};
517
518		ports {
519			#address-cells = <1>;
520			#size-cells = <0>;
521
522			port@1 {
523				reg = <0x1>;
524				label = "lan9";
525				phy-handle = <&switch1phy1>;
526			};
527
528			port@2 {
529				reg = <0x2>;
530				label = "lan10";
531				phy-handle = <&switch1phy2>;
532			};
533
534			port@3 {
535				reg = <0x3>;
536				label = "lan11";
537				phy-handle = <&switch1phy3>;
538			};
539
540			port@4 {
541				reg = <0x4>;
542				label = "lan12";
543				phy-handle = <&switch1phy4>;
544			};
545
546			port@5 {
547				reg = <0x5>;
548				label = "lan13";
549				phy-handle = <&switch1phy5>;
550			};
551
552			port@6 {
553				reg = <0x6>;
554				label = "lan14";
555				phy-handle = <&switch1phy6>;
556			};
557
558			port@7 {
559				reg = <0x7>;
560				label = "lan15";
561				phy-handle = <&switch1phy7>;
562			};
563
564			port@8 {
565				reg = <0x8>;
566				label = "lan16";
567				phy-handle = <&switch1phy8>;
568			};
569
570			switch1port9: port@9 {
571				reg = <0x9>;
572				label = "dsa";
573				phy-mode = "2500base-x";
574				managed = "in-band-status";
575				link = <&switch0port10>;
576			};
577
578			switch1port10: port@a {
579				reg = <0xa>;
580				label = "dsa";
581				phy-mode = "2500base-x";
582				managed = "in-band-status";
583				link = <&switch2port9>;
584				status = "disabled";
585			};
586
587			port-sfp@a {
588				reg = <0xa>;
589				label = "sfp";
590				sfp = <&sfp>;
591				phy-mode = "sgmii";
592				managed = "in-band-status";
593				status = "disabled";
594			};
595		};
596	};
597
598	switch1@2 {
599		compatible = "marvell,mv88e6085";
600		reg = <0x2 0>;
601		dsa,member = <0 1>;
602		interrupt-parent = <&moxtet>;
603		interrupts = <MOXTET_IRQ_TOPAZ>;
604		status = "disabled";
605
606		mdio {
607			#address-cells = <1>;
608			#size-cells = <0>;
609
610			switch1phy1_topaz: switch1phy1@11 {
611				reg = <0x11>;
612			};
613
614			switch1phy2_topaz: switch1phy2@12 {
615				reg = <0x12>;
616			};
617
618			switch1phy3_topaz: switch1phy3@13 {
619				reg = <0x13>;
620			};
621
622			switch1phy4_topaz: switch1phy4@14 {
623				reg = <0x14>;
624			};
625		};
626
627		ports {
628			#address-cells = <1>;
629			#size-cells = <0>;
630
631			port@1 {
632				reg = <0x1>;
633				label = "lan9";
634				phy-handle = <&switch1phy1_topaz>;
635			};
636
637			port@2 {
638				reg = <0x2>;
639				label = "lan10";
640				phy-handle = <&switch1phy2_topaz>;
641			};
642
643			port@3 {
644				reg = <0x3>;
645				label = "lan11";
646				phy-handle = <&switch1phy3_topaz>;
647			};
648
649			port@4 {
650				reg = <0x4>;
651				label = "lan12";
652				phy-handle = <&switch1phy4_topaz>;
653			};
654
655			port@5 {
656				reg = <0x5>;
657				label = "dsa";
658				phy-mode = "2500base-x";
659				managed = "in-band-status";
660				link = <&switch0port10>;
661			};
662		};
663	};
664
665	switch2@12 {
666		compatible = "marvell,mv88e6190";
667		reg = <0x12 0>;
668		dsa,member = <0 2>;
669		interrupt-parent = <&moxtet>;
670		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
671		status = "disabled";
672
673		mdio {
674			#address-cells = <1>;
675			#size-cells = <0>;
676
677			switch2phy1: switch2phy1@1 {
678				reg = <0x1>;
679			};
680
681			switch2phy2: switch2phy2@2 {
682				reg = <0x2>;
683			};
684
685			switch2phy3: switch2phy3@3 {
686				reg = <0x3>;
687			};
688
689			switch2phy4: switch2phy4@4 {
690				reg = <0x4>;
691			};
692
693			switch2phy5: switch2phy5@5 {
694				reg = <0x5>;
695			};
696
697			switch2phy6: switch2phy6@6 {
698				reg = <0x6>;
699			};
700
701			switch2phy7: switch2phy7@7 {
702				reg = <0x7>;
703			};
704
705			switch2phy8: switch2phy8@8 {
706				reg = <0x8>;
707			};
708		};
709
710		ports {
711			#address-cells = <1>;
712			#size-cells = <0>;
713
714			port@1 {
715				reg = <0x1>;
716				label = "lan17";
717				phy-handle = <&switch2phy1>;
718			};
719
720			port@2 {
721				reg = <0x2>;
722				label = "lan18";
723				phy-handle = <&switch2phy2>;
724			};
725
726			port@3 {
727				reg = <0x3>;
728				label = "lan19";
729				phy-handle = <&switch2phy3>;
730			};
731
732			port@4 {
733				reg = <0x4>;
734				label = "lan20";
735				phy-handle = <&switch2phy4>;
736			};
737
738			port@5 {
739				reg = <0x5>;
740				label = "lan21";
741				phy-handle = <&switch2phy5>;
742			};
743
744			port@6 {
745				reg = <0x6>;
746				label = "lan22";
747				phy-handle = <&switch2phy6>;
748			};
749
750			port@7 {
751				reg = <0x7>;
752				label = "lan23";
753				phy-handle = <&switch2phy7>;
754			};
755
756			port@8 {
757				reg = <0x8>;
758				label = "lan24";
759				phy-handle = <&switch2phy8>;
760			};
761
762			switch2port9: port@9 {
763				reg = <0x9>;
764				label = "dsa";
765				phy-mode = "2500base-x";
766				managed = "in-band-status";
767				link = <&switch1port10 &switch0port10>;
768			};
769
770			port-sfp@a {
771				reg = <0xa>;
772				label = "sfp";
773				sfp = <&sfp>;
774				phy-mode = "sgmii";
775				managed = "in-band-status";
776				status = "disabled";
777			};
778		};
779	};
780
781	switch2@2 {
782		compatible = "marvell,mv88e6085";
783		reg = <0x2 0>;
784		dsa,member = <0 2>;
785		interrupt-parent = <&moxtet>;
786		interrupts = <MOXTET_IRQ_TOPAZ>;
787		status = "disabled";
788
789		mdio {
790			#address-cells = <1>;
791			#size-cells = <0>;
792
793			switch2phy1_topaz: switch2phy1@11 {
794				reg = <0x11>;
795			};
796
797			switch2phy2_topaz: switch2phy2@12 {
798				reg = <0x12>;
799			};
800
801			switch2phy3_topaz: switch2phy3@13 {
802				reg = <0x13>;
803			};
804
805			switch2phy4_topaz: switch2phy4@14 {
806				reg = <0x14>;
807			};
808		};
809
810		ports {
811			#address-cells = <1>;
812			#size-cells = <0>;
813
814			port@1 {
815				reg = <0x1>;
816				label = "lan17";
817				phy-handle = <&switch2phy1_topaz>;
818			};
819
820			port@2 {
821				reg = <0x2>;
822				label = "lan18";
823				phy-handle = <&switch2phy2_topaz>;
824			};
825
826			port@3 {
827				reg = <0x3>;
828				label = "lan19";
829				phy-handle = <&switch2phy3_topaz>;
830			};
831
832			port@4 {
833				reg = <0x4>;
834				label = "lan20";
835				phy-handle = <&switch2phy4_topaz>;
836			};
837
838			port@5 {
839				reg = <0x5>;
840				label = "dsa";
841				phy-mode = "2500base-x";
842				managed = "in-band-status";
843				link = <&switch1port10 &switch0port10>;
844			};
845		};
846	};
847};
848