1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	vsdc_reg: vsdc-reg {
64		compatible = "regulator-gpio";
65		regulator-name = "vsdc";
66		regulator-min-microvolt = <1800000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-boot-on;
69
70		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
71		gpios-states = <0>;
72		states = <1800000 0x1
73			  3300000 0x0>;
74		enable-active-high;
75	};
76
77	vsdio_reg: vsdio-reg {
78		compatible = "regulator-gpio";
79		regulator-name = "vsdio";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		regulator-boot-on;
83
84		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
85		gpios-states = <0>;
86		states = <1800000 0x1
87			  3300000 0x0>;
88		enable-active-high;
89	};
90
91	sdhci1_pwrseq: sdhci1-pwrseq {
92		compatible = "mmc-pwrseq-simple";
93		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
94		status = "okay";
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp";
99		i2c-bus = <&i2c0>;
100		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
105
106		/* enabled by U-Boot if SFP module is present */
107		status = "disabled";
108	};
109
110	firmware {
111		armada-3700-rwtm {
112			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
113		};
114	};
115};
116
117&i2c0 {
118	pinctrl-names = "default";
119	pinctrl-0 = <&i2c1_pins>;
120	clock-frequency = <100000>;
121	status = "okay";
122
123	rtc@6f {
124		compatible = "microchip,mcp7940x";
125		reg = <0x6f>;
126	};
127};
128
129&pcie0 {
130	pinctrl-names = "default";
131	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
132	status = "okay";
133	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
134
135	/* enabled by U-Boot if PCIe module is present */
136	status = "disabled";
137};
138
139&uart0 {
140	status = "okay";
141};
142
143&eth0 {
144	pinctrl-names = "default";
145	pinctrl-0 = <&rgmii_pins>;
146	phy-mode = "rgmii-id";
147	phy-handle = <&phy1>;
148	status = "okay";
149};
150
151&eth1 {
152	phy-mode = "2500base-x";
153	managed = "in-band-status";
154	phys = <&comphy0 1>;
155};
156
157&sdhci0 {
158	wp-inverted;
159	bus-width = <4>;
160	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
161	vqmmc-supply = <&vsdc_reg>;
162	marvell,pad-type = "sd";
163	status = "okay";
164};
165
166&sdhci1 {
167	pinctrl-names = "default";
168	pinctrl-0 = <&sdio_pins>;
169	non-removable;
170	bus-width = <4>;
171	marvell,pad-type = "sd";
172	vqmmc-supply = <&vsdio_reg>;
173	mmc-pwrseq = <&sdhci1_pwrseq>;
174	/* forbid SDR104 for FCC purposes */
175	sdhci-caps-mask = <0x2 0x0>;
176	status = "okay";
177};
178
179&spi0 {
180	status = "okay";
181	pinctrl-names = "default";
182	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
183	assigned-clocks = <&nb_periph_clk 7>;
184	assigned-clock-parents = <&tbg 1>;
185	assigned-clock-rates = <20000000>;
186
187	spi-flash@0 {
188		#address-cells = <1>;
189		#size-cells = <1>;
190		compatible = "jedec,spi-nor";
191		reg = <0>;
192		spi-max-frequency = <20000000>;
193
194		partitions {
195			compatible = "fixed-partitions";
196			#address-cells = <1>;
197			#size-cells = <1>;
198
199			partition@0 {
200				label = "secure-firmware";
201				reg = <0x0 0x20000>;
202			};
203
204			partition@20000 {
205				label = "a53-firmware";
206				reg = <0x20000 0x160000>;
207			};
208
209			partition@180000 {
210				label = "u-boot-env";
211				reg = <0x180000 0x10000>;
212			};
213
214			partition@190000 {
215				label = "Rescue system";
216				reg = <0x190000 0x660000>;
217			};
218
219			partition@7f0000 {
220				label = "dtb";
221				reg = <0x7f0000 0x10000>;
222			};
223		};
224	};
225
226	moxtet: moxtet@1 {
227		#address-cells = <1>;
228		#size-cells = <0>;
229		compatible = "cznic,moxtet";
230		reg = <1>;
231		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
232		spi-max-frequency = <10000000>;
233		spi-cpol;
234		spi-cpha;
235		interrupt-controller;
236		#interrupt-cells = <1>;
237		interrupt-parent = <&gpiosb>;
238		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
239		status = "okay";
240
241		moxtet_sfp: gpio@0 {
242			compatible = "cznic,moxtet-gpio";
243			gpio-controller;
244			#gpio-cells = <2>;
245			reg = <0>;
246			status = "disabled";
247		};
248	};
249};
250
251&usb2 {
252	status = "okay";
253};
254
255&comphy2 {
256	connector {
257		compatible = "usb-a-connector";
258		phy-supply = <&exp_usb3_vbus>;
259	};
260};
261
262&usb3 {
263	status = "okay";
264	phys = <&comphy2 0>;
265};
266
267&mdio {
268	pinctrl-names = "default";
269	pinctrl-0 = <&smi_pins>;
270	status = "okay";
271
272	phy1: ethernet-phy@1 {
273		reg = <1>;
274	};
275
276	/* switch nodes are enabled by U-Boot if modules are present */
277	switch0@10 {
278		compatible = "marvell,mv88e6190";
279		reg = <0x10 0>;
280		dsa,member = <0 0>;
281		interrupt-parent = <&moxtet>;
282		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
283		status = "disabled";
284
285		mdio {
286			#address-cells = <1>;
287			#size-cells = <0>;
288
289			switch0phy1: switch0phy1@1 {
290				reg = <0x1>;
291			};
292
293			switch0phy2: switch0phy2@2 {
294				reg = <0x2>;
295			};
296
297			switch0phy3: switch0phy3@3 {
298				reg = <0x3>;
299			};
300
301			switch0phy4: switch0phy4@4 {
302				reg = <0x4>;
303			};
304
305			switch0phy5: switch0phy5@5 {
306				reg = <0x5>;
307			};
308
309			switch0phy6: switch0phy6@6 {
310				reg = <0x6>;
311			};
312
313			switch0phy7: switch0phy7@7 {
314				reg = <0x7>;
315			};
316
317			switch0phy8: switch0phy8@8 {
318				reg = <0x8>;
319			};
320		};
321
322		ports {
323			#address-cells = <1>;
324			#size-cells = <0>;
325
326			port@1 {
327				reg = <0x1>;
328				label = "lan1";
329				phy-handle = <&switch0phy1>;
330			};
331
332			port@2 {
333				reg = <0x2>;
334				label = "lan2";
335				phy-handle = <&switch0phy2>;
336			};
337
338			port@3 {
339				reg = <0x3>;
340				label = "lan3";
341				phy-handle = <&switch0phy3>;
342			};
343
344			port@4 {
345				reg = <0x4>;
346				label = "lan4";
347				phy-handle = <&switch0phy4>;
348			};
349
350			port@5 {
351				reg = <0x5>;
352				label = "lan5";
353				phy-handle = <&switch0phy5>;
354			};
355
356			port@6 {
357				reg = <0x6>;
358				label = "lan6";
359				phy-handle = <&switch0phy6>;
360			};
361
362			port@7 {
363				reg = <0x7>;
364				label = "lan7";
365				phy-handle = <&switch0phy7>;
366			};
367
368			port@8 {
369				reg = <0x8>;
370				label = "lan8";
371				phy-handle = <&switch0phy8>;
372			};
373
374			port@9 {
375				reg = <0x9>;
376				label = "cpu";
377				ethernet = <&eth1>;
378				phy-mode = "2500base-x";
379				managed = "in-band-status";
380			};
381
382			switch0port10: port@a {
383				reg = <0xa>;
384				label = "dsa";
385				phy-mode = "2500base-x";
386				managed = "in-band-status";
387				link = <&switch1port9 &switch2port9>;
388				status = "disabled";
389			};
390
391			port-sfp@a {
392				reg = <0xa>;
393				label = "sfp";
394				sfp = <&sfp>;
395				phy-mode = "sgmii";
396				managed = "in-band-status";
397				status = "disabled";
398			};
399		};
400	};
401
402	switch0@2 {
403		compatible = "marvell,mv88e6085";
404		reg = <0x2 0>;
405		dsa,member = <0 0>;
406		interrupt-parent = <&moxtet>;
407		interrupts = <MOXTET_IRQ_TOPAZ>;
408		status = "disabled";
409
410		mdio {
411			#address-cells = <1>;
412			#size-cells = <0>;
413
414			switch0phy1_topaz: switch0phy1@11 {
415				reg = <0x11>;
416			};
417
418			switch0phy2_topaz: switch0phy2@12 {
419				reg = <0x12>;
420			};
421
422			switch0phy3_topaz: switch0phy3@13 {
423				reg = <0x13>;
424			};
425
426			switch0phy4_topaz: switch0phy4@14 {
427				reg = <0x14>;
428			};
429		};
430
431		ports {
432			#address-cells = <1>;
433			#size-cells = <0>;
434
435			port@1 {
436				reg = <0x1>;
437				label = "lan1";
438				phy-handle = <&switch0phy1_topaz>;
439			};
440
441			port@2 {
442				reg = <0x2>;
443				label = "lan2";
444				phy-handle = <&switch0phy2_topaz>;
445			};
446
447			port@3 {
448				reg = <0x3>;
449				label = "lan3";
450				phy-handle = <&switch0phy3_topaz>;
451			};
452
453			port@4 {
454				reg = <0x4>;
455				label = "lan4";
456				phy-handle = <&switch0phy4_topaz>;
457			};
458
459			port@5 {
460				reg = <0x5>;
461				label = "cpu";
462				phy-mode = "2500base-x";
463				managed = "in-band-status";
464				ethernet = <&eth1>;
465			};
466		};
467	};
468
469	switch1@11 {
470		compatible = "marvell,mv88e6190";
471		reg = <0x11 0>;
472		dsa,member = <0 1>;
473		interrupt-parent = <&moxtet>;
474		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
475		status = "disabled";
476
477		mdio {
478			#address-cells = <1>;
479			#size-cells = <0>;
480
481			switch1phy1: switch1phy1@1 {
482				reg = <0x1>;
483			};
484
485			switch1phy2: switch1phy2@2 {
486				reg = <0x2>;
487			};
488
489			switch1phy3: switch1phy3@3 {
490				reg = <0x3>;
491			};
492
493			switch1phy4: switch1phy4@4 {
494				reg = <0x4>;
495			};
496
497			switch1phy5: switch1phy5@5 {
498				reg = <0x5>;
499			};
500
501			switch1phy6: switch1phy6@6 {
502				reg = <0x6>;
503			};
504
505			switch1phy7: switch1phy7@7 {
506				reg = <0x7>;
507			};
508
509			switch1phy8: switch1phy8@8 {
510				reg = <0x8>;
511			};
512		};
513
514		ports {
515			#address-cells = <1>;
516			#size-cells = <0>;
517
518			port@1 {
519				reg = <0x1>;
520				label = "lan9";
521				phy-handle = <&switch1phy1>;
522			};
523
524			port@2 {
525				reg = <0x2>;
526				label = "lan10";
527				phy-handle = <&switch1phy2>;
528			};
529
530			port@3 {
531				reg = <0x3>;
532				label = "lan11";
533				phy-handle = <&switch1phy3>;
534			};
535
536			port@4 {
537				reg = <0x4>;
538				label = "lan12";
539				phy-handle = <&switch1phy4>;
540			};
541
542			port@5 {
543				reg = <0x5>;
544				label = "lan13";
545				phy-handle = <&switch1phy5>;
546			};
547
548			port@6 {
549				reg = <0x6>;
550				label = "lan14";
551				phy-handle = <&switch1phy6>;
552			};
553
554			port@7 {
555				reg = <0x7>;
556				label = "lan15";
557				phy-handle = <&switch1phy7>;
558			};
559
560			port@8 {
561				reg = <0x8>;
562				label = "lan16";
563				phy-handle = <&switch1phy8>;
564			};
565
566			switch1port9: port@9 {
567				reg = <0x9>;
568				label = "dsa";
569				phy-mode = "2500base-x";
570				managed = "in-band-status";
571				link = <&switch0port10>;
572			};
573
574			switch1port10: port@a {
575				reg = <0xa>;
576				label = "dsa";
577				phy-mode = "2500base-x";
578				managed = "in-band-status";
579				link = <&switch2port9>;
580				status = "disabled";
581			};
582
583			port-sfp@a {
584				reg = <0xa>;
585				label = "sfp";
586				sfp = <&sfp>;
587				phy-mode = "sgmii";
588				managed = "in-band-status";
589				status = "disabled";
590			};
591		};
592	};
593
594	switch1@2 {
595		compatible = "marvell,mv88e6085";
596		reg = <0x2 0>;
597		dsa,member = <0 1>;
598		interrupt-parent = <&moxtet>;
599		interrupts = <MOXTET_IRQ_TOPAZ>;
600		status = "disabled";
601
602		mdio {
603			#address-cells = <1>;
604			#size-cells = <0>;
605
606			switch1phy1_topaz: switch1phy1@11 {
607				reg = <0x11>;
608			};
609
610			switch1phy2_topaz: switch1phy2@12 {
611				reg = <0x12>;
612			};
613
614			switch1phy3_topaz: switch1phy3@13 {
615				reg = <0x13>;
616			};
617
618			switch1phy4_topaz: switch1phy4@14 {
619				reg = <0x14>;
620			};
621		};
622
623		ports {
624			#address-cells = <1>;
625			#size-cells = <0>;
626
627			port@1 {
628				reg = <0x1>;
629				label = "lan9";
630				phy-handle = <&switch1phy1_topaz>;
631			};
632
633			port@2 {
634				reg = <0x2>;
635				label = "lan10";
636				phy-handle = <&switch1phy2_topaz>;
637			};
638
639			port@3 {
640				reg = <0x3>;
641				label = "lan11";
642				phy-handle = <&switch1phy3_topaz>;
643			};
644
645			port@4 {
646				reg = <0x4>;
647				label = "lan12";
648				phy-handle = <&switch1phy4_topaz>;
649			};
650
651			port@5 {
652				reg = <0x5>;
653				label = "dsa";
654				phy-mode = "2500base-x";
655				managed = "in-band-status";
656				link = <&switch0port10>;
657			};
658		};
659	};
660
661	switch2@12 {
662		compatible = "marvell,mv88e6190";
663		reg = <0x12 0>;
664		dsa,member = <0 2>;
665		interrupt-parent = <&moxtet>;
666		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
667		status = "disabled";
668
669		mdio {
670			#address-cells = <1>;
671			#size-cells = <0>;
672
673			switch2phy1: switch2phy1@1 {
674				reg = <0x1>;
675			};
676
677			switch2phy2: switch2phy2@2 {
678				reg = <0x2>;
679			};
680
681			switch2phy3: switch2phy3@3 {
682				reg = <0x3>;
683			};
684
685			switch2phy4: switch2phy4@4 {
686				reg = <0x4>;
687			};
688
689			switch2phy5: switch2phy5@5 {
690				reg = <0x5>;
691			};
692
693			switch2phy6: switch2phy6@6 {
694				reg = <0x6>;
695			};
696
697			switch2phy7: switch2phy7@7 {
698				reg = <0x7>;
699			};
700
701			switch2phy8: switch2phy8@8 {
702				reg = <0x8>;
703			};
704		};
705
706		ports {
707			#address-cells = <1>;
708			#size-cells = <0>;
709
710			port@1 {
711				reg = <0x1>;
712				label = "lan17";
713				phy-handle = <&switch2phy1>;
714			};
715
716			port@2 {
717				reg = <0x2>;
718				label = "lan18";
719				phy-handle = <&switch2phy2>;
720			};
721
722			port@3 {
723				reg = <0x3>;
724				label = "lan19";
725				phy-handle = <&switch2phy3>;
726			};
727
728			port@4 {
729				reg = <0x4>;
730				label = "lan20";
731				phy-handle = <&switch2phy4>;
732			};
733
734			port@5 {
735				reg = <0x5>;
736				label = "lan21";
737				phy-handle = <&switch2phy5>;
738			};
739
740			port@6 {
741				reg = <0x6>;
742				label = "lan22";
743				phy-handle = <&switch2phy6>;
744			};
745
746			port@7 {
747				reg = <0x7>;
748				label = "lan23";
749				phy-handle = <&switch2phy7>;
750			};
751
752			port@8 {
753				reg = <0x8>;
754				label = "lan24";
755				phy-handle = <&switch2phy8>;
756			};
757
758			switch2port9: port@9 {
759				reg = <0x9>;
760				label = "dsa";
761				phy-mode = "2500base-x";
762				managed = "in-band-status";
763				link = <&switch1port10 &switch0port10>;
764			};
765
766			port-sfp@a {
767				reg = <0xa>;
768				label = "sfp";
769				sfp = <&sfp>;
770				phy-mode = "sgmii";
771				managed = "in-band-status";
772				status = "disabled";
773			};
774		};
775	};
776
777	switch2@2 {
778		compatible = "marvell,mv88e6085";
779		reg = <0x2 0>;
780		dsa,member = <0 2>;
781		interrupt-parent = <&moxtet>;
782		interrupts = <MOXTET_IRQ_TOPAZ>;
783		status = "disabled";
784
785		mdio {
786			#address-cells = <1>;
787			#size-cells = <0>;
788
789			switch2phy1_topaz: switch2phy1@11 {
790				reg = <0x11>;
791			};
792
793			switch2phy2_topaz: switch2phy2@12 {
794				reg = <0x12>;
795			};
796
797			switch2phy3_topaz: switch2phy3@13 {
798				reg = <0x13>;
799			};
800
801			switch2phy4_topaz: switch2phy4@14 {
802				reg = <0x14>;
803			};
804		};
805
806		ports {
807			#address-cells = <1>;
808			#size-cells = <0>;
809
810			port@1 {
811				reg = <0x1>;
812				label = "lan17";
813				phy-handle = <&switch2phy1_topaz>;
814			};
815
816			port@2 {
817				reg = <0x2>;
818				label = "lan18";
819				phy-handle = <&switch2phy2_topaz>;
820			};
821
822			port@3 {
823				reg = <0x3>;
824				label = "lan19";
825				phy-handle = <&switch2phy3_topaz>;
826			};
827
828			port@4 {
829				reg = <0x4>;
830				label = "lan20";
831				phy-handle = <&switch2phy4_topaz>;
832			};
833
834			port@5 {
835				reg = <0x5>;
836				label = "dsa";
837				phy-mode = "2500base-x";
838				managed = "in-band-status";
839				link = <&switch1port10 &switch0port10>;
840			};
841		};
842	};
843};
844