1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22		mmc0 = &sdhci0;
23		mmc1 = &sdhci1;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@0 {
31		device_type = "memory";
32		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
33	};
34
35	leds {
36		compatible = "gpio-leds";
37		red {
38			label = "mox:red:activity";
39			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
40			linux,default-trigger = "default-on";
41		};
42	};
43
44	gpio-keys {
45		compatible = "gpio-keys";
46
47		reset {
48			label = "reset";
49			linux,code = <KEY_RESTART>;
50			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
51			debounce-interval = <60>;
52		};
53	};
54
55	exp_usb3_vbus: usb3-vbus {
56		compatible = "regulator-fixed";
57		regulator-name = "usb3-vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		enable-active-high;
61		regulator-always-on;
62		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
63	};
64
65	vsdc_reg: vsdc-reg {
66		compatible = "regulator-gpio";
67		regulator-name = "vsdc";
68		regulator-min-microvolt = <1800000>;
69		regulator-max-microvolt = <3300000>;
70		regulator-boot-on;
71
72		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
73		gpios-states = <0>;
74		states = <1800000 0x1
75			  3300000 0x0>;
76		enable-active-high;
77	};
78
79	vsdio_reg: vsdio-reg {
80		compatible = "regulator-gpio";
81		regulator-name = "vsdio";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <3300000>;
84		regulator-boot-on;
85
86		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
87		gpios-states = <0>;
88		states = <1800000 0x1
89			  3300000 0x0>;
90		enable-active-high;
91	};
92
93	sdhci1_pwrseq: sdhci1-pwrseq {
94		compatible = "mmc-pwrseq-simple";
95		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
96		status = "okay";
97	};
98
99	sfp: sfp {
100		compatible = "sff,sfp";
101		i2c-bus = <&i2c0>;
102		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
103		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
104		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
105		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
106		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
107		maximum-power-milliwatt = <3000>;
108
109		/* enabled by U-Boot if SFP module is present */
110		status = "disabled";
111	};
112
113	firmware {
114		armada-3700-rwtm {
115			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
116		};
117	};
118};
119
120&i2c0 {
121	pinctrl-names = "default";
122	pinctrl-0 = <&i2c1_pins>;
123	clock-frequency = <100000>;
124	/delete-property/ mrvl,i2c-fast-mode;
125	status = "okay";
126
127	rtc@6f {
128		compatible = "microchip,mcp7940x";
129		reg = <0x6f>;
130	};
131};
132
133&pcie0 {
134	pinctrl-names = "default";
135	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
136	status = "okay";
137	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
138	/*
139	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
140	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
141	 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
142	 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
143	 * no remapping) and that this address is the lowest from all specified ranges. If these
144	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
145	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
146	 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
147	 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
148	 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
149	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
150	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
151	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
152	 * Bug related to requirement of same child and parent addresses for first range is fixed
153	 * in U-Boot version 2022.04 by following commit:
154	 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
155	 */
156	#address-cells = <3>;
157	#size-cells = <2>;
158	ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
159		  0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */
160
161	/* enabled by U-Boot if PCIe module is present */
162	status = "disabled";
163};
164
165&uart0 {
166	status = "okay";
167};
168
169&eth0 {
170	pinctrl-names = "default";
171	pinctrl-0 = <&rgmii_pins>;
172	phy-mode = "rgmii-id";
173	phy-handle = <&phy1>;
174	status = "okay";
175};
176
177&eth1 {
178	phy-mode = "2500base-x";
179	managed = "in-band-status";
180	phys = <&comphy0 1>;
181};
182
183&sdhci0 {
184	wp-inverted;
185	bus-width = <4>;
186	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
187	vqmmc-supply = <&vsdc_reg>;
188	marvell,pad-type = "sd";
189	status = "okay";
190};
191
192&sdhci1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&sdio_pins>;
195	non-removable;
196	bus-width = <4>;
197	marvell,pad-type = "sd";
198	vqmmc-supply = <&vsdio_reg>;
199	mmc-pwrseq = <&sdhci1_pwrseq>;
200	/* forbid SDR104 for FCC purposes */
201	sdhci-caps-mask = <0x2 0x0>;
202	status = "okay";
203};
204
205&spi0 {
206	status = "okay";
207	pinctrl-names = "default";
208	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
209	assigned-clocks = <&nb_periph_clk 7>;
210	assigned-clock-parents = <&tbg 1>;
211	assigned-clock-rates = <20000000>;
212
213	spi-flash@0 {
214		#address-cells = <1>;
215		#size-cells = <1>;
216		compatible = "jedec,spi-nor";
217		reg = <0>;
218		spi-max-frequency = <20000000>;
219
220		partitions {
221			compatible = "fixed-partitions";
222			#address-cells = <1>;
223			#size-cells = <1>;
224
225			partition@0 {
226				label = "secure-firmware";
227				reg = <0x0 0x20000>;
228			};
229
230			partition@20000 {
231				label = "a53-firmware";
232				reg = <0x20000 0x160000>;
233			};
234
235			partition@180000 {
236				label = "u-boot-env";
237				reg = <0x180000 0x10000>;
238			};
239
240			partition@190000 {
241				label = "Rescue system";
242				reg = <0x190000 0x660000>;
243			};
244
245			partition@7f0000 {
246				label = "dtb";
247				reg = <0x7f0000 0x10000>;
248			};
249		};
250	};
251
252	moxtet: moxtet@1 {
253		#address-cells = <1>;
254		#size-cells = <0>;
255		compatible = "cznic,moxtet";
256		reg = <1>;
257		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
258		spi-max-frequency = <10000000>;
259		spi-cpol;
260		spi-cpha;
261		interrupt-controller;
262		#interrupt-cells = <1>;
263		interrupt-parent = <&gpiosb>;
264		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
265		status = "okay";
266
267		moxtet_sfp: gpio@0 {
268			compatible = "cznic,moxtet-gpio";
269			gpio-controller;
270			#gpio-cells = <2>;
271			reg = <0>;
272			status = "disabled";
273		};
274	};
275};
276
277&usb2 {
278	status = "okay";
279};
280
281&comphy2 {
282	connector {
283		compatible = "usb-a-connector";
284		phy-supply = <&exp_usb3_vbus>;
285	};
286};
287
288&usb3 {
289	status = "okay";
290	phys = <&comphy2 0>;
291};
292
293&mdio {
294	pinctrl-names = "default";
295	pinctrl-0 = <&smi_pins>;
296	status = "okay";
297
298	phy1: ethernet-phy@1 {
299		reg = <1>;
300	};
301
302	/* switch nodes are enabled by U-Boot if modules are present */
303	switch0@10 {
304		compatible = "marvell,mv88e6190";
305		reg = <0x10 0>;
306		dsa,member = <0 0>;
307		interrupt-parent = <&moxtet>;
308		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
309		status = "disabled";
310
311		mdio {
312			#address-cells = <1>;
313			#size-cells = <0>;
314
315			switch0phy1: switch0phy1@1 {
316				reg = <0x1>;
317			};
318
319			switch0phy2: switch0phy2@2 {
320				reg = <0x2>;
321			};
322
323			switch0phy3: switch0phy3@3 {
324				reg = <0x3>;
325			};
326
327			switch0phy4: switch0phy4@4 {
328				reg = <0x4>;
329			};
330
331			switch0phy5: switch0phy5@5 {
332				reg = <0x5>;
333			};
334
335			switch0phy6: switch0phy6@6 {
336				reg = <0x6>;
337			};
338
339			switch0phy7: switch0phy7@7 {
340				reg = <0x7>;
341			};
342
343			switch0phy8: switch0phy8@8 {
344				reg = <0x8>;
345			};
346		};
347
348		ports {
349			#address-cells = <1>;
350			#size-cells = <0>;
351
352			port@1 {
353				reg = <0x1>;
354				label = "lan1";
355				phy-handle = <&switch0phy1>;
356			};
357
358			port@2 {
359				reg = <0x2>;
360				label = "lan2";
361				phy-handle = <&switch0phy2>;
362			};
363
364			port@3 {
365				reg = <0x3>;
366				label = "lan3";
367				phy-handle = <&switch0phy3>;
368			};
369
370			port@4 {
371				reg = <0x4>;
372				label = "lan4";
373				phy-handle = <&switch0phy4>;
374			};
375
376			port@5 {
377				reg = <0x5>;
378				label = "lan5";
379				phy-handle = <&switch0phy5>;
380			};
381
382			port@6 {
383				reg = <0x6>;
384				label = "lan6";
385				phy-handle = <&switch0phy6>;
386			};
387
388			port@7 {
389				reg = <0x7>;
390				label = "lan7";
391				phy-handle = <&switch0phy7>;
392			};
393
394			port@8 {
395				reg = <0x8>;
396				label = "lan8";
397				phy-handle = <&switch0phy8>;
398			};
399
400			port@9 {
401				reg = <0x9>;
402				label = "cpu";
403				ethernet = <&eth1>;
404				phy-mode = "2500base-x";
405				managed = "in-band-status";
406			};
407
408			switch0port10: port@a {
409				reg = <0xa>;
410				label = "dsa";
411				phy-mode = "2500base-x";
412				managed = "in-band-status";
413				link = <&switch1port9 &switch2port9>;
414				status = "disabled";
415			};
416
417			port-sfp@a {
418				reg = <0xa>;
419				label = "sfp";
420				sfp = <&sfp>;
421				phy-mode = "sgmii";
422				managed = "in-band-status";
423				status = "disabled";
424			};
425		};
426	};
427
428	switch0@2 {
429		compatible = "marvell,mv88e6085";
430		reg = <0x2 0>;
431		dsa,member = <0 0>;
432		interrupt-parent = <&moxtet>;
433		interrupts = <MOXTET_IRQ_TOPAZ>;
434		status = "disabled";
435
436		mdio {
437			#address-cells = <1>;
438			#size-cells = <0>;
439
440			switch0phy1_topaz: switch0phy1@11 {
441				reg = <0x11>;
442			};
443
444			switch0phy2_topaz: switch0phy2@12 {
445				reg = <0x12>;
446			};
447
448			switch0phy3_topaz: switch0phy3@13 {
449				reg = <0x13>;
450			};
451
452			switch0phy4_topaz: switch0phy4@14 {
453				reg = <0x14>;
454			};
455		};
456
457		ports {
458			#address-cells = <1>;
459			#size-cells = <0>;
460
461			port@1 {
462				reg = <0x1>;
463				label = "lan1";
464				phy-handle = <&switch0phy1_topaz>;
465			};
466
467			port@2 {
468				reg = <0x2>;
469				label = "lan2";
470				phy-handle = <&switch0phy2_topaz>;
471			};
472
473			port@3 {
474				reg = <0x3>;
475				label = "lan3";
476				phy-handle = <&switch0phy3_topaz>;
477			};
478
479			port@4 {
480				reg = <0x4>;
481				label = "lan4";
482				phy-handle = <&switch0phy4_topaz>;
483			};
484
485			port@5 {
486				reg = <0x5>;
487				label = "cpu";
488				phy-mode = "2500base-x";
489				managed = "in-band-status";
490				ethernet = <&eth1>;
491			};
492		};
493	};
494
495	switch1@11 {
496		compatible = "marvell,mv88e6190";
497		reg = <0x11 0>;
498		dsa,member = <0 1>;
499		interrupt-parent = <&moxtet>;
500		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
501		status = "disabled";
502
503		mdio {
504			#address-cells = <1>;
505			#size-cells = <0>;
506
507			switch1phy1: switch1phy1@1 {
508				reg = <0x1>;
509			};
510
511			switch1phy2: switch1phy2@2 {
512				reg = <0x2>;
513			};
514
515			switch1phy3: switch1phy3@3 {
516				reg = <0x3>;
517			};
518
519			switch1phy4: switch1phy4@4 {
520				reg = <0x4>;
521			};
522
523			switch1phy5: switch1phy5@5 {
524				reg = <0x5>;
525			};
526
527			switch1phy6: switch1phy6@6 {
528				reg = <0x6>;
529			};
530
531			switch1phy7: switch1phy7@7 {
532				reg = <0x7>;
533			};
534
535			switch1phy8: switch1phy8@8 {
536				reg = <0x8>;
537			};
538		};
539
540		ports {
541			#address-cells = <1>;
542			#size-cells = <0>;
543
544			port@1 {
545				reg = <0x1>;
546				label = "lan9";
547				phy-handle = <&switch1phy1>;
548			};
549
550			port@2 {
551				reg = <0x2>;
552				label = "lan10";
553				phy-handle = <&switch1phy2>;
554			};
555
556			port@3 {
557				reg = <0x3>;
558				label = "lan11";
559				phy-handle = <&switch1phy3>;
560			};
561
562			port@4 {
563				reg = <0x4>;
564				label = "lan12";
565				phy-handle = <&switch1phy4>;
566			};
567
568			port@5 {
569				reg = <0x5>;
570				label = "lan13";
571				phy-handle = <&switch1phy5>;
572			};
573
574			port@6 {
575				reg = <0x6>;
576				label = "lan14";
577				phy-handle = <&switch1phy6>;
578			};
579
580			port@7 {
581				reg = <0x7>;
582				label = "lan15";
583				phy-handle = <&switch1phy7>;
584			};
585
586			port@8 {
587				reg = <0x8>;
588				label = "lan16";
589				phy-handle = <&switch1phy8>;
590			};
591
592			switch1port9: port@9 {
593				reg = <0x9>;
594				label = "dsa";
595				phy-mode = "2500base-x";
596				managed = "in-band-status";
597				link = <&switch0port10>;
598			};
599
600			switch1port10: port@a {
601				reg = <0xa>;
602				label = "dsa";
603				phy-mode = "2500base-x";
604				managed = "in-band-status";
605				link = <&switch2port9>;
606				status = "disabled";
607			};
608
609			port-sfp@a {
610				reg = <0xa>;
611				label = "sfp";
612				sfp = <&sfp>;
613				phy-mode = "sgmii";
614				managed = "in-band-status";
615				status = "disabled";
616			};
617		};
618	};
619
620	switch1@2 {
621		compatible = "marvell,mv88e6085";
622		reg = <0x2 0>;
623		dsa,member = <0 1>;
624		interrupt-parent = <&moxtet>;
625		interrupts = <MOXTET_IRQ_TOPAZ>;
626		status = "disabled";
627
628		mdio {
629			#address-cells = <1>;
630			#size-cells = <0>;
631
632			switch1phy1_topaz: switch1phy1@11 {
633				reg = <0x11>;
634			};
635
636			switch1phy2_topaz: switch1phy2@12 {
637				reg = <0x12>;
638			};
639
640			switch1phy3_topaz: switch1phy3@13 {
641				reg = <0x13>;
642			};
643
644			switch1phy4_topaz: switch1phy4@14 {
645				reg = <0x14>;
646			};
647		};
648
649		ports {
650			#address-cells = <1>;
651			#size-cells = <0>;
652
653			port@1 {
654				reg = <0x1>;
655				label = "lan9";
656				phy-handle = <&switch1phy1_topaz>;
657			};
658
659			port@2 {
660				reg = <0x2>;
661				label = "lan10";
662				phy-handle = <&switch1phy2_topaz>;
663			};
664
665			port@3 {
666				reg = <0x3>;
667				label = "lan11";
668				phy-handle = <&switch1phy3_topaz>;
669			};
670
671			port@4 {
672				reg = <0x4>;
673				label = "lan12";
674				phy-handle = <&switch1phy4_topaz>;
675			};
676
677			port@5 {
678				reg = <0x5>;
679				label = "dsa";
680				phy-mode = "2500base-x";
681				managed = "in-band-status";
682				link = <&switch0port10>;
683			};
684		};
685	};
686
687	switch2@12 {
688		compatible = "marvell,mv88e6190";
689		reg = <0x12 0>;
690		dsa,member = <0 2>;
691		interrupt-parent = <&moxtet>;
692		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
693		status = "disabled";
694
695		mdio {
696			#address-cells = <1>;
697			#size-cells = <0>;
698
699			switch2phy1: switch2phy1@1 {
700				reg = <0x1>;
701			};
702
703			switch2phy2: switch2phy2@2 {
704				reg = <0x2>;
705			};
706
707			switch2phy3: switch2phy3@3 {
708				reg = <0x3>;
709			};
710
711			switch2phy4: switch2phy4@4 {
712				reg = <0x4>;
713			};
714
715			switch2phy5: switch2phy5@5 {
716				reg = <0x5>;
717			};
718
719			switch2phy6: switch2phy6@6 {
720				reg = <0x6>;
721			};
722
723			switch2phy7: switch2phy7@7 {
724				reg = <0x7>;
725			};
726
727			switch2phy8: switch2phy8@8 {
728				reg = <0x8>;
729			};
730		};
731
732		ports {
733			#address-cells = <1>;
734			#size-cells = <0>;
735
736			port@1 {
737				reg = <0x1>;
738				label = "lan17";
739				phy-handle = <&switch2phy1>;
740			};
741
742			port@2 {
743				reg = <0x2>;
744				label = "lan18";
745				phy-handle = <&switch2phy2>;
746			};
747
748			port@3 {
749				reg = <0x3>;
750				label = "lan19";
751				phy-handle = <&switch2phy3>;
752			};
753
754			port@4 {
755				reg = <0x4>;
756				label = "lan20";
757				phy-handle = <&switch2phy4>;
758			};
759
760			port@5 {
761				reg = <0x5>;
762				label = "lan21";
763				phy-handle = <&switch2phy5>;
764			};
765
766			port@6 {
767				reg = <0x6>;
768				label = "lan22";
769				phy-handle = <&switch2phy6>;
770			};
771
772			port@7 {
773				reg = <0x7>;
774				label = "lan23";
775				phy-handle = <&switch2phy7>;
776			};
777
778			port@8 {
779				reg = <0x8>;
780				label = "lan24";
781				phy-handle = <&switch2phy8>;
782			};
783
784			switch2port9: port@9 {
785				reg = <0x9>;
786				label = "dsa";
787				phy-mode = "2500base-x";
788				managed = "in-band-status";
789				link = <&switch1port10 &switch0port10>;
790			};
791
792			port-sfp@a {
793				reg = <0xa>;
794				label = "sfp";
795				sfp = <&sfp>;
796				phy-mode = "sgmii";
797				managed = "in-band-status";
798				status = "disabled";
799			};
800		};
801	};
802
803	switch2@2 {
804		compatible = "marvell,mv88e6085";
805		reg = <0x2 0>;
806		dsa,member = <0 2>;
807		interrupt-parent = <&moxtet>;
808		interrupts = <MOXTET_IRQ_TOPAZ>;
809		status = "disabled";
810
811		mdio {
812			#address-cells = <1>;
813			#size-cells = <0>;
814
815			switch2phy1_topaz: switch2phy1@11 {
816				reg = <0x11>;
817			};
818
819			switch2phy2_topaz: switch2phy2@12 {
820				reg = <0x12>;
821			};
822
823			switch2phy3_topaz: switch2phy3@13 {
824				reg = <0x13>;
825			};
826
827			switch2phy4_topaz: switch2phy4@14 {
828				reg = <0x14>;
829			};
830		};
831
832		ports {
833			#address-cells = <1>;
834			#size-cells = <0>;
835
836			port@1 {
837				reg = <0x1>;
838				label = "lan17";
839				phy-handle = <&switch2phy1_topaz>;
840			};
841
842			port@2 {
843				reg = <0x2>;
844				label = "lan18";
845				phy-handle = <&switch2phy2_topaz>;
846			};
847
848			port@3 {
849				reg = <0x3>;
850				label = "lan19";
851				phy-handle = <&switch2phy3_topaz>;
852			};
853
854			port@4 {
855				reg = <0x4>;
856				label = "lan20";
857				phy-handle = <&switch2phy4_topaz>;
858			};
859
860			port@5 {
861				reg = <0x5>;
862				label = "dsa";
863				phy-mode = "2500base-x";
864				managed = "in-band-status";
865				link = <&switch1port10 &switch0port10>;
866			};
867		};
868	};
869};
870