1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22		mmc0 = &sdhci0;
23		mmc1 = &sdhci1;
24	};
25
26	chosen {
27		stdout-path = "serial0:115200n8";
28	};
29
30	memory@0 {
31		device_type = "memory";
32		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
33	};
34
35	leds {
36		compatible = "gpio-leds";
37		red {
38			label = "mox:red:activity";
39			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
40			linux,default-trigger = "default-on";
41		};
42	};
43
44	gpio-keys {
45		compatible = "gpio-keys";
46
47		reset {
48			label = "reset";
49			linux,code = <KEY_RESTART>;
50			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
51			debounce-interval = <60>;
52		};
53	};
54
55	exp_usb3_vbus: usb3-vbus {
56		compatible = "regulator-fixed";
57		regulator-name = "usb3-vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		enable-active-high;
61		regulator-always-on;
62		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
63	};
64
65	vsdc_reg: vsdc-reg {
66		compatible = "regulator-gpio";
67		regulator-name = "vsdc";
68		regulator-min-microvolt = <1800000>;
69		regulator-max-microvolt = <3300000>;
70		regulator-boot-on;
71
72		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
73		gpios-states = <0>;
74		states = <1800000 0x1
75			  3300000 0x0>;
76		enable-active-high;
77	};
78
79	vsdio_reg: vsdio-reg {
80		compatible = "regulator-gpio";
81		regulator-name = "vsdio";
82		regulator-min-microvolt = <1800000>;
83		regulator-max-microvolt = <3300000>;
84		regulator-boot-on;
85
86		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
87		gpios-states = <0>;
88		states = <1800000 0x1
89			  3300000 0x0>;
90		enable-active-high;
91	};
92
93	sdhci1_pwrseq: sdhci1-pwrseq {
94		compatible = "mmc-pwrseq-simple";
95		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
96		status = "okay";
97	};
98
99	sfp: sfp {
100		compatible = "sff,sfp";
101		i2c-bus = <&i2c0>;
102		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
103		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
104		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
105		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
106		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
107
108		/* enabled by U-Boot if SFP module is present */
109		status = "disabled";
110	};
111
112	firmware {
113		armada-3700-rwtm {
114			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
115		};
116	};
117};
118
119&i2c0 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&i2c1_pins>;
122	clock-frequency = <100000>;
123	status = "okay";
124
125	rtc@6f {
126		compatible = "microchip,mcp7940x";
127		reg = <0x6f>;
128	};
129};
130
131&pcie0 {
132	pinctrl-names = "default";
133	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
134	status = "okay";
135	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
136
137	/* enabled by U-Boot if PCIe module is present */
138	status = "disabled";
139};
140
141&uart0 {
142	status = "okay";
143};
144
145&eth0 {
146	pinctrl-names = "default";
147	pinctrl-0 = <&rgmii_pins>;
148	phy-mode = "rgmii-id";
149	phy-handle = <&phy1>;
150	status = "okay";
151};
152
153&eth1 {
154	phy-mode = "2500base-x";
155	managed = "in-band-status";
156	phys = <&comphy0 1>;
157};
158
159&sdhci0 {
160	wp-inverted;
161	bus-width = <4>;
162	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
163	vqmmc-supply = <&vsdc_reg>;
164	marvell,pad-type = "sd";
165	status = "okay";
166};
167
168&sdhci1 {
169	pinctrl-names = "default";
170	pinctrl-0 = <&sdio_pins>;
171	non-removable;
172	bus-width = <4>;
173	marvell,pad-type = "sd";
174	vqmmc-supply = <&vsdio_reg>;
175	mmc-pwrseq = <&sdhci1_pwrseq>;
176	/* forbid SDR104 for FCC purposes */
177	sdhci-caps-mask = <0x2 0x0>;
178	status = "okay";
179};
180
181&spi0 {
182	status = "okay";
183	pinctrl-names = "default";
184	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
185	assigned-clocks = <&nb_periph_clk 7>;
186	assigned-clock-parents = <&tbg 1>;
187	assigned-clock-rates = <20000000>;
188
189	spi-flash@0 {
190		#address-cells = <1>;
191		#size-cells = <1>;
192		compatible = "jedec,spi-nor";
193		reg = <0>;
194		spi-max-frequency = <20000000>;
195
196		partitions {
197			compatible = "fixed-partitions";
198			#address-cells = <1>;
199			#size-cells = <1>;
200
201			partition@0 {
202				label = "secure-firmware";
203				reg = <0x0 0x20000>;
204			};
205
206			partition@20000 {
207				label = "a53-firmware";
208				reg = <0x20000 0x160000>;
209			};
210
211			partition@180000 {
212				label = "u-boot-env";
213				reg = <0x180000 0x10000>;
214			};
215
216			partition@190000 {
217				label = "Rescue system";
218				reg = <0x190000 0x660000>;
219			};
220
221			partition@7f0000 {
222				label = "dtb";
223				reg = <0x7f0000 0x10000>;
224			};
225		};
226	};
227
228	moxtet: moxtet@1 {
229		#address-cells = <1>;
230		#size-cells = <0>;
231		compatible = "cznic,moxtet";
232		reg = <1>;
233		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
234		spi-max-frequency = <10000000>;
235		spi-cpol;
236		spi-cpha;
237		interrupt-controller;
238		#interrupt-cells = <1>;
239		interrupt-parent = <&gpiosb>;
240		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
241		status = "okay";
242
243		moxtet_sfp: gpio@0 {
244			compatible = "cznic,moxtet-gpio";
245			gpio-controller;
246			#gpio-cells = <2>;
247			reg = <0>;
248			status = "disabled";
249		};
250	};
251};
252
253&usb2 {
254	status = "okay";
255};
256
257&comphy2 {
258	connector {
259		compatible = "usb-a-connector";
260		phy-supply = <&exp_usb3_vbus>;
261	};
262};
263
264&usb3 {
265	status = "okay";
266	phys = <&comphy2 0>;
267};
268
269&mdio {
270	pinctrl-names = "default";
271	pinctrl-0 = <&smi_pins>;
272	status = "okay";
273
274	phy1: ethernet-phy@1 {
275		reg = <1>;
276	};
277
278	/* switch nodes are enabled by U-Boot if modules are present */
279	switch0@10 {
280		compatible = "marvell,mv88e6190";
281		reg = <0x10 0>;
282		dsa,member = <0 0>;
283		interrupt-parent = <&moxtet>;
284		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
285		status = "disabled";
286
287		mdio {
288			#address-cells = <1>;
289			#size-cells = <0>;
290
291			switch0phy1: switch0phy1@1 {
292				reg = <0x1>;
293			};
294
295			switch0phy2: switch0phy2@2 {
296				reg = <0x2>;
297			};
298
299			switch0phy3: switch0phy3@3 {
300				reg = <0x3>;
301			};
302
303			switch0phy4: switch0phy4@4 {
304				reg = <0x4>;
305			};
306
307			switch0phy5: switch0phy5@5 {
308				reg = <0x5>;
309			};
310
311			switch0phy6: switch0phy6@6 {
312				reg = <0x6>;
313			};
314
315			switch0phy7: switch0phy7@7 {
316				reg = <0x7>;
317			};
318
319			switch0phy8: switch0phy8@8 {
320				reg = <0x8>;
321			};
322		};
323
324		ports {
325			#address-cells = <1>;
326			#size-cells = <0>;
327
328			port@1 {
329				reg = <0x1>;
330				label = "lan1";
331				phy-handle = <&switch0phy1>;
332			};
333
334			port@2 {
335				reg = <0x2>;
336				label = "lan2";
337				phy-handle = <&switch0phy2>;
338			};
339
340			port@3 {
341				reg = <0x3>;
342				label = "lan3";
343				phy-handle = <&switch0phy3>;
344			};
345
346			port@4 {
347				reg = <0x4>;
348				label = "lan4";
349				phy-handle = <&switch0phy4>;
350			};
351
352			port@5 {
353				reg = <0x5>;
354				label = "lan5";
355				phy-handle = <&switch0phy5>;
356			};
357
358			port@6 {
359				reg = <0x6>;
360				label = "lan6";
361				phy-handle = <&switch0phy6>;
362			};
363
364			port@7 {
365				reg = <0x7>;
366				label = "lan7";
367				phy-handle = <&switch0phy7>;
368			};
369
370			port@8 {
371				reg = <0x8>;
372				label = "lan8";
373				phy-handle = <&switch0phy8>;
374			};
375
376			port@9 {
377				reg = <0x9>;
378				label = "cpu";
379				ethernet = <&eth1>;
380				phy-mode = "2500base-x";
381				managed = "in-band-status";
382			};
383
384			switch0port10: port@a {
385				reg = <0xa>;
386				label = "dsa";
387				phy-mode = "2500base-x";
388				managed = "in-band-status";
389				link = <&switch1port9 &switch2port9>;
390				status = "disabled";
391			};
392
393			port-sfp@a {
394				reg = <0xa>;
395				label = "sfp";
396				sfp = <&sfp>;
397				phy-mode = "sgmii";
398				managed = "in-band-status";
399				status = "disabled";
400			};
401		};
402	};
403
404	switch0@2 {
405		compatible = "marvell,mv88e6085";
406		reg = <0x2 0>;
407		dsa,member = <0 0>;
408		interrupt-parent = <&moxtet>;
409		interrupts = <MOXTET_IRQ_TOPAZ>;
410		status = "disabled";
411
412		mdio {
413			#address-cells = <1>;
414			#size-cells = <0>;
415
416			switch0phy1_topaz: switch0phy1@11 {
417				reg = <0x11>;
418			};
419
420			switch0phy2_topaz: switch0phy2@12 {
421				reg = <0x12>;
422			};
423
424			switch0phy3_topaz: switch0phy3@13 {
425				reg = <0x13>;
426			};
427
428			switch0phy4_topaz: switch0phy4@14 {
429				reg = <0x14>;
430			};
431		};
432
433		ports {
434			#address-cells = <1>;
435			#size-cells = <0>;
436
437			port@1 {
438				reg = <0x1>;
439				label = "lan1";
440				phy-handle = <&switch0phy1_topaz>;
441			};
442
443			port@2 {
444				reg = <0x2>;
445				label = "lan2";
446				phy-handle = <&switch0phy2_topaz>;
447			};
448
449			port@3 {
450				reg = <0x3>;
451				label = "lan3";
452				phy-handle = <&switch0phy3_topaz>;
453			};
454
455			port@4 {
456				reg = <0x4>;
457				label = "lan4";
458				phy-handle = <&switch0phy4_topaz>;
459			};
460
461			port@5 {
462				reg = <0x5>;
463				label = "cpu";
464				phy-mode = "2500base-x";
465				managed = "in-band-status";
466				ethernet = <&eth1>;
467			};
468		};
469	};
470
471	switch1@11 {
472		compatible = "marvell,mv88e6190";
473		reg = <0x11 0>;
474		dsa,member = <0 1>;
475		interrupt-parent = <&moxtet>;
476		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
477		status = "disabled";
478
479		mdio {
480			#address-cells = <1>;
481			#size-cells = <0>;
482
483			switch1phy1: switch1phy1@1 {
484				reg = <0x1>;
485			};
486
487			switch1phy2: switch1phy2@2 {
488				reg = <0x2>;
489			};
490
491			switch1phy3: switch1phy3@3 {
492				reg = <0x3>;
493			};
494
495			switch1phy4: switch1phy4@4 {
496				reg = <0x4>;
497			};
498
499			switch1phy5: switch1phy5@5 {
500				reg = <0x5>;
501			};
502
503			switch1phy6: switch1phy6@6 {
504				reg = <0x6>;
505			};
506
507			switch1phy7: switch1phy7@7 {
508				reg = <0x7>;
509			};
510
511			switch1phy8: switch1phy8@8 {
512				reg = <0x8>;
513			};
514		};
515
516		ports {
517			#address-cells = <1>;
518			#size-cells = <0>;
519
520			port@1 {
521				reg = <0x1>;
522				label = "lan9";
523				phy-handle = <&switch1phy1>;
524			};
525
526			port@2 {
527				reg = <0x2>;
528				label = "lan10";
529				phy-handle = <&switch1phy2>;
530			};
531
532			port@3 {
533				reg = <0x3>;
534				label = "lan11";
535				phy-handle = <&switch1phy3>;
536			};
537
538			port@4 {
539				reg = <0x4>;
540				label = "lan12";
541				phy-handle = <&switch1phy4>;
542			};
543
544			port@5 {
545				reg = <0x5>;
546				label = "lan13";
547				phy-handle = <&switch1phy5>;
548			};
549
550			port@6 {
551				reg = <0x6>;
552				label = "lan14";
553				phy-handle = <&switch1phy6>;
554			};
555
556			port@7 {
557				reg = <0x7>;
558				label = "lan15";
559				phy-handle = <&switch1phy7>;
560			};
561
562			port@8 {
563				reg = <0x8>;
564				label = "lan16";
565				phy-handle = <&switch1phy8>;
566			};
567
568			switch1port9: port@9 {
569				reg = <0x9>;
570				label = "dsa";
571				phy-mode = "2500base-x";
572				managed = "in-band-status";
573				link = <&switch0port10>;
574			};
575
576			switch1port10: port@a {
577				reg = <0xa>;
578				label = "dsa";
579				phy-mode = "2500base-x";
580				managed = "in-band-status";
581				link = <&switch2port9>;
582				status = "disabled";
583			};
584
585			port-sfp@a {
586				reg = <0xa>;
587				label = "sfp";
588				sfp = <&sfp>;
589				phy-mode = "sgmii";
590				managed = "in-band-status";
591				status = "disabled";
592			};
593		};
594	};
595
596	switch1@2 {
597		compatible = "marvell,mv88e6085";
598		reg = <0x2 0>;
599		dsa,member = <0 1>;
600		interrupt-parent = <&moxtet>;
601		interrupts = <MOXTET_IRQ_TOPAZ>;
602		status = "disabled";
603
604		mdio {
605			#address-cells = <1>;
606			#size-cells = <0>;
607
608			switch1phy1_topaz: switch1phy1@11 {
609				reg = <0x11>;
610			};
611
612			switch1phy2_topaz: switch1phy2@12 {
613				reg = <0x12>;
614			};
615
616			switch1phy3_topaz: switch1phy3@13 {
617				reg = <0x13>;
618			};
619
620			switch1phy4_topaz: switch1phy4@14 {
621				reg = <0x14>;
622			};
623		};
624
625		ports {
626			#address-cells = <1>;
627			#size-cells = <0>;
628
629			port@1 {
630				reg = <0x1>;
631				label = "lan9";
632				phy-handle = <&switch1phy1_topaz>;
633			};
634
635			port@2 {
636				reg = <0x2>;
637				label = "lan10";
638				phy-handle = <&switch1phy2_topaz>;
639			};
640
641			port@3 {
642				reg = <0x3>;
643				label = "lan11";
644				phy-handle = <&switch1phy3_topaz>;
645			};
646
647			port@4 {
648				reg = <0x4>;
649				label = "lan12";
650				phy-handle = <&switch1phy4_topaz>;
651			};
652
653			port@5 {
654				reg = <0x5>;
655				label = "dsa";
656				phy-mode = "2500base-x";
657				managed = "in-band-status";
658				link = <&switch0port10>;
659			};
660		};
661	};
662
663	switch2@12 {
664		compatible = "marvell,mv88e6190";
665		reg = <0x12 0>;
666		dsa,member = <0 2>;
667		interrupt-parent = <&moxtet>;
668		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
669		status = "disabled";
670
671		mdio {
672			#address-cells = <1>;
673			#size-cells = <0>;
674
675			switch2phy1: switch2phy1@1 {
676				reg = <0x1>;
677			};
678
679			switch2phy2: switch2phy2@2 {
680				reg = <0x2>;
681			};
682
683			switch2phy3: switch2phy3@3 {
684				reg = <0x3>;
685			};
686
687			switch2phy4: switch2phy4@4 {
688				reg = <0x4>;
689			};
690
691			switch2phy5: switch2phy5@5 {
692				reg = <0x5>;
693			};
694
695			switch2phy6: switch2phy6@6 {
696				reg = <0x6>;
697			};
698
699			switch2phy7: switch2phy7@7 {
700				reg = <0x7>;
701			};
702
703			switch2phy8: switch2phy8@8 {
704				reg = <0x8>;
705			};
706		};
707
708		ports {
709			#address-cells = <1>;
710			#size-cells = <0>;
711
712			port@1 {
713				reg = <0x1>;
714				label = "lan17";
715				phy-handle = <&switch2phy1>;
716			};
717
718			port@2 {
719				reg = <0x2>;
720				label = "lan18";
721				phy-handle = <&switch2phy2>;
722			};
723
724			port@3 {
725				reg = <0x3>;
726				label = "lan19";
727				phy-handle = <&switch2phy3>;
728			};
729
730			port@4 {
731				reg = <0x4>;
732				label = "lan20";
733				phy-handle = <&switch2phy4>;
734			};
735
736			port@5 {
737				reg = <0x5>;
738				label = "lan21";
739				phy-handle = <&switch2phy5>;
740			};
741
742			port@6 {
743				reg = <0x6>;
744				label = "lan22";
745				phy-handle = <&switch2phy6>;
746			};
747
748			port@7 {
749				reg = <0x7>;
750				label = "lan23";
751				phy-handle = <&switch2phy7>;
752			};
753
754			port@8 {
755				reg = <0x8>;
756				label = "lan24";
757				phy-handle = <&switch2phy8>;
758			};
759
760			switch2port9: port@9 {
761				reg = <0x9>;
762				label = "dsa";
763				phy-mode = "2500base-x";
764				managed = "in-band-status";
765				link = <&switch1port10 &switch0port10>;
766			};
767
768			port-sfp@a {
769				reg = <0xa>;
770				label = "sfp";
771				sfp = <&sfp>;
772				phy-mode = "sgmii";
773				managed = "in-band-status";
774				status = "disabled";
775			};
776		};
777	};
778
779	switch2@2 {
780		compatible = "marvell,mv88e6085";
781		reg = <0x2 0>;
782		dsa,member = <0 2>;
783		interrupt-parent = <&moxtet>;
784		interrupts = <MOXTET_IRQ_TOPAZ>;
785		status = "disabled";
786
787		mdio {
788			#address-cells = <1>;
789			#size-cells = <0>;
790
791			switch2phy1_topaz: switch2phy1@11 {
792				reg = <0x11>;
793			};
794
795			switch2phy2_topaz: switch2phy2@12 {
796				reg = <0x12>;
797			};
798
799			switch2phy3_topaz: switch2phy3@13 {
800				reg = <0x13>;
801			};
802
803			switch2phy4_topaz: switch2phy4@14 {
804				reg = <0x14>;
805			};
806		};
807
808		ports {
809			#address-cells = <1>;
810			#size-cells = <0>;
811
812			port@1 {
813				reg = <0x1>;
814				label = "lan17";
815				phy-handle = <&switch2phy1_topaz>;
816			};
817
818			port@2 {
819				reg = <0x2>;
820				label = "lan18";
821				phy-handle = <&switch2phy2_topaz>;
822			};
823
824			port@3 {
825				reg = <0x3>;
826				label = "lan19";
827				phy-handle = <&switch2phy3_topaz>;
828			};
829
830			port@4 {
831				reg = <0x4>;
832				label = "lan20";
833				phy-handle = <&switch2phy4_topaz>;
834			};
835
836			port@5 {
837				reg = <0x5>;
838				label = "dsa";
839				phy-mode = "2500base-x";
840				managed = "in-band-status";
841				link = <&switch1port10 &switch0port10>;
842			};
843		};
844	};
845};
846