1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for CZ.NIC Turris Mox Board 4 * 2019 by Marek Behun <marek.behun@nic.cz> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/bus/moxtet.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include "armada-372x.dtsi" 13 14/ { 15 model = "CZ.NIC Turris Mox Board"; 16 compatible = "cznic,turris-mox", "marvell,armada3720", 17 "marvell,armada3710"; 18 19 aliases { 20 spi0 = &spi0; 21 ethernet1 = ð1; 22 mmc0 = &sdhci0; 23 mmc1 = &sdhci1; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 memory@0 { 31 device_type = "memory"; 32 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 33 }; 34 35 leds { 36 compatible = "gpio-leds"; 37 red { 38 label = "mox:red:activity"; 39 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 40 linux,default-trigger = "default-on"; 41 }; 42 }; 43 44 gpio-keys { 45 compatible = "gpio-keys"; 46 47 reset { 48 label = "reset"; 49 linux,code = <KEY_RESTART>; 50 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 51 debounce-interval = <60>; 52 }; 53 }; 54 55 exp_usb3_vbus: usb3-vbus { 56 compatible = "regulator-fixed"; 57 regulator-name = "usb3-vbus"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 enable-active-high; 61 regulator-always-on; 62 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 63 }; 64 65 vsdc_reg: vsdc-reg { 66 compatible = "regulator-gpio"; 67 regulator-name = "vsdc"; 68 regulator-min-microvolt = <1800000>; 69 regulator-max-microvolt = <3300000>; 70 regulator-boot-on; 71 72 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 73 gpios-states = <0>; 74 states = <1800000 0x1 75 3300000 0x0>; 76 enable-active-high; 77 }; 78 79 vsdio_reg: vsdio-reg { 80 compatible = "regulator-gpio"; 81 regulator-name = "vsdio"; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <3300000>; 84 regulator-boot-on; 85 86 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 87 gpios-states = <0>; 88 states = <1800000 0x1 89 3300000 0x0>; 90 enable-active-high; 91 }; 92 93 sdhci1_pwrseq: sdhci1-pwrseq { 94 compatible = "mmc-pwrseq-simple"; 95 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 96 status = "okay"; 97 }; 98 99 sfp: sfp { 100 compatible = "sff,sfp"; 101 i2c-bus = <&i2c0>; 102 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 103 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 104 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 105 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 106 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 107 108 /* enabled by U-Boot if SFP module is present */ 109 status = "disabled"; 110 }; 111 112 firmware { 113 armada-3700-rwtm { 114 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; 115 }; 116 }; 117}; 118 119&i2c0 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&i2c1_pins>; 122 clock-frequency = <100000>; 123 /delete-property/ mrvl,i2c-fast-mode; 124 status = "okay"; 125 126 rtc@6f { 127 compatible = "microchip,mcp7940x"; 128 reg = <0x6f>; 129 }; 130}; 131 132&pcie0 { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 135 status = "okay"; 136 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 137 /* 138 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property 139 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and 140 * 2 size cells and also expects that the second range starts at 16 MB offset. If these 141 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address 142 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window 143 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. 144 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in 145 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): 146 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 147 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf 148 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 149 */ 150 #address-cells = <3>; 151 #size-cells = <2>; 152 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ 153 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ 154 155 /* enabled by U-Boot if PCIe module is present */ 156 status = "disabled"; 157}; 158 159&uart0 { 160 status = "okay"; 161}; 162 163ð0 { 164 pinctrl-names = "default"; 165 pinctrl-0 = <&rgmii_pins>; 166 phy-mode = "rgmii-id"; 167 phy-handle = <&phy1>; 168 status = "okay"; 169}; 170 171ð1 { 172 phy-mode = "2500base-x"; 173 managed = "in-band-status"; 174 phys = <&comphy0 1>; 175}; 176 177&sdhci0 { 178 wp-inverted; 179 bus-width = <4>; 180 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 181 vqmmc-supply = <&vsdc_reg>; 182 marvell,pad-type = "sd"; 183 status = "okay"; 184}; 185 186&sdhci1 { 187 pinctrl-names = "default"; 188 pinctrl-0 = <&sdio_pins>; 189 non-removable; 190 bus-width = <4>; 191 marvell,pad-type = "sd"; 192 vqmmc-supply = <&vsdio_reg>; 193 mmc-pwrseq = <&sdhci1_pwrseq>; 194 /* forbid SDR104 for FCC purposes */ 195 sdhci-caps-mask = <0x2 0x0>; 196 status = "okay"; 197}; 198 199&spi0 { 200 status = "okay"; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 203 assigned-clocks = <&nb_periph_clk 7>; 204 assigned-clock-parents = <&tbg 1>; 205 assigned-clock-rates = <20000000>; 206 207 spi-flash@0 { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 compatible = "jedec,spi-nor"; 211 reg = <0>; 212 spi-max-frequency = <20000000>; 213 214 partitions { 215 compatible = "fixed-partitions"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 219 partition@0 { 220 label = "secure-firmware"; 221 reg = <0x0 0x20000>; 222 }; 223 224 partition@20000 { 225 label = "a53-firmware"; 226 reg = <0x20000 0x160000>; 227 }; 228 229 partition@180000 { 230 label = "u-boot-env"; 231 reg = <0x180000 0x10000>; 232 }; 233 234 partition@190000 { 235 label = "Rescue system"; 236 reg = <0x190000 0x660000>; 237 }; 238 239 partition@7f0000 { 240 label = "dtb"; 241 reg = <0x7f0000 0x10000>; 242 }; 243 }; 244 }; 245 246 moxtet: moxtet@1 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 compatible = "cznic,moxtet"; 250 reg = <1>; 251 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 252 spi-max-frequency = <10000000>; 253 spi-cpol; 254 spi-cpha; 255 interrupt-controller; 256 #interrupt-cells = <1>; 257 interrupt-parent = <&gpiosb>; 258 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 259 status = "okay"; 260 261 moxtet_sfp: gpio@0 { 262 compatible = "cznic,moxtet-gpio"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 reg = <0>; 266 status = "disabled"; 267 }; 268 }; 269}; 270 271&usb2 { 272 status = "okay"; 273}; 274 275&comphy2 { 276 connector { 277 compatible = "usb-a-connector"; 278 phy-supply = <&exp_usb3_vbus>; 279 }; 280}; 281 282&usb3 { 283 status = "okay"; 284 phys = <&comphy2 0>; 285}; 286 287&mdio { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&smi_pins>; 290 status = "okay"; 291 292 phy1: ethernet-phy@1 { 293 reg = <1>; 294 }; 295 296 /* switch nodes are enabled by U-Boot if modules are present */ 297 switch0@10 { 298 compatible = "marvell,mv88e6190"; 299 reg = <0x10 0>; 300 dsa,member = <0 0>; 301 interrupt-parent = <&moxtet>; 302 interrupts = <MOXTET_IRQ_PERIDOT(0)>; 303 status = "disabled"; 304 305 mdio { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 309 switch0phy1: switch0phy1@1 { 310 reg = <0x1>; 311 }; 312 313 switch0phy2: switch0phy2@2 { 314 reg = <0x2>; 315 }; 316 317 switch0phy3: switch0phy3@3 { 318 reg = <0x3>; 319 }; 320 321 switch0phy4: switch0phy4@4 { 322 reg = <0x4>; 323 }; 324 325 switch0phy5: switch0phy5@5 { 326 reg = <0x5>; 327 }; 328 329 switch0phy6: switch0phy6@6 { 330 reg = <0x6>; 331 }; 332 333 switch0phy7: switch0phy7@7 { 334 reg = <0x7>; 335 }; 336 337 switch0phy8: switch0phy8@8 { 338 reg = <0x8>; 339 }; 340 }; 341 342 ports { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 port@1 { 347 reg = <0x1>; 348 label = "lan1"; 349 phy-handle = <&switch0phy1>; 350 }; 351 352 port@2 { 353 reg = <0x2>; 354 label = "lan2"; 355 phy-handle = <&switch0phy2>; 356 }; 357 358 port@3 { 359 reg = <0x3>; 360 label = "lan3"; 361 phy-handle = <&switch0phy3>; 362 }; 363 364 port@4 { 365 reg = <0x4>; 366 label = "lan4"; 367 phy-handle = <&switch0phy4>; 368 }; 369 370 port@5 { 371 reg = <0x5>; 372 label = "lan5"; 373 phy-handle = <&switch0phy5>; 374 }; 375 376 port@6 { 377 reg = <0x6>; 378 label = "lan6"; 379 phy-handle = <&switch0phy6>; 380 }; 381 382 port@7 { 383 reg = <0x7>; 384 label = "lan7"; 385 phy-handle = <&switch0phy7>; 386 }; 387 388 port@8 { 389 reg = <0x8>; 390 label = "lan8"; 391 phy-handle = <&switch0phy8>; 392 }; 393 394 port@9 { 395 reg = <0x9>; 396 label = "cpu"; 397 ethernet = <ð1>; 398 phy-mode = "2500base-x"; 399 managed = "in-band-status"; 400 }; 401 402 switch0port10: port@a { 403 reg = <0xa>; 404 label = "dsa"; 405 phy-mode = "2500base-x"; 406 managed = "in-band-status"; 407 link = <&switch1port9 &switch2port9>; 408 status = "disabled"; 409 }; 410 411 port-sfp@a { 412 reg = <0xa>; 413 label = "sfp"; 414 sfp = <&sfp>; 415 phy-mode = "sgmii"; 416 managed = "in-band-status"; 417 status = "disabled"; 418 }; 419 }; 420 }; 421 422 switch0@2 { 423 compatible = "marvell,mv88e6085"; 424 reg = <0x2 0>; 425 dsa,member = <0 0>; 426 interrupt-parent = <&moxtet>; 427 interrupts = <MOXTET_IRQ_TOPAZ>; 428 status = "disabled"; 429 430 mdio { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 switch0phy1_topaz: switch0phy1@11 { 435 reg = <0x11>; 436 }; 437 438 switch0phy2_topaz: switch0phy2@12 { 439 reg = <0x12>; 440 }; 441 442 switch0phy3_topaz: switch0phy3@13 { 443 reg = <0x13>; 444 }; 445 446 switch0phy4_topaz: switch0phy4@14 { 447 reg = <0x14>; 448 }; 449 }; 450 451 ports { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 455 port@1 { 456 reg = <0x1>; 457 label = "lan1"; 458 phy-handle = <&switch0phy1_topaz>; 459 }; 460 461 port@2 { 462 reg = <0x2>; 463 label = "lan2"; 464 phy-handle = <&switch0phy2_topaz>; 465 }; 466 467 port@3 { 468 reg = <0x3>; 469 label = "lan3"; 470 phy-handle = <&switch0phy3_topaz>; 471 }; 472 473 port@4 { 474 reg = <0x4>; 475 label = "lan4"; 476 phy-handle = <&switch0phy4_topaz>; 477 }; 478 479 port@5 { 480 reg = <0x5>; 481 label = "cpu"; 482 phy-mode = "2500base-x"; 483 managed = "in-band-status"; 484 ethernet = <ð1>; 485 }; 486 }; 487 }; 488 489 switch1@11 { 490 compatible = "marvell,mv88e6190"; 491 reg = <0x11 0>; 492 dsa,member = <0 1>; 493 interrupt-parent = <&moxtet>; 494 interrupts = <MOXTET_IRQ_PERIDOT(1)>; 495 status = "disabled"; 496 497 mdio { 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 switch1phy1: switch1phy1@1 { 502 reg = <0x1>; 503 }; 504 505 switch1phy2: switch1phy2@2 { 506 reg = <0x2>; 507 }; 508 509 switch1phy3: switch1phy3@3 { 510 reg = <0x3>; 511 }; 512 513 switch1phy4: switch1phy4@4 { 514 reg = <0x4>; 515 }; 516 517 switch1phy5: switch1phy5@5 { 518 reg = <0x5>; 519 }; 520 521 switch1phy6: switch1phy6@6 { 522 reg = <0x6>; 523 }; 524 525 switch1phy7: switch1phy7@7 { 526 reg = <0x7>; 527 }; 528 529 switch1phy8: switch1phy8@8 { 530 reg = <0x8>; 531 }; 532 }; 533 534 ports { 535 #address-cells = <1>; 536 #size-cells = <0>; 537 538 port@1 { 539 reg = <0x1>; 540 label = "lan9"; 541 phy-handle = <&switch1phy1>; 542 }; 543 544 port@2 { 545 reg = <0x2>; 546 label = "lan10"; 547 phy-handle = <&switch1phy2>; 548 }; 549 550 port@3 { 551 reg = <0x3>; 552 label = "lan11"; 553 phy-handle = <&switch1phy3>; 554 }; 555 556 port@4 { 557 reg = <0x4>; 558 label = "lan12"; 559 phy-handle = <&switch1phy4>; 560 }; 561 562 port@5 { 563 reg = <0x5>; 564 label = "lan13"; 565 phy-handle = <&switch1phy5>; 566 }; 567 568 port@6 { 569 reg = <0x6>; 570 label = "lan14"; 571 phy-handle = <&switch1phy6>; 572 }; 573 574 port@7 { 575 reg = <0x7>; 576 label = "lan15"; 577 phy-handle = <&switch1phy7>; 578 }; 579 580 port@8 { 581 reg = <0x8>; 582 label = "lan16"; 583 phy-handle = <&switch1phy8>; 584 }; 585 586 switch1port9: port@9 { 587 reg = <0x9>; 588 label = "dsa"; 589 phy-mode = "2500base-x"; 590 managed = "in-band-status"; 591 link = <&switch0port10>; 592 }; 593 594 switch1port10: port@a { 595 reg = <0xa>; 596 label = "dsa"; 597 phy-mode = "2500base-x"; 598 managed = "in-band-status"; 599 link = <&switch2port9>; 600 status = "disabled"; 601 }; 602 603 port-sfp@a { 604 reg = <0xa>; 605 label = "sfp"; 606 sfp = <&sfp>; 607 phy-mode = "sgmii"; 608 managed = "in-band-status"; 609 status = "disabled"; 610 }; 611 }; 612 }; 613 614 switch1@2 { 615 compatible = "marvell,mv88e6085"; 616 reg = <0x2 0>; 617 dsa,member = <0 1>; 618 interrupt-parent = <&moxtet>; 619 interrupts = <MOXTET_IRQ_TOPAZ>; 620 status = "disabled"; 621 622 mdio { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 switch1phy1_topaz: switch1phy1@11 { 627 reg = <0x11>; 628 }; 629 630 switch1phy2_topaz: switch1phy2@12 { 631 reg = <0x12>; 632 }; 633 634 switch1phy3_topaz: switch1phy3@13 { 635 reg = <0x13>; 636 }; 637 638 switch1phy4_topaz: switch1phy4@14 { 639 reg = <0x14>; 640 }; 641 }; 642 643 ports { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 647 port@1 { 648 reg = <0x1>; 649 label = "lan9"; 650 phy-handle = <&switch1phy1_topaz>; 651 }; 652 653 port@2 { 654 reg = <0x2>; 655 label = "lan10"; 656 phy-handle = <&switch1phy2_topaz>; 657 }; 658 659 port@3 { 660 reg = <0x3>; 661 label = "lan11"; 662 phy-handle = <&switch1phy3_topaz>; 663 }; 664 665 port@4 { 666 reg = <0x4>; 667 label = "lan12"; 668 phy-handle = <&switch1phy4_topaz>; 669 }; 670 671 port@5 { 672 reg = <0x5>; 673 label = "dsa"; 674 phy-mode = "2500base-x"; 675 managed = "in-band-status"; 676 link = <&switch0port10>; 677 }; 678 }; 679 }; 680 681 switch2@12 { 682 compatible = "marvell,mv88e6190"; 683 reg = <0x12 0>; 684 dsa,member = <0 2>; 685 interrupt-parent = <&moxtet>; 686 interrupts = <MOXTET_IRQ_PERIDOT(2)>; 687 status = "disabled"; 688 689 mdio { 690 #address-cells = <1>; 691 #size-cells = <0>; 692 693 switch2phy1: switch2phy1@1 { 694 reg = <0x1>; 695 }; 696 697 switch2phy2: switch2phy2@2 { 698 reg = <0x2>; 699 }; 700 701 switch2phy3: switch2phy3@3 { 702 reg = <0x3>; 703 }; 704 705 switch2phy4: switch2phy4@4 { 706 reg = <0x4>; 707 }; 708 709 switch2phy5: switch2phy5@5 { 710 reg = <0x5>; 711 }; 712 713 switch2phy6: switch2phy6@6 { 714 reg = <0x6>; 715 }; 716 717 switch2phy7: switch2phy7@7 { 718 reg = <0x7>; 719 }; 720 721 switch2phy8: switch2phy8@8 { 722 reg = <0x8>; 723 }; 724 }; 725 726 ports { 727 #address-cells = <1>; 728 #size-cells = <0>; 729 730 port@1 { 731 reg = <0x1>; 732 label = "lan17"; 733 phy-handle = <&switch2phy1>; 734 }; 735 736 port@2 { 737 reg = <0x2>; 738 label = "lan18"; 739 phy-handle = <&switch2phy2>; 740 }; 741 742 port@3 { 743 reg = <0x3>; 744 label = "lan19"; 745 phy-handle = <&switch2phy3>; 746 }; 747 748 port@4 { 749 reg = <0x4>; 750 label = "lan20"; 751 phy-handle = <&switch2phy4>; 752 }; 753 754 port@5 { 755 reg = <0x5>; 756 label = "lan21"; 757 phy-handle = <&switch2phy5>; 758 }; 759 760 port@6 { 761 reg = <0x6>; 762 label = "lan22"; 763 phy-handle = <&switch2phy6>; 764 }; 765 766 port@7 { 767 reg = <0x7>; 768 label = "lan23"; 769 phy-handle = <&switch2phy7>; 770 }; 771 772 port@8 { 773 reg = <0x8>; 774 label = "lan24"; 775 phy-handle = <&switch2phy8>; 776 }; 777 778 switch2port9: port@9 { 779 reg = <0x9>; 780 label = "dsa"; 781 phy-mode = "2500base-x"; 782 managed = "in-band-status"; 783 link = <&switch1port10 &switch0port10>; 784 }; 785 786 port-sfp@a { 787 reg = <0xa>; 788 label = "sfp"; 789 sfp = <&sfp>; 790 phy-mode = "sgmii"; 791 managed = "in-band-status"; 792 status = "disabled"; 793 }; 794 }; 795 }; 796 797 switch2@2 { 798 compatible = "marvell,mv88e6085"; 799 reg = <0x2 0>; 800 dsa,member = <0 2>; 801 interrupt-parent = <&moxtet>; 802 interrupts = <MOXTET_IRQ_TOPAZ>; 803 status = "disabled"; 804 805 mdio { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 809 switch2phy1_topaz: switch2phy1@11 { 810 reg = <0x11>; 811 }; 812 813 switch2phy2_topaz: switch2phy2@12 { 814 reg = <0x12>; 815 }; 816 817 switch2phy3_topaz: switch2phy3@13 { 818 reg = <0x13>; 819 }; 820 821 switch2phy4_topaz: switch2phy4@14 { 822 reg = <0x14>; 823 }; 824 }; 825 826 ports { 827 #address-cells = <1>; 828 #size-cells = <0>; 829 830 port@1 { 831 reg = <0x1>; 832 label = "lan17"; 833 phy-handle = <&switch2phy1_topaz>; 834 }; 835 836 port@2 { 837 reg = <0x2>; 838 label = "lan18"; 839 phy-handle = <&switch2phy2_topaz>; 840 }; 841 842 port@3 { 843 reg = <0x3>; 844 label = "lan19"; 845 phy-handle = <&switch2phy3_topaz>; 846 }; 847 848 port@4 { 849 reg = <0x4>; 850 label = "lan20"; 851 phy-handle = <&switch2phy4_topaz>; 852 }; 853 854 port@5 { 855 reg = <0x5>; 856 label = "dsa"; 857 phy-mode = "2500base-x"; 858 managed = "in-band-status"; 859 link = <&switch1port10 &switch0port10>; 860 }; 861 }; 862 }; 863}; 864