1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behún <kabel@kernel.org>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	vsdc_reg: vsdc-reg {
64		compatible = "regulator-gpio";
65		regulator-name = "vsdc";
66		regulator-min-microvolt = <1800000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-boot-on;
69
70		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
71		gpios-states = <0>;
72		states = <1800000 0x1
73			  3300000 0x0>;
74		enable-active-high;
75	};
76
77	vsdio_reg: vsdio-reg {
78		compatible = "regulator-gpio";
79		regulator-name = "vsdio";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		regulator-boot-on;
83
84		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
85		gpios-states = <0>;
86		states = <1800000 0x1
87			  3300000 0x0>;
88		enable-active-high;
89	};
90
91	sdhci1_pwrseq: sdhci1-pwrseq {
92		compatible = "mmc-pwrseq-simple";
93		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
94		status = "okay";
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp";
99		i2c-bus = <&i2c0>;
100		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
105		maximum-power-milliwatt = <3000>;
106
107		/* enabled by U-Boot if SFP module is present */
108		status = "disabled";
109	};
110
111	firmware {
112		armada-3700-rwtm {
113			compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
114		};
115	};
116};
117
118&i2c0 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&i2c1_pins>;
121	clock-frequency = <100000>;
122	status = "okay";
123
124	rtc@6f {
125		compatible = "microchip,mcp7940x";
126		reg = <0x6f>;
127	};
128};
129
130&pcie0 {
131	pinctrl-names = "default";
132	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
133	status = "okay";
134	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
135	/*
136	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
137	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
138	 * 2 size cells and also expects that the second range starts at 16 MB offset. If these
139	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
140	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
141	 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
142	 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
143	 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
144	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
145	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
146	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
147	 */
148	#address-cells = <3>;
149	#size-cells = <2>;
150	ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
151		  0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */
152
153	/* enabled by U-Boot if PCIe module is present */
154	status = "disabled";
155};
156
157&uart0 {
158	status = "okay";
159};
160
161&eth0 {
162	pinctrl-names = "default";
163	pinctrl-0 = <&rgmii_pins>;
164	phy-mode = "rgmii-id";
165	phy-handle = <&phy1>;
166	status = "okay";
167};
168
169&eth1 {
170	phy-mode = "2500base-x";
171	managed = "in-band-status";
172	phys = <&comphy0 1>;
173};
174
175&sdhci0 {
176	wp-inverted;
177	bus-width = <4>;
178	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
179	vqmmc-supply = <&vsdc_reg>;
180	marvell,pad-type = "sd";
181	status = "okay";
182};
183
184&sdhci1 {
185	pinctrl-names = "default";
186	pinctrl-0 = <&sdio_pins>;
187	non-removable;
188	bus-width = <4>;
189	marvell,pad-type = "sd";
190	vqmmc-supply = <&vsdio_reg>;
191	mmc-pwrseq = <&sdhci1_pwrseq>;
192	/* forbid SDR104 for FCC purposes */
193	sdhci-caps-mask = <0x2 0x0>;
194	status = "okay";
195};
196
197&spi0 {
198	status = "okay";
199	pinctrl-names = "default";
200	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
201	assigned-clocks = <&nb_periph_clk 7>;
202	assigned-clock-parents = <&tbg 1>;
203	assigned-clock-rates = <20000000>;
204
205	spi-flash@0 {
206		#address-cells = <1>;
207		#size-cells = <1>;
208		compatible = "jedec,spi-nor";
209		reg = <0>;
210		spi-max-frequency = <20000000>;
211
212		partitions {
213			compatible = "fixed-partitions";
214			#address-cells = <1>;
215			#size-cells = <1>;
216
217			partition@0 {
218				label = "secure-firmware";
219				reg = <0x0 0x20000>;
220			};
221
222			partition@20000 {
223				label = "a53-firmware";
224				reg = <0x20000 0x160000>;
225			};
226
227			partition@180000 {
228				label = "u-boot-env";
229				reg = <0x180000 0x10000>;
230			};
231
232			partition@190000 {
233				label = "Rescue system";
234				reg = <0x190000 0x660000>;
235			};
236
237			partition@7f0000 {
238				label = "dtb";
239				reg = <0x7f0000 0x10000>;
240			};
241		};
242	};
243
244	moxtet: moxtet@1 {
245		#address-cells = <1>;
246		#size-cells = <0>;
247		compatible = "cznic,moxtet";
248		reg = <1>;
249		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
250		spi-max-frequency = <10000000>;
251		spi-cpol;
252		spi-cpha;
253		interrupt-controller;
254		#interrupt-cells = <1>;
255		interrupt-parent = <&gpiosb>;
256		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
257		status = "okay";
258
259		moxtet_sfp: gpio@0 {
260			compatible = "cznic,moxtet-gpio";
261			gpio-controller;
262			#gpio-cells = <2>;
263			reg = <0>;
264			status = "disabled";
265		};
266	};
267};
268
269&usb2 {
270	status = "okay";
271};
272
273&comphy2 {
274	connector {
275		compatible = "usb-a-connector";
276		phy-supply = <&exp_usb3_vbus>;
277	};
278};
279
280&usb3 {
281	status = "okay";
282	phys = <&comphy2 0>;
283};
284
285&mdio {
286	pinctrl-names = "default";
287	pinctrl-0 = <&smi_pins>;
288	status = "okay";
289
290	phy1: ethernet-phy@1 {
291		reg = <1>;
292	};
293
294	/* switch nodes are enabled by U-Boot if modules are present */
295	switch0@10 {
296		compatible = "marvell,mv88e6190";
297		reg = <0x10 0>;
298		dsa,member = <0 0>;
299		interrupt-parent = <&moxtet>;
300		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
301		status = "disabled";
302
303		mdio {
304			#address-cells = <1>;
305			#size-cells = <0>;
306
307			switch0phy1: switch0phy1@1 {
308				reg = <0x1>;
309			};
310
311			switch0phy2: switch0phy2@2 {
312				reg = <0x2>;
313			};
314
315			switch0phy3: switch0phy3@3 {
316				reg = <0x3>;
317			};
318
319			switch0phy4: switch0phy4@4 {
320				reg = <0x4>;
321			};
322
323			switch0phy5: switch0phy5@5 {
324				reg = <0x5>;
325			};
326
327			switch0phy6: switch0phy6@6 {
328				reg = <0x6>;
329			};
330
331			switch0phy7: switch0phy7@7 {
332				reg = <0x7>;
333			};
334
335			switch0phy8: switch0phy8@8 {
336				reg = <0x8>;
337			};
338		};
339
340		ports {
341			#address-cells = <1>;
342			#size-cells = <0>;
343
344			port@1 {
345				reg = <0x1>;
346				label = "lan1";
347				phy-handle = <&switch0phy1>;
348			};
349
350			port@2 {
351				reg = <0x2>;
352				label = "lan2";
353				phy-handle = <&switch0phy2>;
354			};
355
356			port@3 {
357				reg = <0x3>;
358				label = "lan3";
359				phy-handle = <&switch0phy3>;
360			};
361
362			port@4 {
363				reg = <0x4>;
364				label = "lan4";
365				phy-handle = <&switch0phy4>;
366			};
367
368			port@5 {
369				reg = <0x5>;
370				label = "lan5";
371				phy-handle = <&switch0phy5>;
372			};
373
374			port@6 {
375				reg = <0x6>;
376				label = "lan6";
377				phy-handle = <&switch0phy6>;
378			};
379
380			port@7 {
381				reg = <0x7>;
382				label = "lan7";
383				phy-handle = <&switch0phy7>;
384			};
385
386			port@8 {
387				reg = <0x8>;
388				label = "lan8";
389				phy-handle = <&switch0phy8>;
390			};
391
392			port@9 {
393				reg = <0x9>;
394				label = "cpu";
395				ethernet = <&eth1>;
396				phy-mode = "2500base-x";
397				managed = "in-band-status";
398			};
399
400			switch0port10: port@a {
401				reg = <0xa>;
402				label = "dsa";
403				phy-mode = "2500base-x";
404				managed = "in-band-status";
405				link = <&switch1port9 &switch2port9>;
406				status = "disabled";
407			};
408
409			port-sfp@a {
410				reg = <0xa>;
411				label = "sfp";
412				sfp = <&sfp>;
413				phy-mode = "sgmii";
414				managed = "in-band-status";
415				status = "disabled";
416			};
417		};
418	};
419
420	switch0@2 {
421		compatible = "marvell,mv88e6085";
422		reg = <0x2 0>;
423		dsa,member = <0 0>;
424		interrupt-parent = <&moxtet>;
425		interrupts = <MOXTET_IRQ_TOPAZ>;
426		status = "disabled";
427
428		mdio {
429			#address-cells = <1>;
430			#size-cells = <0>;
431
432			switch0phy1_topaz: switch0phy1@11 {
433				reg = <0x11>;
434			};
435
436			switch0phy2_topaz: switch0phy2@12 {
437				reg = <0x12>;
438			};
439
440			switch0phy3_topaz: switch0phy3@13 {
441				reg = <0x13>;
442			};
443
444			switch0phy4_topaz: switch0phy4@14 {
445				reg = <0x14>;
446			};
447		};
448
449		ports {
450			#address-cells = <1>;
451			#size-cells = <0>;
452
453			port@1 {
454				reg = <0x1>;
455				label = "lan1";
456				phy-handle = <&switch0phy1_topaz>;
457			};
458
459			port@2 {
460				reg = <0x2>;
461				label = "lan2";
462				phy-handle = <&switch0phy2_topaz>;
463			};
464
465			port@3 {
466				reg = <0x3>;
467				label = "lan3";
468				phy-handle = <&switch0phy3_topaz>;
469			};
470
471			port@4 {
472				reg = <0x4>;
473				label = "lan4";
474				phy-handle = <&switch0phy4_topaz>;
475			};
476
477			port@5 {
478				reg = <0x5>;
479				label = "cpu";
480				phy-mode = "2500base-x";
481				managed = "in-band-status";
482				ethernet = <&eth1>;
483			};
484		};
485	};
486
487	switch1@11 {
488		compatible = "marvell,mv88e6190";
489		reg = <0x11 0>;
490		dsa,member = <0 1>;
491		interrupt-parent = <&moxtet>;
492		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
493		status = "disabled";
494
495		mdio {
496			#address-cells = <1>;
497			#size-cells = <0>;
498
499			switch1phy1: switch1phy1@1 {
500				reg = <0x1>;
501			};
502
503			switch1phy2: switch1phy2@2 {
504				reg = <0x2>;
505			};
506
507			switch1phy3: switch1phy3@3 {
508				reg = <0x3>;
509			};
510
511			switch1phy4: switch1phy4@4 {
512				reg = <0x4>;
513			};
514
515			switch1phy5: switch1phy5@5 {
516				reg = <0x5>;
517			};
518
519			switch1phy6: switch1phy6@6 {
520				reg = <0x6>;
521			};
522
523			switch1phy7: switch1phy7@7 {
524				reg = <0x7>;
525			};
526
527			switch1phy8: switch1phy8@8 {
528				reg = <0x8>;
529			};
530		};
531
532		ports {
533			#address-cells = <1>;
534			#size-cells = <0>;
535
536			port@1 {
537				reg = <0x1>;
538				label = "lan9";
539				phy-handle = <&switch1phy1>;
540			};
541
542			port@2 {
543				reg = <0x2>;
544				label = "lan10";
545				phy-handle = <&switch1phy2>;
546			};
547
548			port@3 {
549				reg = <0x3>;
550				label = "lan11";
551				phy-handle = <&switch1phy3>;
552			};
553
554			port@4 {
555				reg = <0x4>;
556				label = "lan12";
557				phy-handle = <&switch1phy4>;
558			};
559
560			port@5 {
561				reg = <0x5>;
562				label = "lan13";
563				phy-handle = <&switch1phy5>;
564			};
565
566			port@6 {
567				reg = <0x6>;
568				label = "lan14";
569				phy-handle = <&switch1phy6>;
570			};
571
572			port@7 {
573				reg = <0x7>;
574				label = "lan15";
575				phy-handle = <&switch1phy7>;
576			};
577
578			port@8 {
579				reg = <0x8>;
580				label = "lan16";
581				phy-handle = <&switch1phy8>;
582			};
583
584			switch1port9: port@9 {
585				reg = <0x9>;
586				label = "dsa";
587				phy-mode = "2500base-x";
588				managed = "in-band-status";
589				link = <&switch0port10>;
590			};
591
592			switch1port10: port@a {
593				reg = <0xa>;
594				label = "dsa";
595				phy-mode = "2500base-x";
596				managed = "in-band-status";
597				link = <&switch2port9>;
598				status = "disabled";
599			};
600
601			port-sfp@a {
602				reg = <0xa>;
603				label = "sfp";
604				sfp = <&sfp>;
605				phy-mode = "sgmii";
606				managed = "in-band-status";
607				status = "disabled";
608			};
609		};
610	};
611
612	switch1@2 {
613		compatible = "marvell,mv88e6085";
614		reg = <0x2 0>;
615		dsa,member = <0 1>;
616		interrupt-parent = <&moxtet>;
617		interrupts = <MOXTET_IRQ_TOPAZ>;
618		status = "disabled";
619
620		mdio {
621			#address-cells = <1>;
622			#size-cells = <0>;
623
624			switch1phy1_topaz: switch1phy1@11 {
625				reg = <0x11>;
626			};
627
628			switch1phy2_topaz: switch1phy2@12 {
629				reg = <0x12>;
630			};
631
632			switch1phy3_topaz: switch1phy3@13 {
633				reg = <0x13>;
634			};
635
636			switch1phy4_topaz: switch1phy4@14 {
637				reg = <0x14>;
638			};
639		};
640
641		ports {
642			#address-cells = <1>;
643			#size-cells = <0>;
644
645			port@1 {
646				reg = <0x1>;
647				label = "lan9";
648				phy-handle = <&switch1phy1_topaz>;
649			};
650
651			port@2 {
652				reg = <0x2>;
653				label = "lan10";
654				phy-handle = <&switch1phy2_topaz>;
655			};
656
657			port@3 {
658				reg = <0x3>;
659				label = "lan11";
660				phy-handle = <&switch1phy3_topaz>;
661			};
662
663			port@4 {
664				reg = <0x4>;
665				label = "lan12";
666				phy-handle = <&switch1phy4_topaz>;
667			};
668
669			port@5 {
670				reg = <0x5>;
671				label = "dsa";
672				phy-mode = "2500base-x";
673				managed = "in-band-status";
674				link = <&switch0port10>;
675			};
676		};
677	};
678
679	switch2@12 {
680		compatible = "marvell,mv88e6190";
681		reg = <0x12 0>;
682		dsa,member = <0 2>;
683		interrupt-parent = <&moxtet>;
684		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
685		status = "disabled";
686
687		mdio {
688			#address-cells = <1>;
689			#size-cells = <0>;
690
691			switch2phy1: switch2phy1@1 {
692				reg = <0x1>;
693			};
694
695			switch2phy2: switch2phy2@2 {
696				reg = <0x2>;
697			};
698
699			switch2phy3: switch2phy3@3 {
700				reg = <0x3>;
701			};
702
703			switch2phy4: switch2phy4@4 {
704				reg = <0x4>;
705			};
706
707			switch2phy5: switch2phy5@5 {
708				reg = <0x5>;
709			};
710
711			switch2phy6: switch2phy6@6 {
712				reg = <0x6>;
713			};
714
715			switch2phy7: switch2phy7@7 {
716				reg = <0x7>;
717			};
718
719			switch2phy8: switch2phy8@8 {
720				reg = <0x8>;
721			};
722		};
723
724		ports {
725			#address-cells = <1>;
726			#size-cells = <0>;
727
728			port@1 {
729				reg = <0x1>;
730				label = "lan17";
731				phy-handle = <&switch2phy1>;
732			};
733
734			port@2 {
735				reg = <0x2>;
736				label = "lan18";
737				phy-handle = <&switch2phy2>;
738			};
739
740			port@3 {
741				reg = <0x3>;
742				label = "lan19";
743				phy-handle = <&switch2phy3>;
744			};
745
746			port@4 {
747				reg = <0x4>;
748				label = "lan20";
749				phy-handle = <&switch2phy4>;
750			};
751
752			port@5 {
753				reg = <0x5>;
754				label = "lan21";
755				phy-handle = <&switch2phy5>;
756			};
757
758			port@6 {
759				reg = <0x6>;
760				label = "lan22";
761				phy-handle = <&switch2phy6>;
762			};
763
764			port@7 {
765				reg = <0x7>;
766				label = "lan23";
767				phy-handle = <&switch2phy7>;
768			};
769
770			port@8 {
771				reg = <0x8>;
772				label = "lan24";
773				phy-handle = <&switch2phy8>;
774			};
775
776			switch2port9: port@9 {
777				reg = <0x9>;
778				label = "dsa";
779				phy-mode = "2500base-x";
780				managed = "in-band-status";
781				link = <&switch1port10 &switch0port10>;
782			};
783
784			port-sfp@a {
785				reg = <0xa>;
786				label = "sfp";
787				sfp = <&sfp>;
788				phy-mode = "sgmii";
789				managed = "in-band-status";
790				status = "disabled";
791			};
792		};
793	};
794
795	switch2@2 {
796		compatible = "marvell,mv88e6085";
797		reg = <0x2 0>;
798		dsa,member = <0 2>;
799		interrupt-parent = <&moxtet>;
800		interrupts = <MOXTET_IRQ_TOPAZ>;
801		status = "disabled";
802
803		mdio {
804			#address-cells = <1>;
805			#size-cells = <0>;
806
807			switch2phy1_topaz: switch2phy1@11 {
808				reg = <0x11>;
809			};
810
811			switch2phy2_topaz: switch2phy2@12 {
812				reg = <0x12>;
813			};
814
815			switch2phy3_topaz: switch2phy3@13 {
816				reg = <0x13>;
817			};
818
819			switch2phy4_topaz: switch2phy4@14 {
820				reg = <0x14>;
821			};
822		};
823
824		ports {
825			#address-cells = <1>;
826			#size-cells = <0>;
827
828			port@1 {
829				reg = <0x1>;
830				label = "lan17";
831				phy-handle = <&switch2phy1_topaz>;
832			};
833
834			port@2 {
835				reg = <0x2>;
836				label = "lan18";
837				phy-handle = <&switch2phy2_topaz>;
838			};
839
840			port@3 {
841				reg = <0x3>;
842				label = "lan19";
843				phy-handle = <&switch2phy3_topaz>;
844			};
845
846			port@4 {
847				reg = <0x4>;
848				label = "lan20";
849				phy-handle = <&switch2phy4_topaz>;
850			};
851
852			port@5 {
853				reg = <0x5>;
854				label = "dsa";
855				phy-mode = "2500base-x";
856				managed = "in-band-status";
857				link = <&switch1port10 &switch0port10>;
858			};
859		};
860	};
861};
862