1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	usb3_phy: usb3-phy {
64		compatible = "usb-nop-xceiv";
65		vcc-supply = <&exp_usb3_vbus>;
66	};
67
68	vsdc_reg: vsdc-reg {
69		compatible = "regulator-gpio";
70		regulator-name = "vsdc";
71		regulator-min-microvolt = <1800000>;
72		regulator-max-microvolt = <3300000>;
73		regulator-boot-on;
74
75		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
76		gpios-states = <0>;
77		states = <1800000 0x1
78			  3300000 0x0>;
79		enable-active-high;
80	};
81
82	vsdio_reg: vsdio-reg {
83		compatible = "regulator-gpio";
84		regulator-name = "vsdio";
85		regulator-min-microvolt = <1800000>;
86		regulator-max-microvolt = <3300000>;
87		regulator-boot-on;
88
89		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
90		gpios-states = <0>;
91		states = <1800000 0x1
92			  3300000 0x0>;
93		enable-active-high;
94	};
95
96	sdhci1_pwrseq: sdhci1-pwrseq {
97		compatible = "mmc-pwrseq-simple";
98		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
99		status = "okay";
100	};
101
102	sfp: sfp {
103		compatible = "sff,sfp+";
104		i2c-bus = <&i2c0>;
105		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
106		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
107		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
108		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
109		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
110
111		/* enabled by U-Boot if SFP module is present */
112		status = "disabled";
113	};
114
115	firmware {
116		turris-mox-rwtm {
117			compatible = "cznic,turris-mox-rwtm";
118			mboxes = <&rwtm 0>;
119			status = "okay";
120		};
121	};
122};
123
124&i2c0 {
125	pinctrl-names = "default";
126	pinctrl-0 = <&i2c1_pins>;
127	clock-frequency = <100000>;
128	status = "okay";
129
130	rtc@6f {
131		compatible = "microchip,mcp7940x";
132		reg = <0x6f>;
133	};
134};
135
136&pcie_reset_pins {
137	function = "gpio";
138};
139
140&pcie0 {
141	pinctrl-names = "default";
142	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
143	status = "okay";
144	max-link-speed = <2>;
145	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
146	phys = <&comphy1 0>;
147
148	/* enabled by U-Boot if PCIe module is present */
149	status = "disabled";
150};
151
152&uart0 {
153	status = "okay";
154};
155
156&eth0 {
157	pinctrl-names = "default";
158	pinctrl-0 = <&rgmii_pins>;
159	phy-mode = "rgmii-id";
160	phy = <&phy1>;
161	status = "okay";
162};
163
164&eth1 {
165	phy-mode = "2500base-x";
166	managed = "in-band-status";
167	phys = <&comphy0 1>;
168};
169
170&sdhci0 {
171	wp-inverted;
172	bus-width = <4>;
173	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
174	vqmmc-supply = <&vsdc_reg>;
175	marvell,pad-type = "sd";
176	status = "okay";
177};
178
179&sdhci1 {
180	pinctrl-names = "default";
181	pinctrl-0 = <&sdio_pins>;
182	non-removable;
183	bus-width = <4>;
184	marvell,pad-type = "sd";
185	vqmmc-supply = <&vsdio_reg>;
186	mmc-pwrseq = <&sdhci1_pwrseq>;
187	status = "okay";
188};
189
190&spi0 {
191	status = "okay";
192	pinctrl-names = "default";
193	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
194	assigned-clocks = <&nb_periph_clk 7>;
195	assigned-clock-parents = <&tbg 1>;
196	assigned-clock-rates = <20000000>;
197
198	spi-flash@0 {
199		#address-cells = <1>;
200		#size-cells = <1>;
201		compatible = "jedec,spi-nor";
202		reg = <0>;
203		spi-max-frequency = <20000000>;
204
205		partitions {
206			compatible = "fixed-partitions";
207			#address-cells = <1>;
208			#size-cells = <1>;
209
210			partition@0 {
211				label = "secure-firmware";
212				reg = <0x0 0x20000>;
213			};
214
215			partition@20000 {
216				label = "u-boot";
217				reg = <0x20000 0x160000>;
218			};
219
220			partition@180000 {
221				label = "u-boot-env";
222				reg = <0x180000 0x10000>;
223			};
224
225			partition@190000 {
226				label = "Rescue system";
227				reg = <0x190000 0x660000>;
228			};
229
230			partition@7f0000 {
231				label = "dtb";
232				reg = <0x7f0000 0x10000>;
233			};
234		};
235	};
236
237	moxtet: moxtet@1 {
238		#address-cells = <1>;
239		#size-cells = <0>;
240		compatible = "cznic,moxtet";
241		reg = <1>;
242		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
243		spi-max-frequency = <10000000>;
244		spi-cpol;
245		spi-cpha;
246		interrupt-controller;
247		#interrupt-cells = <1>;
248		interrupt-parent = <&gpiosb>;
249		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
250		status = "okay";
251
252		moxtet_sfp: gpio@0 {
253			compatible = "cznic,moxtet-gpio";
254			gpio-controller;
255			#gpio-cells = <2>;
256			reg = <0>;
257			status = "disabled";
258		};
259	};
260};
261
262&usb2 {
263	status = "okay";
264};
265
266&usb3 {
267	status = "okay";
268	phys = <&comphy2 0>;
269	usb-phy = <&usb3_phy>;
270};
271
272&mdio {
273	pinctrl-names = "default";
274	pinctrl-0 = <&smi_pins>;
275	status = "okay";
276
277	phy1: ethernet-phy@1 {
278		reg = <1>;
279	};
280
281	/* switch nodes are enabled by U-Boot if modules are present */
282	switch0@10 {
283		compatible = "marvell,mv88e6190";
284		reg = <0x10 0>;
285		dsa,member = <0 0>;
286		interrupt-parent = <&moxtet>;
287		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
288		status = "disabled";
289
290		mdio {
291			#address-cells = <1>;
292			#size-cells = <0>;
293
294			switch0phy1: switch0phy1@1 {
295				reg = <0x1>;
296			};
297
298			switch0phy2: switch0phy2@2 {
299				reg = <0x2>;
300			};
301
302			switch0phy3: switch0phy3@3 {
303				reg = <0x3>;
304			};
305
306			switch0phy4: switch0phy4@4 {
307				reg = <0x4>;
308			};
309
310			switch0phy5: switch0phy5@5 {
311				reg = <0x5>;
312			};
313
314			switch0phy6: switch0phy6@6 {
315				reg = <0x6>;
316			};
317
318			switch0phy7: switch0phy7@7 {
319				reg = <0x7>;
320			};
321
322			switch0phy8: switch0phy8@8 {
323				reg = <0x8>;
324			};
325		};
326
327		ports {
328			#address-cells = <1>;
329			#size-cells = <0>;
330
331			port@1 {
332				reg = <0x1>;
333				label = "lan1";
334				phy-handle = <&switch0phy1>;
335			};
336
337			port@2 {
338				reg = <0x2>;
339				label = "lan2";
340				phy-handle = <&switch0phy2>;
341			};
342
343			port@3 {
344				reg = <0x3>;
345				label = "lan3";
346				phy-handle = <&switch0phy3>;
347			};
348
349			port@4 {
350				reg = <0x4>;
351				label = "lan4";
352				phy-handle = <&switch0phy4>;
353			};
354
355			port@5 {
356				reg = <0x5>;
357				label = "lan5";
358				phy-handle = <&switch0phy5>;
359			};
360
361			port@6 {
362				reg = <0x6>;
363				label = "lan6";
364				phy-handle = <&switch0phy6>;
365			};
366
367			port@7 {
368				reg = <0x7>;
369				label = "lan7";
370				phy-handle = <&switch0phy7>;
371			};
372
373			port@8 {
374				reg = <0x8>;
375				label = "lan8";
376				phy-handle = <&switch0phy8>;
377			};
378
379			port@9 {
380				reg = <0x9>;
381				label = "cpu";
382				ethernet = <&eth1>;
383				phy-mode = "2500base-x";
384				managed = "in-band-status";
385			};
386
387			switch0port10: port@a {
388				reg = <0xa>;
389				label = "dsa";
390				phy-mode = "2500base-x";
391				managed = "in-band-status";
392				link = <&switch1port9 &switch2port9>;
393				status = "disabled";
394			};
395
396			port-sfp@a {
397				reg = <0xa>;
398				label = "sfp";
399				sfp = <&sfp>;
400				phy-mode = "sgmii";
401				managed = "in-band-status";
402				status = "disabled";
403			};
404		};
405	};
406
407	switch0@2 {
408		compatible = "marvell,mv88e6085";
409		reg = <0x2 0>;
410		dsa,member = <0 0>;
411		interrupt-parent = <&moxtet>;
412		interrupts = <MOXTET_IRQ_TOPAZ>;
413		status = "disabled";
414
415		mdio {
416			#address-cells = <1>;
417			#size-cells = <0>;
418
419			switch0phy1_topaz: switch0phy1@11 {
420				reg = <0x11>;
421			};
422
423			switch0phy2_topaz: switch0phy2@12 {
424				reg = <0x12>;
425			};
426
427			switch0phy3_topaz: switch0phy3@13 {
428				reg = <0x13>;
429			};
430
431			switch0phy4_topaz: switch0phy4@14 {
432				reg = <0x14>;
433			};
434		};
435
436		ports {
437			#address-cells = <1>;
438			#size-cells = <0>;
439
440			port@1 {
441				reg = <0x1>;
442				label = "lan1";
443				phy-handle = <&switch0phy1_topaz>;
444			};
445
446			port@2 {
447				reg = <0x2>;
448				label = "lan2";
449				phy-handle = <&switch0phy2_topaz>;
450			};
451
452			port@3 {
453				reg = <0x3>;
454				label = "lan3";
455				phy-handle = <&switch0phy3_topaz>;
456			};
457
458			port@4 {
459				reg = <0x4>;
460				label = "lan4";
461				phy-handle = <&switch0phy4_topaz>;
462			};
463
464			port@5 {
465				reg = <0x5>;
466				label = "cpu";
467				phy-mode = "2500base-x";
468				managed = "in-band-status";
469				ethernet = <&eth1>;
470			};
471		};
472	};
473
474	switch1@11 {
475		compatible = "marvell,mv88e6190";
476		reg = <0x11 0>;
477		dsa,member = <0 1>;
478		interrupt-parent = <&moxtet>;
479		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
480		status = "disabled";
481
482		mdio {
483			#address-cells = <1>;
484			#size-cells = <0>;
485
486			switch1phy1: switch1phy1@1 {
487				reg = <0x1>;
488			};
489
490			switch1phy2: switch1phy2@2 {
491				reg = <0x2>;
492			};
493
494			switch1phy3: switch1phy3@3 {
495				reg = <0x3>;
496			};
497
498			switch1phy4: switch1phy4@4 {
499				reg = <0x4>;
500			};
501
502			switch1phy5: switch1phy5@5 {
503				reg = <0x5>;
504			};
505
506			switch1phy6: switch1phy6@6 {
507				reg = <0x6>;
508			};
509
510			switch1phy7: switch1phy7@7 {
511				reg = <0x7>;
512			};
513
514			switch1phy8: switch1phy8@8 {
515				reg = <0x8>;
516			};
517		};
518
519		ports {
520			#address-cells = <1>;
521			#size-cells = <0>;
522
523			port@1 {
524				reg = <0x1>;
525				label = "lan9";
526				phy-handle = <&switch1phy1>;
527			};
528
529			port@2 {
530				reg = <0x2>;
531				label = "lan10";
532				phy-handle = <&switch1phy2>;
533			};
534
535			port@3 {
536				reg = <0x3>;
537				label = "lan11";
538				phy-handle = <&switch1phy3>;
539			};
540
541			port@4 {
542				reg = <0x4>;
543				label = "lan12";
544				phy-handle = <&switch1phy4>;
545			};
546
547			port@5 {
548				reg = <0x5>;
549				label = "lan13";
550				phy-handle = <&switch1phy5>;
551			};
552
553			port@6 {
554				reg = <0x6>;
555				label = "lan14";
556				phy-handle = <&switch1phy6>;
557			};
558
559			port@7 {
560				reg = <0x7>;
561				label = "lan15";
562				phy-handle = <&switch1phy7>;
563			};
564
565			port@8 {
566				reg = <0x8>;
567				label = "lan16";
568				phy-handle = <&switch1phy8>;
569			};
570
571			switch1port9: port@9 {
572				reg = <0x9>;
573				label = "dsa";
574				phy-mode = "2500base-x";
575				managed = "in-band-status";
576				link = <&switch0port10>;
577			};
578
579			switch1port10: port@a {
580				reg = <0xa>;
581				label = "dsa";
582				phy-mode = "2500base-x";
583				managed = "in-band-status";
584				link = <&switch2port9>;
585				status = "disabled";
586			};
587
588			port-sfp@a {
589				reg = <0xa>;
590				label = "sfp";
591				sfp = <&sfp>;
592				phy-mode = "sgmii";
593				managed = "in-band-status";
594				status = "disabled";
595			};
596		};
597	};
598
599	switch1@2 {
600		compatible = "marvell,mv88e6085";
601		reg = <0x2 0>;
602		dsa,member = <0 1>;
603		interrupt-parent = <&moxtet>;
604		interrupts = <MOXTET_IRQ_TOPAZ>;
605		status = "disabled";
606
607		mdio {
608			#address-cells = <1>;
609			#size-cells = <0>;
610
611			switch1phy1_topaz: switch1phy1@11 {
612				reg = <0x11>;
613			};
614
615			switch1phy2_topaz: switch1phy2@12 {
616				reg = <0x12>;
617			};
618
619			switch1phy3_topaz: switch1phy3@13 {
620				reg = <0x13>;
621			};
622
623			switch1phy4_topaz: switch1phy4@14 {
624				reg = <0x14>;
625			};
626		};
627
628		ports {
629			#address-cells = <1>;
630			#size-cells = <0>;
631
632			port@1 {
633				reg = <0x1>;
634				label = "lan9";
635				phy-handle = <&switch1phy1_topaz>;
636			};
637
638			port@2 {
639				reg = <0x2>;
640				label = "lan10";
641				phy-handle = <&switch1phy2_topaz>;
642			};
643
644			port@3 {
645				reg = <0x3>;
646				label = "lan11";
647				phy-handle = <&switch1phy3_topaz>;
648			};
649
650			port@4 {
651				reg = <0x4>;
652				label = "lan12";
653				phy-handle = <&switch1phy4_topaz>;
654			};
655
656			port@5 {
657				reg = <0x5>;
658				label = "dsa";
659				phy-mode = "2500base-x";
660				managed = "in-band-status";
661				link = <&switch0port10>;
662			};
663		};
664	};
665
666	switch2@12 {
667		compatible = "marvell,mv88e6190";
668		reg = <0x12 0>;
669		dsa,member = <0 2>;
670		interrupt-parent = <&moxtet>;
671		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
672		status = "disabled";
673
674		mdio {
675			#address-cells = <1>;
676			#size-cells = <0>;
677
678			switch2phy1: switch2phy1@1 {
679				reg = <0x1>;
680			};
681
682			switch2phy2: switch2phy2@2 {
683				reg = <0x2>;
684			};
685
686			switch2phy3: switch2phy3@3 {
687				reg = <0x3>;
688			};
689
690			switch2phy4: switch2phy4@4 {
691				reg = <0x4>;
692			};
693
694			switch2phy5: switch2phy5@5 {
695				reg = <0x5>;
696			};
697
698			switch2phy6: switch2phy6@6 {
699				reg = <0x6>;
700			};
701
702			switch2phy7: switch2phy7@7 {
703				reg = <0x7>;
704			};
705
706			switch2phy8: switch2phy8@8 {
707				reg = <0x8>;
708			};
709		};
710
711		ports {
712			#address-cells = <1>;
713			#size-cells = <0>;
714
715			port@1 {
716				reg = <0x1>;
717				label = "lan17";
718				phy-handle = <&switch2phy1>;
719			};
720
721			port@2 {
722				reg = <0x2>;
723				label = "lan18";
724				phy-handle = <&switch2phy2>;
725			};
726
727			port@3 {
728				reg = <0x3>;
729				label = "lan19";
730				phy-handle = <&switch2phy3>;
731			};
732
733			port@4 {
734				reg = <0x4>;
735				label = "lan20";
736				phy-handle = <&switch2phy4>;
737			};
738
739			port@5 {
740				reg = <0x5>;
741				label = "lan21";
742				phy-handle = <&switch2phy5>;
743			};
744
745			port@6 {
746				reg = <0x6>;
747				label = "lan22";
748				phy-handle = <&switch2phy6>;
749			};
750
751			port@7 {
752				reg = <0x7>;
753				label = "lan23";
754				phy-handle = <&switch2phy7>;
755			};
756
757			port@8 {
758				reg = <0x8>;
759				label = "lan24";
760				phy-handle = <&switch2phy8>;
761			};
762
763			switch2port9: port@9 {
764				reg = <0x9>;
765				label = "dsa";
766				phy-mode = "2500base-x";
767				managed = "in-band-status";
768				link = <&switch1port10 &switch0port10>;
769			};
770
771			port-sfp@a {
772				reg = <0xa>;
773				label = "sfp";
774				sfp = <&sfp>;
775				phy-mode = "sgmii";
776				managed = "in-band-status";
777				status = "disabled";
778			};
779		};
780	};
781
782	switch2@2 {
783		compatible = "marvell,mv88e6085";
784		reg = <0x2 0>;
785		dsa,member = <0 2>;
786		interrupt-parent = <&moxtet>;
787		interrupts = <MOXTET_IRQ_TOPAZ>;
788		status = "disabled";
789
790		mdio {
791			#address-cells = <1>;
792			#size-cells = <0>;
793
794			switch2phy1_topaz: switch2phy1@11 {
795				reg = <0x11>;
796			};
797
798			switch2phy2_topaz: switch2phy2@12 {
799				reg = <0x12>;
800			};
801
802			switch2phy3_topaz: switch2phy3@13 {
803				reg = <0x13>;
804			};
805
806			switch2phy4_topaz: switch2phy4@14 {
807				reg = <0x14>;
808			};
809		};
810
811		ports {
812			#address-cells = <1>;
813			#size-cells = <0>;
814
815			port@1 {
816				reg = <0x1>;
817				label = "lan17";
818				phy-handle = <&switch2phy1_topaz>;
819			};
820
821			port@2 {
822				reg = <0x2>;
823				label = "lan18";
824				phy-handle = <&switch2phy2_topaz>;
825			};
826
827			port@3 {
828				reg = <0x3>;
829				label = "lan19";
830				phy-handle = <&switch2phy3_topaz>;
831			};
832
833			port@4 {
834				reg = <0x4>;
835				label = "lan20";
836				phy-handle = <&switch2phy4_topaz>;
837			};
838
839			port@5 {
840				reg = <0x5>;
841				label = "dsa";
842				phy-mode = "2500base-x";
843				managed = "in-band-status";
844				link = <&switch1port10 &switch0port10>;
845			};
846		};
847	};
848};
849