1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for CZ.NIC Turris Mox Board 4 * 2019 by Marek Behún <kabel@kernel.org> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/bus/moxtet.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include "armada-372x.dtsi" 13 14/ { 15 model = "CZ.NIC Turris Mox Board"; 16 compatible = "cznic,turris-mox", "marvell,armada3720", 17 "marvell,armada3710"; 18 19 aliases { 20 spi0 = &spi0; 21 ethernet0 = ð0; 22 ethernet1 = ð1; 23 mmc0 = &sdhci0; 24 mmc1 = &sdhci1; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@0 { 32 device_type = "memory"; 33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 34 }; 35 36 leds { 37 compatible = "gpio-leds"; 38 led { 39 label = "mox:red:activity"; 40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 41 linux,default-trigger = "default-on"; 42 }; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 48 key-reset { 49 label = "reset"; 50 linux,code = <KEY_RESTART>; 51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 52 debounce-interval = <60>; 53 }; 54 }; 55 56 exp_usb3_vbus: usb3-vbus { 57 compatible = "regulator-fixed"; 58 regulator-name = "usb3-vbus"; 59 regulator-min-microvolt = <5000000>; 60 regulator-max-microvolt = <5000000>; 61 enable-active-high; 62 regulator-always-on; 63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 64 }; 65 66 vsdc_reg: vsdc-reg { 67 compatible = "regulator-gpio"; 68 regulator-name = "vsdc"; 69 regulator-min-microvolt = <1800000>; 70 regulator-max-microvolt = <3300000>; 71 regulator-boot-on; 72 73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 74 gpios-states = <0>; 75 states = <1800000 0x1 76 3300000 0x0>; 77 enable-active-high; 78 }; 79 80 vsdio_reg: vsdio-reg { 81 compatible = "regulator-gpio"; 82 regulator-name = "vsdio"; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 88 gpios-states = <0>; 89 states = <1800000 0x1 90 3300000 0x0>; 91 enable-active-high; 92 }; 93 94 sdhci1_pwrseq: sdhci1-pwrseq { 95 compatible = "mmc-pwrseq-simple"; 96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 97 status = "okay"; 98 }; 99 100 sfp: sfp { 101 compatible = "sff,sfp"; 102 i2c-bus = <&i2c0>; 103 los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 104 tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 105 mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 106 tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 107 rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 108 maximum-power-milliwatt = <3000>; 109 110 /* enabled by U-Boot if SFP module is present */ 111 status = "disabled"; 112 }; 113 114 firmware { 115 armada-3700-rwtm { 116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; 117 }; 118 }; 119}; 120 121&i2c0 { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&i2c1_pins>; 124 clock-frequency = <100000>; 125 /delete-property/ mrvl,i2c-fast-mode; 126 status = "okay"; 127 128 rtc@6f { 129 compatible = "microchip,mcp7940x"; 130 reg = <0x6f>; 131 }; 132}; 133 134&pcie0 { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 137 status = "okay"; 138 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 139 slot-power-limit-milliwatt = <10000>; 140 /* 141 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property 142 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and 143 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it 144 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so 145 * no remapping) and that this address is the lowest from all specified ranges. If these 146 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address 147 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window 148 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. 149 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in 150 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): 151 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 152 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf 153 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 154 * Bug related to requirement of same child and parent addresses for first range is fixed 155 * in U-Boot version 2022.04 by following commit: 156 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 157 */ 158 #address-cells = <3>; 159 #size-cells = <2>; 160 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ 161 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ 162 163 /* enabled by U-Boot if PCIe module is present */ 164 status = "disabled"; 165}; 166 167&uart0 { 168 status = "okay"; 169}; 170 171ð0 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&rgmii_pins>; 174 phy-mode = "rgmii-id"; 175 phy-handle = <&phy1>; 176 status = "okay"; 177}; 178 179ð1 { 180 phy-mode = "2500base-x"; 181 managed = "in-band-status"; 182 phys = <&comphy0 1>; 183}; 184 185&sdhci0 { 186 wp-inverted; 187 bus-width = <4>; 188 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 189 vqmmc-supply = <&vsdc_reg>; 190 marvell,pad-type = "sd"; 191 status = "okay"; 192}; 193 194&sdhci1 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&sdio_pins>; 197 non-removable; 198 bus-width = <4>; 199 marvell,pad-type = "sd"; 200 vqmmc-supply = <&vsdio_reg>; 201 mmc-pwrseq = <&sdhci1_pwrseq>; 202 /* forbid SDR104 for FCC purposes */ 203 sdhci-caps-mask = <0x2 0x0>; 204 status = "okay"; 205}; 206 207&spi0 { 208 status = "okay"; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 211 assigned-clocks = <&nb_periph_clk 7>; 212 assigned-clock-parents = <&tbg 1>; 213 assigned-clock-rates = <20000000>; 214 215 flash@0 { 216 #address-cells = <1>; 217 #size-cells = <1>; 218 compatible = "jedec,spi-nor"; 219 reg = <0>; 220 spi-max-frequency = <20000000>; 221 222 partitions { 223 compatible = "fixed-partitions"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 227 partition@0 { 228 label = "secure-firmware"; 229 reg = <0x0 0x20000>; 230 }; 231 232 partition@20000 { 233 label = "a53-firmware"; 234 reg = <0x20000 0x160000>; 235 }; 236 237 partition@180000 { 238 label = "u-boot-env"; 239 reg = <0x180000 0x10000>; 240 }; 241 242 partition@190000 { 243 label = "Rescue system"; 244 reg = <0x190000 0x660000>; 245 }; 246 247 partition@7f0000 { 248 label = "dtb"; 249 reg = <0x7f0000 0x10000>; 250 }; 251 }; 252 }; 253 254 moxtet: moxtet@1 { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 compatible = "cznic,moxtet"; 258 reg = <1>; 259 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 260 spi-max-frequency = <10000000>; 261 spi-cpol; 262 spi-cpha; 263 interrupt-controller; 264 #interrupt-cells = <1>; 265 interrupt-parent = <&gpiosb>; 266 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 267 status = "okay"; 268 269 moxtet_sfp: gpio@0 { 270 compatible = "cznic,moxtet-gpio"; 271 gpio-controller; 272 #gpio-cells = <2>; 273 reg = <0>; 274 status = "disabled"; 275 }; 276 }; 277}; 278 279&usb2 { 280 status = "okay"; 281}; 282 283&comphy2 { 284 connector { 285 compatible = "usb-a-connector"; 286 phy-supply = <&exp_usb3_vbus>; 287 }; 288}; 289 290&usb3 { 291 status = "okay"; 292 phys = <&comphy2 0>; 293}; 294 295&mdio { 296 pinctrl-names = "default"; 297 pinctrl-0 = <&smi_pins>; 298 status = "okay"; 299 300 phy1: ethernet-phy@1 { 301 reg = <1>; 302 }; 303 304 /* switch nodes are enabled by U-Boot if modules are present */ 305 switch0@10 { 306 compatible = "marvell,mv88e6190"; 307 reg = <0x10>; 308 dsa,member = <0 0>; 309 interrupt-parent = <&moxtet>; 310 interrupts = <MOXTET_IRQ_PERIDOT(0)>; 311 status = "disabled"; 312 313 mdio { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 317 switch0phy1: switch0phy1@1 { 318 reg = <0x1>; 319 }; 320 321 switch0phy2: switch0phy2@2 { 322 reg = <0x2>; 323 }; 324 325 switch0phy3: switch0phy3@3 { 326 reg = <0x3>; 327 }; 328 329 switch0phy4: switch0phy4@4 { 330 reg = <0x4>; 331 }; 332 333 switch0phy5: switch0phy5@5 { 334 reg = <0x5>; 335 }; 336 337 switch0phy6: switch0phy6@6 { 338 reg = <0x6>; 339 }; 340 341 switch0phy7: switch0phy7@7 { 342 reg = <0x7>; 343 }; 344 345 switch0phy8: switch0phy8@8 { 346 reg = <0x8>; 347 }; 348 }; 349 350 ports { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 354 port@1 { 355 reg = <0x1>; 356 label = "lan1"; 357 phy-handle = <&switch0phy1>; 358 }; 359 360 port@2 { 361 reg = <0x2>; 362 label = "lan2"; 363 phy-handle = <&switch0phy2>; 364 }; 365 366 port@3 { 367 reg = <0x3>; 368 label = "lan3"; 369 phy-handle = <&switch0phy3>; 370 }; 371 372 port@4 { 373 reg = <0x4>; 374 label = "lan4"; 375 phy-handle = <&switch0phy4>; 376 }; 377 378 port@5 { 379 reg = <0x5>; 380 label = "lan5"; 381 phy-handle = <&switch0phy5>; 382 }; 383 384 port@6 { 385 reg = <0x6>; 386 label = "lan6"; 387 phy-handle = <&switch0phy6>; 388 }; 389 390 port@7 { 391 reg = <0x7>; 392 label = "lan7"; 393 phy-handle = <&switch0phy7>; 394 }; 395 396 port@8 { 397 reg = <0x8>; 398 label = "lan8"; 399 phy-handle = <&switch0phy8>; 400 }; 401 402 port@9 { 403 reg = <0x9>; 404 label = "cpu"; 405 ethernet = <ð1>; 406 phy-mode = "2500base-x"; 407 managed = "in-band-status"; 408 }; 409 410 switch0port10: port@a { 411 reg = <0xa>; 412 label = "dsa"; 413 phy-mode = "2500base-x"; 414 managed = "in-band-status"; 415 link = <&switch1port9 &switch2port9>; 416 status = "disabled"; 417 }; 418 419 port-sfp@a { 420 reg = <0xa>; 421 label = "sfp"; 422 sfp = <&sfp>; 423 phy-mode = "sgmii"; 424 managed = "in-band-status"; 425 status = "disabled"; 426 }; 427 }; 428 }; 429 430 switch0@2 { 431 compatible = "marvell,mv88e6085"; 432 reg = <0x2>; 433 dsa,member = <0 0>; 434 interrupt-parent = <&moxtet>; 435 interrupts = <MOXTET_IRQ_TOPAZ>; 436 status = "disabled"; 437 438 mdio { 439 #address-cells = <1>; 440 #size-cells = <0>; 441 442 switch0phy1_topaz: switch0phy1@11 { 443 reg = <0x11>; 444 }; 445 446 switch0phy2_topaz: switch0phy2@12 { 447 reg = <0x12>; 448 }; 449 450 switch0phy3_topaz: switch0phy3@13 { 451 reg = <0x13>; 452 }; 453 454 switch0phy4_topaz: switch0phy4@14 { 455 reg = <0x14>; 456 }; 457 }; 458 459 ports { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 463 port@1 { 464 reg = <0x1>; 465 label = "lan1"; 466 phy-handle = <&switch0phy1_topaz>; 467 }; 468 469 port@2 { 470 reg = <0x2>; 471 label = "lan2"; 472 phy-handle = <&switch0phy2_topaz>; 473 }; 474 475 port@3 { 476 reg = <0x3>; 477 label = "lan3"; 478 phy-handle = <&switch0phy3_topaz>; 479 }; 480 481 port@4 { 482 reg = <0x4>; 483 label = "lan4"; 484 phy-handle = <&switch0phy4_topaz>; 485 }; 486 487 port@5 { 488 reg = <0x5>; 489 label = "cpu"; 490 phy-mode = "2500base-x"; 491 managed = "in-band-status"; 492 ethernet = <ð1>; 493 }; 494 }; 495 }; 496 497 switch1@11 { 498 compatible = "marvell,mv88e6190"; 499 reg = <0x11>; 500 dsa,member = <0 1>; 501 interrupt-parent = <&moxtet>; 502 interrupts = <MOXTET_IRQ_PERIDOT(1)>; 503 status = "disabled"; 504 505 mdio { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 509 switch1phy1: switch1phy1@1 { 510 reg = <0x1>; 511 }; 512 513 switch1phy2: switch1phy2@2 { 514 reg = <0x2>; 515 }; 516 517 switch1phy3: switch1phy3@3 { 518 reg = <0x3>; 519 }; 520 521 switch1phy4: switch1phy4@4 { 522 reg = <0x4>; 523 }; 524 525 switch1phy5: switch1phy5@5 { 526 reg = <0x5>; 527 }; 528 529 switch1phy6: switch1phy6@6 { 530 reg = <0x6>; 531 }; 532 533 switch1phy7: switch1phy7@7 { 534 reg = <0x7>; 535 }; 536 537 switch1phy8: switch1phy8@8 { 538 reg = <0x8>; 539 }; 540 }; 541 542 ports { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 546 port@1 { 547 reg = <0x1>; 548 label = "lan9"; 549 phy-handle = <&switch1phy1>; 550 }; 551 552 port@2 { 553 reg = <0x2>; 554 label = "lan10"; 555 phy-handle = <&switch1phy2>; 556 }; 557 558 port@3 { 559 reg = <0x3>; 560 label = "lan11"; 561 phy-handle = <&switch1phy3>; 562 }; 563 564 port@4 { 565 reg = <0x4>; 566 label = "lan12"; 567 phy-handle = <&switch1phy4>; 568 }; 569 570 port@5 { 571 reg = <0x5>; 572 label = "lan13"; 573 phy-handle = <&switch1phy5>; 574 }; 575 576 port@6 { 577 reg = <0x6>; 578 label = "lan14"; 579 phy-handle = <&switch1phy6>; 580 }; 581 582 port@7 { 583 reg = <0x7>; 584 label = "lan15"; 585 phy-handle = <&switch1phy7>; 586 }; 587 588 port@8 { 589 reg = <0x8>; 590 label = "lan16"; 591 phy-handle = <&switch1phy8>; 592 }; 593 594 switch1port9: port@9 { 595 reg = <0x9>; 596 label = "dsa"; 597 phy-mode = "2500base-x"; 598 managed = "in-band-status"; 599 link = <&switch0port10>; 600 }; 601 602 switch1port10: port@a { 603 reg = <0xa>; 604 label = "dsa"; 605 phy-mode = "2500base-x"; 606 managed = "in-band-status"; 607 link = <&switch2port9>; 608 status = "disabled"; 609 }; 610 611 port-sfp@a { 612 reg = <0xa>; 613 label = "sfp"; 614 sfp = <&sfp>; 615 phy-mode = "sgmii"; 616 managed = "in-band-status"; 617 status = "disabled"; 618 }; 619 }; 620 }; 621 622 switch1@2 { 623 compatible = "marvell,mv88e6085"; 624 reg = <0x2>; 625 dsa,member = <0 1>; 626 interrupt-parent = <&moxtet>; 627 interrupts = <MOXTET_IRQ_TOPAZ>; 628 status = "disabled"; 629 630 mdio { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 634 switch1phy1_topaz: switch1phy1@11 { 635 reg = <0x11>; 636 }; 637 638 switch1phy2_topaz: switch1phy2@12 { 639 reg = <0x12>; 640 }; 641 642 switch1phy3_topaz: switch1phy3@13 { 643 reg = <0x13>; 644 }; 645 646 switch1phy4_topaz: switch1phy4@14 { 647 reg = <0x14>; 648 }; 649 }; 650 651 ports { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 655 port@1 { 656 reg = <0x1>; 657 label = "lan9"; 658 phy-handle = <&switch1phy1_topaz>; 659 }; 660 661 port@2 { 662 reg = <0x2>; 663 label = "lan10"; 664 phy-handle = <&switch1phy2_topaz>; 665 }; 666 667 port@3 { 668 reg = <0x3>; 669 label = "lan11"; 670 phy-handle = <&switch1phy3_topaz>; 671 }; 672 673 port@4 { 674 reg = <0x4>; 675 label = "lan12"; 676 phy-handle = <&switch1phy4_topaz>; 677 }; 678 679 port@5 { 680 reg = <0x5>; 681 label = "dsa"; 682 phy-mode = "2500base-x"; 683 managed = "in-band-status"; 684 link = <&switch0port10>; 685 }; 686 }; 687 }; 688 689 switch2@12 { 690 compatible = "marvell,mv88e6190"; 691 reg = <0x12>; 692 dsa,member = <0 2>; 693 interrupt-parent = <&moxtet>; 694 interrupts = <MOXTET_IRQ_PERIDOT(2)>; 695 status = "disabled"; 696 697 mdio { 698 #address-cells = <1>; 699 #size-cells = <0>; 700 701 switch2phy1: switch2phy1@1 { 702 reg = <0x1>; 703 }; 704 705 switch2phy2: switch2phy2@2 { 706 reg = <0x2>; 707 }; 708 709 switch2phy3: switch2phy3@3 { 710 reg = <0x3>; 711 }; 712 713 switch2phy4: switch2phy4@4 { 714 reg = <0x4>; 715 }; 716 717 switch2phy5: switch2phy5@5 { 718 reg = <0x5>; 719 }; 720 721 switch2phy6: switch2phy6@6 { 722 reg = <0x6>; 723 }; 724 725 switch2phy7: switch2phy7@7 { 726 reg = <0x7>; 727 }; 728 729 switch2phy8: switch2phy8@8 { 730 reg = <0x8>; 731 }; 732 }; 733 734 ports { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 738 port@1 { 739 reg = <0x1>; 740 label = "lan17"; 741 phy-handle = <&switch2phy1>; 742 }; 743 744 port@2 { 745 reg = <0x2>; 746 label = "lan18"; 747 phy-handle = <&switch2phy2>; 748 }; 749 750 port@3 { 751 reg = <0x3>; 752 label = "lan19"; 753 phy-handle = <&switch2phy3>; 754 }; 755 756 port@4 { 757 reg = <0x4>; 758 label = "lan20"; 759 phy-handle = <&switch2phy4>; 760 }; 761 762 port@5 { 763 reg = <0x5>; 764 label = "lan21"; 765 phy-handle = <&switch2phy5>; 766 }; 767 768 port@6 { 769 reg = <0x6>; 770 label = "lan22"; 771 phy-handle = <&switch2phy6>; 772 }; 773 774 port@7 { 775 reg = <0x7>; 776 label = "lan23"; 777 phy-handle = <&switch2phy7>; 778 }; 779 780 port@8 { 781 reg = <0x8>; 782 label = "lan24"; 783 phy-handle = <&switch2phy8>; 784 }; 785 786 switch2port9: port@9 { 787 reg = <0x9>; 788 label = "dsa"; 789 phy-mode = "2500base-x"; 790 managed = "in-band-status"; 791 link = <&switch1port10 &switch0port10>; 792 }; 793 794 port-sfp@a { 795 reg = <0xa>; 796 label = "sfp"; 797 sfp = <&sfp>; 798 phy-mode = "sgmii"; 799 managed = "in-band-status"; 800 status = "disabled"; 801 }; 802 }; 803 }; 804 805 switch2@2 { 806 compatible = "marvell,mv88e6085"; 807 reg = <0x2>; 808 dsa,member = <0 2>; 809 interrupt-parent = <&moxtet>; 810 interrupts = <MOXTET_IRQ_TOPAZ>; 811 status = "disabled"; 812 813 mdio { 814 #address-cells = <1>; 815 #size-cells = <0>; 816 817 switch2phy1_topaz: switch2phy1@11 { 818 reg = <0x11>; 819 }; 820 821 switch2phy2_topaz: switch2phy2@12 { 822 reg = <0x12>; 823 }; 824 825 switch2phy3_topaz: switch2phy3@13 { 826 reg = <0x13>; 827 }; 828 829 switch2phy4_topaz: switch2phy4@14 { 830 reg = <0x14>; 831 }; 832 }; 833 834 ports { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 838 port@1 { 839 reg = <0x1>; 840 label = "lan17"; 841 phy-handle = <&switch2phy1_topaz>; 842 }; 843 844 port@2 { 845 reg = <0x2>; 846 label = "lan18"; 847 phy-handle = <&switch2phy2_topaz>; 848 }; 849 850 port@3 { 851 reg = <0x3>; 852 label = "lan19"; 853 phy-handle = <&switch2phy3_topaz>; 854 }; 855 856 port@4 { 857 reg = <0x4>; 858 label = "lan20"; 859 phy-handle = <&switch2phy4_topaz>; 860 }; 861 862 port@5 { 863 reg = <0x5>; 864 label = "dsa"; 865 phy-mode = "2500base-x"; 866 managed = "in-band-status"; 867 link = <&switch1port10 &switch0port10>; 868 }; 869 }; 870 }; 871}; 872