1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek Behun <marek.behun@nic.cz>
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/bus/moxtet.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include "armada-372x.dtsi"
13
14/ {
15	model = "CZ.NIC Turris Mox Board";
16	compatible = "cznic,turris-mox", "marvell,armada3720",
17		     "marvell,armada3710";
18
19	aliases {
20		spi0 = &spi0;
21		ethernet1 = &eth1;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26	};
27
28	memory@0 {
29		device_type = "memory";
30		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31	};
32
33	leds {
34		compatible = "gpio-leds";
35		red {
36			label = "mox:red:activity";
37			gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
38			linux,default-trigger = "default-on";
39		};
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		reset {
46			label = "reset";
47			linux,code = <KEY_RESTART>;
48			gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
49			debounce-interval = <60>;
50		};
51	};
52
53	exp_usb3_vbus: usb3-vbus {
54		compatible = "regulator-fixed";
55		regulator-name = "usb3-vbus";
56		regulator-min-microvolt = <5000000>;
57		regulator-max-microvolt = <5000000>;
58		enable-active-high;
59		regulator-always-on;
60		gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
61	};
62
63	vsdc_reg: vsdc-reg {
64		compatible = "regulator-gpio";
65		regulator-name = "vsdc";
66		regulator-min-microvolt = <1800000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-boot-on;
69
70		gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
71		gpios-states = <0>;
72		states = <1800000 0x1
73			  3300000 0x0>;
74		enable-active-high;
75	};
76
77	vsdio_reg: vsdio-reg {
78		compatible = "regulator-gpio";
79		regulator-name = "vsdio";
80		regulator-min-microvolt = <1800000>;
81		regulator-max-microvolt = <3300000>;
82		regulator-boot-on;
83
84		gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
85		gpios-states = <0>;
86		states = <1800000 0x1
87			  3300000 0x0>;
88		enable-active-high;
89	};
90
91	sdhci1_pwrseq: sdhci1-pwrseq {
92		compatible = "mmc-pwrseq-simple";
93		reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
94		status = "okay";
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp+";
99		i2c-bus = <&i2c0>;
100		los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
101		tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
102		mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
103		tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
104		rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
105
106		/* enabled by U-Boot if SFP module is present */
107		status = "disabled";
108	};
109};
110
111&i2c0 {
112	pinctrl-names = "default";
113	pinctrl-0 = <&i2c1_pins>;
114	clock-frequency = <100000>;
115	status = "okay";
116
117	rtc@6f {
118		compatible = "microchip,mcp7940x";
119		reg = <0x6f>;
120	};
121};
122
123&pcie_reset_pins {
124	function = "gpio";
125};
126
127&pcie0 {
128	pinctrl-names = "default";
129	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
130	status = "okay";
131	max-link-speed = <2>;
132	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
133	phys = <&comphy1 0>;
134
135	/* enabled by U-Boot if PCIe module is present */
136	status = "disabled";
137};
138
139&uart0 {
140	status = "okay";
141};
142
143&eth0 {
144	pinctrl-names = "default";
145	pinctrl-0 = <&rgmii_pins>;
146	phy-mode = "rgmii-id";
147	phy = <&phy1>;
148	status = "okay";
149};
150
151&eth1 {
152	phy-mode = "2500base-x";
153	managed = "in-band-status";
154	phys = <&comphy0 1>;
155};
156
157&sdhci0 {
158	wp-inverted;
159	bus-width = <4>;
160	cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
161	vqmmc-supply = <&vsdc_reg>;
162	marvell,pad-type = "sd";
163	status = "okay";
164};
165
166&sdhci1 {
167	pinctrl-names = "default";
168	pinctrl-0 = <&sdio_pins>;
169	non-removable;
170	bus-width = <4>;
171	marvell,pad-type = "sd";
172	vqmmc-supply = <&vsdio_reg>;
173	mmc-pwrseq = <&sdhci1_pwrseq>;
174	status = "okay";
175};
176
177&spi0 {
178	status = "okay";
179	pinctrl-names = "default";
180	pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
181	assigned-clocks = <&nb_periph_clk 7>;
182	assigned-clock-parents = <&tbg 1>;
183	assigned-clock-rates = <20000000>;
184
185	spi-flash@0 {
186		#address-cells = <1>;
187		#size-cells = <1>;
188		compatible = "jedec,spi-nor";
189		reg = <0>;
190		spi-max-frequency = <20000000>;
191
192		partitions {
193			compatible = "fixed-partitions";
194			#address-cells = <1>;
195			#size-cells = <1>;
196
197			partition@0 {
198				label = "secure-firmware";
199				reg = <0x0 0x20000>;
200			};
201
202			partition@20000 {
203				label = "u-boot";
204				reg = <0x20000 0x160000>;
205			};
206
207			partition@180000 {
208				label = "u-boot-env";
209				reg = <0x180000 0x10000>;
210			};
211
212			partition@190000 {
213				label = "Rescue system";
214				reg = <0x190000 0x660000>;
215			};
216
217			partition@7f0000 {
218				label = "dtb";
219				reg = <0x7f0000 0x10000>;
220			};
221		};
222	};
223
224	moxtet: moxtet@1 {
225		#address-cells = <1>;
226		#size-cells = <0>;
227		compatible = "cznic,moxtet";
228		reg = <1>;
229		reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
230		spi-max-frequency = <10000000>;
231		spi-cpol;
232		spi-cpha;
233		interrupt-controller;
234		#interrupt-cells = <1>;
235		interrupt-parent = <&gpiosb>;
236		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
237		status = "okay";
238
239		moxtet_sfp: gpio@0 {
240			compatible = "cznic,moxtet-gpio";
241			gpio-controller;
242			#gpio-cells = <2>;
243			reg = <0>;
244			status = "disabled";
245		};
246	};
247};
248
249&usb2 {
250	status = "okay";
251};
252
253&comphy2 {
254	connector {
255		compatible = "usb-a-connector";
256		phy-supply = <&exp_usb3_vbus>;
257	};
258};
259
260&usb3 {
261	status = "okay";
262	phys = <&comphy2 0>;
263};
264
265&mdio {
266	pinctrl-names = "default";
267	pinctrl-0 = <&smi_pins>;
268	status = "okay";
269
270	phy1: ethernet-phy@1 {
271		reg = <1>;
272	};
273
274	/* switch nodes are enabled by U-Boot if modules are present */
275	switch0@10 {
276		compatible = "marvell,mv88e6190";
277		reg = <0x10 0>;
278		dsa,member = <0 0>;
279		interrupt-parent = <&moxtet>;
280		interrupts = <MOXTET_IRQ_PERIDOT(0)>;
281		status = "disabled";
282
283		mdio {
284			#address-cells = <1>;
285			#size-cells = <0>;
286
287			switch0phy1: switch0phy1@1 {
288				reg = <0x1>;
289			};
290
291			switch0phy2: switch0phy2@2 {
292				reg = <0x2>;
293			};
294
295			switch0phy3: switch0phy3@3 {
296				reg = <0x3>;
297			};
298
299			switch0phy4: switch0phy4@4 {
300				reg = <0x4>;
301			};
302
303			switch0phy5: switch0phy5@5 {
304				reg = <0x5>;
305			};
306
307			switch0phy6: switch0phy6@6 {
308				reg = <0x6>;
309			};
310
311			switch0phy7: switch0phy7@7 {
312				reg = <0x7>;
313			};
314
315			switch0phy8: switch0phy8@8 {
316				reg = <0x8>;
317			};
318		};
319
320		ports {
321			#address-cells = <1>;
322			#size-cells = <0>;
323
324			port@1 {
325				reg = <0x1>;
326				label = "lan1";
327				phy-handle = <&switch0phy1>;
328			};
329
330			port@2 {
331				reg = <0x2>;
332				label = "lan2";
333				phy-handle = <&switch0phy2>;
334			};
335
336			port@3 {
337				reg = <0x3>;
338				label = "lan3";
339				phy-handle = <&switch0phy3>;
340			};
341
342			port@4 {
343				reg = <0x4>;
344				label = "lan4";
345				phy-handle = <&switch0phy4>;
346			};
347
348			port@5 {
349				reg = <0x5>;
350				label = "lan5";
351				phy-handle = <&switch0phy5>;
352			};
353
354			port@6 {
355				reg = <0x6>;
356				label = "lan6";
357				phy-handle = <&switch0phy6>;
358			};
359
360			port@7 {
361				reg = <0x7>;
362				label = "lan7";
363				phy-handle = <&switch0phy7>;
364			};
365
366			port@8 {
367				reg = <0x8>;
368				label = "lan8";
369				phy-handle = <&switch0phy8>;
370			};
371
372			port@9 {
373				reg = <0x9>;
374				label = "cpu";
375				ethernet = <&eth1>;
376				phy-mode = "2500base-x";
377				managed = "in-band-status";
378			};
379
380			switch0port10: port@a {
381				reg = <0xa>;
382				label = "dsa";
383				phy-mode = "2500base-x";
384				managed = "in-band-status";
385				link = <&switch1port9 &switch2port9>;
386				status = "disabled";
387			};
388
389			port-sfp@a {
390				reg = <0xa>;
391				label = "sfp";
392				sfp = <&sfp>;
393				phy-mode = "sgmii";
394				managed = "in-band-status";
395				status = "disabled";
396			};
397		};
398	};
399
400	switch0@2 {
401		compatible = "marvell,mv88e6085";
402		reg = <0x2 0>;
403		dsa,member = <0 0>;
404		interrupt-parent = <&moxtet>;
405		interrupts = <MOXTET_IRQ_TOPAZ>;
406		status = "disabled";
407
408		mdio {
409			#address-cells = <1>;
410			#size-cells = <0>;
411
412			switch0phy1_topaz: switch0phy1@11 {
413				reg = <0x11>;
414			};
415
416			switch0phy2_topaz: switch0phy2@12 {
417				reg = <0x12>;
418			};
419
420			switch0phy3_topaz: switch0phy3@13 {
421				reg = <0x13>;
422			};
423
424			switch0phy4_topaz: switch0phy4@14 {
425				reg = <0x14>;
426			};
427		};
428
429		ports {
430			#address-cells = <1>;
431			#size-cells = <0>;
432
433			port@1 {
434				reg = <0x1>;
435				label = "lan1";
436				phy-handle = <&switch0phy1_topaz>;
437			};
438
439			port@2 {
440				reg = <0x2>;
441				label = "lan2";
442				phy-handle = <&switch0phy2_topaz>;
443			};
444
445			port@3 {
446				reg = <0x3>;
447				label = "lan3";
448				phy-handle = <&switch0phy3_topaz>;
449			};
450
451			port@4 {
452				reg = <0x4>;
453				label = "lan4";
454				phy-handle = <&switch0phy4_topaz>;
455			};
456
457			port@5 {
458				reg = <0x5>;
459				label = "cpu";
460				phy-mode = "2500base-x";
461				managed = "in-band-status";
462				ethernet = <&eth1>;
463			};
464		};
465	};
466
467	switch1@11 {
468		compatible = "marvell,mv88e6190";
469		reg = <0x11 0>;
470		dsa,member = <0 1>;
471		interrupt-parent = <&moxtet>;
472		interrupts = <MOXTET_IRQ_PERIDOT(1)>;
473		status = "disabled";
474
475		mdio {
476			#address-cells = <1>;
477			#size-cells = <0>;
478
479			switch1phy1: switch1phy1@1 {
480				reg = <0x1>;
481			};
482
483			switch1phy2: switch1phy2@2 {
484				reg = <0x2>;
485			};
486
487			switch1phy3: switch1phy3@3 {
488				reg = <0x3>;
489			};
490
491			switch1phy4: switch1phy4@4 {
492				reg = <0x4>;
493			};
494
495			switch1phy5: switch1phy5@5 {
496				reg = <0x5>;
497			};
498
499			switch1phy6: switch1phy6@6 {
500				reg = <0x6>;
501			};
502
503			switch1phy7: switch1phy7@7 {
504				reg = <0x7>;
505			};
506
507			switch1phy8: switch1phy8@8 {
508				reg = <0x8>;
509			};
510		};
511
512		ports {
513			#address-cells = <1>;
514			#size-cells = <0>;
515
516			port@1 {
517				reg = <0x1>;
518				label = "lan9";
519				phy-handle = <&switch1phy1>;
520			};
521
522			port@2 {
523				reg = <0x2>;
524				label = "lan10";
525				phy-handle = <&switch1phy2>;
526			};
527
528			port@3 {
529				reg = <0x3>;
530				label = "lan11";
531				phy-handle = <&switch1phy3>;
532			};
533
534			port@4 {
535				reg = <0x4>;
536				label = "lan12";
537				phy-handle = <&switch1phy4>;
538			};
539
540			port@5 {
541				reg = <0x5>;
542				label = "lan13";
543				phy-handle = <&switch1phy5>;
544			};
545
546			port@6 {
547				reg = <0x6>;
548				label = "lan14";
549				phy-handle = <&switch1phy6>;
550			};
551
552			port@7 {
553				reg = <0x7>;
554				label = "lan15";
555				phy-handle = <&switch1phy7>;
556			};
557
558			port@8 {
559				reg = <0x8>;
560				label = "lan16";
561				phy-handle = <&switch1phy8>;
562			};
563
564			switch1port9: port@9 {
565				reg = <0x9>;
566				label = "dsa";
567				phy-mode = "2500base-x";
568				managed = "in-band-status";
569				link = <&switch0port10>;
570			};
571
572			switch1port10: port@a {
573				reg = <0xa>;
574				label = "dsa";
575				phy-mode = "2500base-x";
576				managed = "in-band-status";
577				link = <&switch2port9>;
578				status = "disabled";
579			};
580
581			port-sfp@a {
582				reg = <0xa>;
583				label = "sfp";
584				sfp = <&sfp>;
585				phy-mode = "sgmii";
586				managed = "in-band-status";
587				status = "disabled";
588			};
589		};
590	};
591
592	switch1@2 {
593		compatible = "marvell,mv88e6085";
594		reg = <0x2 0>;
595		dsa,member = <0 1>;
596		interrupt-parent = <&moxtet>;
597		interrupts = <MOXTET_IRQ_TOPAZ>;
598		status = "disabled";
599
600		mdio {
601			#address-cells = <1>;
602			#size-cells = <0>;
603
604			switch1phy1_topaz: switch1phy1@11 {
605				reg = <0x11>;
606			};
607
608			switch1phy2_topaz: switch1phy2@12 {
609				reg = <0x12>;
610			};
611
612			switch1phy3_topaz: switch1phy3@13 {
613				reg = <0x13>;
614			};
615
616			switch1phy4_topaz: switch1phy4@14 {
617				reg = <0x14>;
618			};
619		};
620
621		ports {
622			#address-cells = <1>;
623			#size-cells = <0>;
624
625			port@1 {
626				reg = <0x1>;
627				label = "lan9";
628				phy-handle = <&switch1phy1_topaz>;
629			};
630
631			port@2 {
632				reg = <0x2>;
633				label = "lan10";
634				phy-handle = <&switch1phy2_topaz>;
635			};
636
637			port@3 {
638				reg = <0x3>;
639				label = "lan11";
640				phy-handle = <&switch1phy3_topaz>;
641			};
642
643			port@4 {
644				reg = <0x4>;
645				label = "lan12";
646				phy-handle = <&switch1phy4_topaz>;
647			};
648
649			port@5 {
650				reg = <0x5>;
651				label = "dsa";
652				phy-mode = "2500base-x";
653				managed = "in-band-status";
654				link = <&switch0port10>;
655			};
656		};
657	};
658
659	switch2@12 {
660		compatible = "marvell,mv88e6190";
661		reg = <0x12 0>;
662		dsa,member = <0 2>;
663		interrupt-parent = <&moxtet>;
664		interrupts = <MOXTET_IRQ_PERIDOT(2)>;
665		status = "disabled";
666
667		mdio {
668			#address-cells = <1>;
669			#size-cells = <0>;
670
671			switch2phy1: switch2phy1@1 {
672				reg = <0x1>;
673			};
674
675			switch2phy2: switch2phy2@2 {
676				reg = <0x2>;
677			};
678
679			switch2phy3: switch2phy3@3 {
680				reg = <0x3>;
681			};
682
683			switch2phy4: switch2phy4@4 {
684				reg = <0x4>;
685			};
686
687			switch2phy5: switch2phy5@5 {
688				reg = <0x5>;
689			};
690
691			switch2phy6: switch2phy6@6 {
692				reg = <0x6>;
693			};
694
695			switch2phy7: switch2phy7@7 {
696				reg = <0x7>;
697			};
698
699			switch2phy8: switch2phy8@8 {
700				reg = <0x8>;
701			};
702		};
703
704		ports {
705			#address-cells = <1>;
706			#size-cells = <0>;
707
708			port@1 {
709				reg = <0x1>;
710				label = "lan17";
711				phy-handle = <&switch2phy1>;
712			};
713
714			port@2 {
715				reg = <0x2>;
716				label = "lan18";
717				phy-handle = <&switch2phy2>;
718			};
719
720			port@3 {
721				reg = <0x3>;
722				label = "lan19";
723				phy-handle = <&switch2phy3>;
724			};
725
726			port@4 {
727				reg = <0x4>;
728				label = "lan20";
729				phy-handle = <&switch2phy4>;
730			};
731
732			port@5 {
733				reg = <0x5>;
734				label = "lan21";
735				phy-handle = <&switch2phy5>;
736			};
737
738			port@6 {
739				reg = <0x6>;
740				label = "lan22";
741				phy-handle = <&switch2phy6>;
742			};
743
744			port@7 {
745				reg = <0x7>;
746				label = "lan23";
747				phy-handle = <&switch2phy7>;
748			};
749
750			port@8 {
751				reg = <0x8>;
752				label = "lan24";
753				phy-handle = <&switch2phy8>;
754			};
755
756			switch2port9: port@9 {
757				reg = <0x9>;
758				label = "dsa";
759				phy-mode = "2500base-x";
760				managed = "in-band-status";
761				link = <&switch1port10 &switch0port10>;
762			};
763
764			port-sfp@a {
765				reg = <0xa>;
766				label = "sfp";
767				sfp = <&sfp>;
768				phy-mode = "sgmii";
769				managed = "in-band-status";
770				status = "disabled";
771			};
772		};
773	};
774
775	switch2@2 {
776		compatible = "marvell,mv88e6085";
777		reg = <0x2 0>;
778		dsa,member = <0 2>;
779		interrupt-parent = <&moxtet>;
780		interrupts = <MOXTET_IRQ_TOPAZ>;
781		status = "disabled";
782
783		mdio {
784			#address-cells = <1>;
785			#size-cells = <0>;
786
787			switch2phy1_topaz: switch2phy1@11 {
788				reg = <0x11>;
789			};
790
791			switch2phy2_topaz: switch2phy2@12 {
792				reg = <0x12>;
793			};
794
795			switch2phy3_topaz: switch2phy3@13 {
796				reg = <0x13>;
797			};
798
799			switch2phy4_topaz: switch2phy4@14 {
800				reg = <0x14>;
801			};
802		};
803
804		ports {
805			#address-cells = <1>;
806			#size-cells = <0>;
807
808			port@1 {
809				reg = <0x1>;
810				label = "lan17";
811				phy-handle = <&switch2phy1_topaz>;
812			};
813
814			port@2 {
815				reg = <0x2>;
816				label = "lan18";
817				phy-handle = <&switch2phy2_topaz>;
818			};
819
820			port@3 {
821				reg = <0x3>;
822				label = "lan19";
823				phy-handle = <&switch2phy3_topaz>;
824			};
825
826			port@4 {
827				reg = <0x4>;
828				label = "lan20";
829				phy-handle = <&switch2phy4_topaz>;
830			};
831
832			port@5 {
833				reg = <0x5>;
834				label = "dsa";
835				phy-mode = "2500base-x";
836				managed = "in-band-status";
837				link = <&switch1port10 &switch0port10>;
838			};
839		};
840	};
841};
842