1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for CZ.NIC Turris Mox Board 4 * 2019 by Marek Behún <kabel@kernel.org> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/bus/moxtet.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include "armada-372x.dtsi" 13 14/ { 15 model = "CZ.NIC Turris Mox Board"; 16 compatible = "cznic,turris-mox", "marvell,armada3720", 17 "marvell,armada3710"; 18 19 aliases { 20 spi0 = &spi0; 21 ethernet0 = ð0; 22 ethernet1 = ð1; 23 mmc0 = &sdhci0; 24 mmc1 = &sdhci1; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 memory@0 { 32 device_type = "memory"; 33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 34 }; 35 36 leds { 37 compatible = "gpio-leds"; 38 red { 39 label = "mox:red:activity"; 40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 41 linux,default-trigger = "default-on"; 42 }; 43 }; 44 45 gpio-keys { 46 compatible = "gpio-keys"; 47 48 reset { 49 label = "reset"; 50 linux,code = <KEY_RESTART>; 51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 52 debounce-interval = <60>; 53 }; 54 }; 55 56 exp_usb3_vbus: usb3-vbus { 57 compatible = "regulator-fixed"; 58 regulator-name = "usb3-vbus"; 59 regulator-min-microvolt = <5000000>; 60 regulator-max-microvolt = <5000000>; 61 enable-active-high; 62 regulator-always-on; 63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 64 }; 65 66 vsdc_reg: vsdc-reg { 67 compatible = "regulator-gpio"; 68 regulator-name = "vsdc"; 69 regulator-min-microvolt = <1800000>; 70 regulator-max-microvolt = <3300000>; 71 regulator-boot-on; 72 73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 74 gpios-states = <0>; 75 states = <1800000 0x1 76 3300000 0x0>; 77 enable-active-high; 78 }; 79 80 vsdio_reg: vsdio-reg { 81 compatible = "regulator-gpio"; 82 regulator-name = "vsdio"; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 88 gpios-states = <0>; 89 states = <1800000 0x1 90 3300000 0x0>; 91 enable-active-high; 92 }; 93 94 sdhci1_pwrseq: sdhci1-pwrseq { 95 compatible = "mmc-pwrseq-simple"; 96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 97 status = "okay"; 98 }; 99 100 sfp: sfp { 101 compatible = "sff,sfp"; 102 i2c-bus = <&i2c0>; 103 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 104 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 105 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 106 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 107 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 108 maximum-power-milliwatt = <3000>; 109 110 /* enabled by U-Boot if SFP module is present */ 111 status = "disabled"; 112 }; 113 114 firmware { 115 armada-3700-rwtm { 116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; 117 }; 118 }; 119}; 120 121&i2c0 { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&i2c1_pins>; 124 clock-frequency = <100000>; 125 /delete-property/ mrvl,i2c-fast-mode; 126 status = "okay"; 127 128 rtc@6f { 129 compatible = "microchip,mcp7940x"; 130 reg = <0x6f>; 131 }; 132}; 133 134&pcie0 { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 137 status = "okay"; 138 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 139 /* 140 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property 141 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and 142 * 2 size cells and also expects that the second range starts at 16 MB offset. If these 143 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address 144 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window 145 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. 146 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in 147 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): 148 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 149 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf 150 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 151 */ 152 #address-cells = <3>; 153 #size-cells = <2>; 154 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ 155 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ 156 157 /* enabled by U-Boot if PCIe module is present */ 158 status = "disabled"; 159}; 160 161&uart0 { 162 status = "okay"; 163}; 164 165ð0 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&rgmii_pins>; 168 phy-mode = "rgmii-id"; 169 phy-handle = <&phy1>; 170 status = "okay"; 171}; 172 173ð1 { 174 phy-mode = "2500base-x"; 175 managed = "in-band-status"; 176 phys = <&comphy0 1>; 177}; 178 179&sdhci0 { 180 wp-inverted; 181 bus-width = <4>; 182 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 183 vqmmc-supply = <&vsdc_reg>; 184 marvell,pad-type = "sd"; 185 status = "okay"; 186}; 187 188&sdhci1 { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&sdio_pins>; 191 non-removable; 192 bus-width = <4>; 193 marvell,pad-type = "sd"; 194 vqmmc-supply = <&vsdio_reg>; 195 mmc-pwrseq = <&sdhci1_pwrseq>; 196 /* forbid SDR104 for FCC purposes */ 197 sdhci-caps-mask = <0x2 0x0>; 198 status = "okay"; 199}; 200 201&spi0 { 202 status = "okay"; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 205 assigned-clocks = <&nb_periph_clk 7>; 206 assigned-clock-parents = <&tbg 1>; 207 assigned-clock-rates = <20000000>; 208 209 spi-flash@0 { 210 #address-cells = <1>; 211 #size-cells = <1>; 212 compatible = "jedec,spi-nor"; 213 reg = <0>; 214 spi-max-frequency = <20000000>; 215 216 partitions { 217 compatible = "fixed-partitions"; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 221 partition@0 { 222 label = "secure-firmware"; 223 reg = <0x0 0x20000>; 224 }; 225 226 partition@20000 { 227 label = "a53-firmware"; 228 reg = <0x20000 0x160000>; 229 }; 230 231 partition@180000 { 232 label = "u-boot-env"; 233 reg = <0x180000 0x10000>; 234 }; 235 236 partition@190000 { 237 label = "Rescue system"; 238 reg = <0x190000 0x660000>; 239 }; 240 241 partition@7f0000 { 242 label = "dtb"; 243 reg = <0x7f0000 0x10000>; 244 }; 245 }; 246 }; 247 248 moxtet: moxtet@1 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "cznic,moxtet"; 252 reg = <1>; 253 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 254 spi-max-frequency = <10000000>; 255 spi-cpol; 256 spi-cpha; 257 interrupt-controller; 258 #interrupt-cells = <1>; 259 interrupt-parent = <&gpiosb>; 260 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 261 status = "okay"; 262 263 moxtet_sfp: gpio@0 { 264 compatible = "cznic,moxtet-gpio"; 265 gpio-controller; 266 #gpio-cells = <2>; 267 reg = <0>; 268 status = "disabled"; 269 }; 270 }; 271}; 272 273&usb2 { 274 status = "okay"; 275}; 276 277&comphy2 { 278 connector { 279 compatible = "usb-a-connector"; 280 phy-supply = <&exp_usb3_vbus>; 281 }; 282}; 283 284&usb3 { 285 status = "okay"; 286 phys = <&comphy2 0>; 287}; 288 289&mdio { 290 pinctrl-names = "default"; 291 pinctrl-0 = <&smi_pins>; 292 status = "okay"; 293 294 phy1: ethernet-phy@1 { 295 reg = <1>; 296 }; 297 298 /* switch nodes are enabled by U-Boot if modules are present */ 299 switch0@10 { 300 compatible = "marvell,mv88e6190"; 301 reg = <0x10 0>; 302 dsa,member = <0 0>; 303 interrupt-parent = <&moxtet>; 304 interrupts = <MOXTET_IRQ_PERIDOT(0)>; 305 status = "disabled"; 306 307 mdio { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 311 switch0phy1: switch0phy1@1 { 312 reg = <0x1>; 313 }; 314 315 switch0phy2: switch0phy2@2 { 316 reg = <0x2>; 317 }; 318 319 switch0phy3: switch0phy3@3 { 320 reg = <0x3>; 321 }; 322 323 switch0phy4: switch0phy4@4 { 324 reg = <0x4>; 325 }; 326 327 switch0phy5: switch0phy5@5 { 328 reg = <0x5>; 329 }; 330 331 switch0phy6: switch0phy6@6 { 332 reg = <0x6>; 333 }; 334 335 switch0phy7: switch0phy7@7 { 336 reg = <0x7>; 337 }; 338 339 switch0phy8: switch0phy8@8 { 340 reg = <0x8>; 341 }; 342 }; 343 344 ports { 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 port@1 { 349 reg = <0x1>; 350 label = "lan1"; 351 phy-handle = <&switch0phy1>; 352 }; 353 354 port@2 { 355 reg = <0x2>; 356 label = "lan2"; 357 phy-handle = <&switch0phy2>; 358 }; 359 360 port@3 { 361 reg = <0x3>; 362 label = "lan3"; 363 phy-handle = <&switch0phy3>; 364 }; 365 366 port@4 { 367 reg = <0x4>; 368 label = "lan4"; 369 phy-handle = <&switch0phy4>; 370 }; 371 372 port@5 { 373 reg = <0x5>; 374 label = "lan5"; 375 phy-handle = <&switch0phy5>; 376 }; 377 378 port@6 { 379 reg = <0x6>; 380 label = "lan6"; 381 phy-handle = <&switch0phy6>; 382 }; 383 384 port@7 { 385 reg = <0x7>; 386 label = "lan7"; 387 phy-handle = <&switch0phy7>; 388 }; 389 390 port@8 { 391 reg = <0x8>; 392 label = "lan8"; 393 phy-handle = <&switch0phy8>; 394 }; 395 396 port@9 { 397 reg = <0x9>; 398 label = "cpu"; 399 ethernet = <ð1>; 400 phy-mode = "2500base-x"; 401 managed = "in-band-status"; 402 }; 403 404 switch0port10: port@a { 405 reg = <0xa>; 406 label = "dsa"; 407 phy-mode = "2500base-x"; 408 managed = "in-band-status"; 409 link = <&switch1port9 &switch2port9>; 410 status = "disabled"; 411 }; 412 413 port-sfp@a { 414 reg = <0xa>; 415 label = "sfp"; 416 sfp = <&sfp>; 417 phy-mode = "sgmii"; 418 managed = "in-band-status"; 419 status = "disabled"; 420 }; 421 }; 422 }; 423 424 switch0@2 { 425 compatible = "marvell,mv88e6085"; 426 reg = <0x2 0>; 427 dsa,member = <0 0>; 428 interrupt-parent = <&moxtet>; 429 interrupts = <MOXTET_IRQ_TOPAZ>; 430 status = "disabled"; 431 432 mdio { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 switch0phy1_topaz: switch0phy1@11 { 437 reg = <0x11>; 438 }; 439 440 switch0phy2_topaz: switch0phy2@12 { 441 reg = <0x12>; 442 }; 443 444 switch0phy3_topaz: switch0phy3@13 { 445 reg = <0x13>; 446 }; 447 448 switch0phy4_topaz: switch0phy4@14 { 449 reg = <0x14>; 450 }; 451 }; 452 453 ports { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 457 port@1 { 458 reg = <0x1>; 459 label = "lan1"; 460 phy-handle = <&switch0phy1_topaz>; 461 }; 462 463 port@2 { 464 reg = <0x2>; 465 label = "lan2"; 466 phy-handle = <&switch0phy2_topaz>; 467 }; 468 469 port@3 { 470 reg = <0x3>; 471 label = "lan3"; 472 phy-handle = <&switch0phy3_topaz>; 473 }; 474 475 port@4 { 476 reg = <0x4>; 477 label = "lan4"; 478 phy-handle = <&switch0phy4_topaz>; 479 }; 480 481 port@5 { 482 reg = <0x5>; 483 label = "cpu"; 484 phy-mode = "2500base-x"; 485 managed = "in-band-status"; 486 ethernet = <ð1>; 487 }; 488 }; 489 }; 490 491 switch1@11 { 492 compatible = "marvell,mv88e6190"; 493 reg = <0x11 0>; 494 dsa,member = <0 1>; 495 interrupt-parent = <&moxtet>; 496 interrupts = <MOXTET_IRQ_PERIDOT(1)>; 497 status = "disabled"; 498 499 mdio { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 503 switch1phy1: switch1phy1@1 { 504 reg = <0x1>; 505 }; 506 507 switch1phy2: switch1phy2@2 { 508 reg = <0x2>; 509 }; 510 511 switch1phy3: switch1phy3@3 { 512 reg = <0x3>; 513 }; 514 515 switch1phy4: switch1phy4@4 { 516 reg = <0x4>; 517 }; 518 519 switch1phy5: switch1phy5@5 { 520 reg = <0x5>; 521 }; 522 523 switch1phy6: switch1phy6@6 { 524 reg = <0x6>; 525 }; 526 527 switch1phy7: switch1phy7@7 { 528 reg = <0x7>; 529 }; 530 531 switch1phy8: switch1phy8@8 { 532 reg = <0x8>; 533 }; 534 }; 535 536 ports { 537 #address-cells = <1>; 538 #size-cells = <0>; 539 540 port@1 { 541 reg = <0x1>; 542 label = "lan9"; 543 phy-handle = <&switch1phy1>; 544 }; 545 546 port@2 { 547 reg = <0x2>; 548 label = "lan10"; 549 phy-handle = <&switch1phy2>; 550 }; 551 552 port@3 { 553 reg = <0x3>; 554 label = "lan11"; 555 phy-handle = <&switch1phy3>; 556 }; 557 558 port@4 { 559 reg = <0x4>; 560 label = "lan12"; 561 phy-handle = <&switch1phy4>; 562 }; 563 564 port@5 { 565 reg = <0x5>; 566 label = "lan13"; 567 phy-handle = <&switch1phy5>; 568 }; 569 570 port@6 { 571 reg = <0x6>; 572 label = "lan14"; 573 phy-handle = <&switch1phy6>; 574 }; 575 576 port@7 { 577 reg = <0x7>; 578 label = "lan15"; 579 phy-handle = <&switch1phy7>; 580 }; 581 582 port@8 { 583 reg = <0x8>; 584 label = "lan16"; 585 phy-handle = <&switch1phy8>; 586 }; 587 588 switch1port9: port@9 { 589 reg = <0x9>; 590 label = "dsa"; 591 phy-mode = "2500base-x"; 592 managed = "in-band-status"; 593 link = <&switch0port10>; 594 }; 595 596 switch1port10: port@a { 597 reg = <0xa>; 598 label = "dsa"; 599 phy-mode = "2500base-x"; 600 managed = "in-band-status"; 601 link = <&switch2port9>; 602 status = "disabled"; 603 }; 604 605 port-sfp@a { 606 reg = <0xa>; 607 label = "sfp"; 608 sfp = <&sfp>; 609 phy-mode = "sgmii"; 610 managed = "in-band-status"; 611 status = "disabled"; 612 }; 613 }; 614 }; 615 616 switch1@2 { 617 compatible = "marvell,mv88e6085"; 618 reg = <0x2 0>; 619 dsa,member = <0 1>; 620 interrupt-parent = <&moxtet>; 621 interrupts = <MOXTET_IRQ_TOPAZ>; 622 status = "disabled"; 623 624 mdio { 625 #address-cells = <1>; 626 #size-cells = <0>; 627 628 switch1phy1_topaz: switch1phy1@11 { 629 reg = <0x11>; 630 }; 631 632 switch1phy2_topaz: switch1phy2@12 { 633 reg = <0x12>; 634 }; 635 636 switch1phy3_topaz: switch1phy3@13 { 637 reg = <0x13>; 638 }; 639 640 switch1phy4_topaz: switch1phy4@14 { 641 reg = <0x14>; 642 }; 643 }; 644 645 ports { 646 #address-cells = <1>; 647 #size-cells = <0>; 648 649 port@1 { 650 reg = <0x1>; 651 label = "lan9"; 652 phy-handle = <&switch1phy1_topaz>; 653 }; 654 655 port@2 { 656 reg = <0x2>; 657 label = "lan10"; 658 phy-handle = <&switch1phy2_topaz>; 659 }; 660 661 port@3 { 662 reg = <0x3>; 663 label = "lan11"; 664 phy-handle = <&switch1phy3_topaz>; 665 }; 666 667 port@4 { 668 reg = <0x4>; 669 label = "lan12"; 670 phy-handle = <&switch1phy4_topaz>; 671 }; 672 673 port@5 { 674 reg = <0x5>; 675 label = "dsa"; 676 phy-mode = "2500base-x"; 677 managed = "in-band-status"; 678 link = <&switch0port10>; 679 }; 680 }; 681 }; 682 683 switch2@12 { 684 compatible = "marvell,mv88e6190"; 685 reg = <0x12 0>; 686 dsa,member = <0 2>; 687 interrupt-parent = <&moxtet>; 688 interrupts = <MOXTET_IRQ_PERIDOT(2)>; 689 status = "disabled"; 690 691 mdio { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 695 switch2phy1: switch2phy1@1 { 696 reg = <0x1>; 697 }; 698 699 switch2phy2: switch2phy2@2 { 700 reg = <0x2>; 701 }; 702 703 switch2phy3: switch2phy3@3 { 704 reg = <0x3>; 705 }; 706 707 switch2phy4: switch2phy4@4 { 708 reg = <0x4>; 709 }; 710 711 switch2phy5: switch2phy5@5 { 712 reg = <0x5>; 713 }; 714 715 switch2phy6: switch2phy6@6 { 716 reg = <0x6>; 717 }; 718 719 switch2phy7: switch2phy7@7 { 720 reg = <0x7>; 721 }; 722 723 switch2phy8: switch2phy8@8 { 724 reg = <0x8>; 725 }; 726 }; 727 728 ports { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 732 port@1 { 733 reg = <0x1>; 734 label = "lan17"; 735 phy-handle = <&switch2phy1>; 736 }; 737 738 port@2 { 739 reg = <0x2>; 740 label = "lan18"; 741 phy-handle = <&switch2phy2>; 742 }; 743 744 port@3 { 745 reg = <0x3>; 746 label = "lan19"; 747 phy-handle = <&switch2phy3>; 748 }; 749 750 port@4 { 751 reg = <0x4>; 752 label = "lan20"; 753 phy-handle = <&switch2phy4>; 754 }; 755 756 port@5 { 757 reg = <0x5>; 758 label = "lan21"; 759 phy-handle = <&switch2phy5>; 760 }; 761 762 port@6 { 763 reg = <0x6>; 764 label = "lan22"; 765 phy-handle = <&switch2phy6>; 766 }; 767 768 port@7 { 769 reg = <0x7>; 770 label = "lan23"; 771 phy-handle = <&switch2phy7>; 772 }; 773 774 port@8 { 775 reg = <0x8>; 776 label = "lan24"; 777 phy-handle = <&switch2phy8>; 778 }; 779 780 switch2port9: port@9 { 781 reg = <0x9>; 782 label = "dsa"; 783 phy-mode = "2500base-x"; 784 managed = "in-band-status"; 785 link = <&switch1port10 &switch0port10>; 786 }; 787 788 port-sfp@a { 789 reg = <0xa>; 790 label = "sfp"; 791 sfp = <&sfp>; 792 phy-mode = "sgmii"; 793 managed = "in-band-status"; 794 status = "disabled"; 795 }; 796 }; 797 }; 798 799 switch2@2 { 800 compatible = "marvell,mv88e6085"; 801 reg = <0x2 0>; 802 dsa,member = <0 2>; 803 interrupt-parent = <&moxtet>; 804 interrupts = <MOXTET_IRQ_TOPAZ>; 805 status = "disabled"; 806 807 mdio { 808 #address-cells = <1>; 809 #size-cells = <0>; 810 811 switch2phy1_topaz: switch2phy1@11 { 812 reg = <0x11>; 813 }; 814 815 switch2phy2_topaz: switch2phy2@12 { 816 reg = <0x12>; 817 }; 818 819 switch2phy3_topaz: switch2phy3@13 { 820 reg = <0x13>; 821 }; 822 823 switch2phy4_topaz: switch2phy4@14 { 824 reg = <0x14>; 825 }; 826 }; 827 828 ports { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 port@1 { 833 reg = <0x1>; 834 label = "lan17"; 835 phy-handle = <&switch2phy1_topaz>; 836 }; 837 838 port@2 { 839 reg = <0x2>; 840 label = "lan18"; 841 phy-handle = <&switch2phy2_topaz>; 842 }; 843 844 port@3 { 845 reg = <0x3>; 846 label = "lan19"; 847 phy-handle = <&switch2phy3_topaz>; 848 }; 849 850 port@4 { 851 reg = <0x4>; 852 label = "lan20"; 853 phy-handle = <&switch2phy4_topaz>; 854 }; 855 856 port@5 { 857 reg = <0x5>; 858 label = "dsa"; 859 phy-mode = "2500base-x"; 860 managed = "in-band-status"; 861 link = <&switch1port10 &switch0port10>; 862 }; 863 }; 864 }; 865}; 866