17109d817SMarek Behún// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27109d817SMarek Behún/* 37109d817SMarek Behún * Device Tree file for CZ.NIC Turris Mox Board 4b37c3848SMarek Behún * 2019 by Marek Behún <kabel@kernel.org> 57109d817SMarek Behún */ 67109d817SMarek Behún 77109d817SMarek Behún/dts-v1/; 87109d817SMarek Behún 97109d817SMarek Behún#include <dt-bindings/bus/moxtet.h> 107109d817SMarek Behún#include <dt-bindings/gpio/gpio.h> 117109d817SMarek Behún#include <dt-bindings/input/input.h> 127109d817SMarek Behún#include "armada-372x.dtsi" 137109d817SMarek Behún 147109d817SMarek Behún/ { 157109d817SMarek Behún model = "CZ.NIC Turris Mox Board"; 167109d817SMarek Behún compatible = "cznic,turris-mox", "marvell,armada3720", 177109d817SMarek Behún "marvell,armada3710"; 187109d817SMarek Behún 197109d817SMarek Behún aliases { 207109d817SMarek Behún spi0 = &spi0; 217109d817SMarek Behún ethernet1 = ð1; 22923f9892SVladimir Oltean mmc0 = &sdhci0; 23923f9892SVladimir Oltean mmc1 = &sdhci1; 247109d817SMarek Behún }; 257109d817SMarek Behún 267109d817SMarek Behún chosen { 277109d817SMarek Behún stdout-path = "serial0:115200n8"; 287109d817SMarek Behún }; 297109d817SMarek Behún 307109d817SMarek Behún memory@0 { 317109d817SMarek Behún device_type = "memory"; 327109d817SMarek Behún reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 337109d817SMarek Behún }; 347109d817SMarek Behún 357109d817SMarek Behún leds { 367109d817SMarek Behún compatible = "gpio-leds"; 377109d817SMarek Behún red { 387109d817SMarek Behún label = "mox:red:activity"; 397109d817SMarek Behún gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 407109d817SMarek Behún linux,default-trigger = "default-on"; 417109d817SMarek Behún }; 427109d817SMarek Behún }; 437109d817SMarek Behún 447109d817SMarek Behún gpio-keys { 457109d817SMarek Behún compatible = "gpio-keys"; 467109d817SMarek Behún 477109d817SMarek Behún reset { 487109d817SMarek Behún label = "reset"; 497109d817SMarek Behún linux,code = <KEY_RESTART>; 507109d817SMarek Behún gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 517109d817SMarek Behún debounce-interval = <60>; 527109d817SMarek Behún }; 537109d817SMarek Behún }; 547109d817SMarek Behún 557109d817SMarek Behún exp_usb3_vbus: usb3-vbus { 567109d817SMarek Behún compatible = "regulator-fixed"; 577109d817SMarek Behún regulator-name = "usb3-vbus"; 587109d817SMarek Behún regulator-min-microvolt = <5000000>; 597109d817SMarek Behún regulator-max-microvolt = <5000000>; 607109d817SMarek Behún enable-active-high; 617109d817SMarek Behún regulator-always-on; 627109d817SMarek Behún gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 637109d817SMarek Behún }; 647109d817SMarek Behún 657109d817SMarek Behún vsdc_reg: vsdc-reg { 667109d817SMarek Behún compatible = "regulator-gpio"; 677109d817SMarek Behún regulator-name = "vsdc"; 687109d817SMarek Behún regulator-min-microvolt = <1800000>; 697109d817SMarek Behún regulator-max-microvolt = <3300000>; 707109d817SMarek Behún regulator-boot-on; 717109d817SMarek Behún 727109d817SMarek Behún gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 737109d817SMarek Behún gpios-states = <0>; 747109d817SMarek Behún states = <1800000 0x1 757109d817SMarek Behún 3300000 0x0>; 767109d817SMarek Behún enable-active-high; 777109d817SMarek Behún }; 787109d817SMarek Behún 797109d817SMarek Behún vsdio_reg: vsdio-reg { 807109d817SMarek Behún compatible = "regulator-gpio"; 817109d817SMarek Behún regulator-name = "vsdio"; 827109d817SMarek Behún regulator-min-microvolt = <1800000>; 837109d817SMarek Behún regulator-max-microvolt = <3300000>; 847109d817SMarek Behún regulator-boot-on; 857109d817SMarek Behún 867109d817SMarek Behún gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 877109d817SMarek Behún gpios-states = <0>; 887109d817SMarek Behún states = <1800000 0x1 897109d817SMarek Behún 3300000 0x0>; 907109d817SMarek Behún enable-active-high; 917109d817SMarek Behún }; 927109d817SMarek Behún 937109d817SMarek Behún sdhci1_pwrseq: sdhci1-pwrseq { 947109d817SMarek Behún compatible = "mmc-pwrseq-simple"; 957109d817SMarek Behún reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 967109d817SMarek Behún status = "okay"; 977109d817SMarek Behún }; 987109d817SMarek Behún 997109d817SMarek Behún sfp: sfp { 100c2671acbSMarek Behún compatible = "sff,sfp"; 1017109d817SMarek Behún i2c-bus = <&i2c0>; 1027109d817SMarek Behún los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 1037109d817SMarek Behún tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 1047109d817SMarek Behún mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 1057109d817SMarek Behún tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 1067109d817SMarek Behún rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 107a2081c09SMarek Behún maximum-power-milliwatt = <3000>; 1087109d817SMarek Behún 1097109d817SMarek Behún /* enabled by U-Boot if SFP module is present */ 1107109d817SMarek Behún status = "disabled"; 1117109d817SMarek Behún }; 11246d2f6d0SMarek Behún 11346d2f6d0SMarek Behún firmware { 1143a52a489SPali Rohár armada-3700-rwtm { 1153a52a489SPali Rohár compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; 11646d2f6d0SMarek Behún }; 11746d2f6d0SMarek Behún }; 1187109d817SMarek Behún}; 1197109d817SMarek Behún 1207109d817SMarek Behún&i2c0 { 1217109d817SMarek Behún pinctrl-names = "default"; 1227109d817SMarek Behún pinctrl-0 = <&i2c1_pins>; 1237109d817SMarek Behún clock-frequency = <100000>; 124ee7ab3f2SPali Rohár /delete-property/ mrvl,i2c-fast-mode; 1257109d817SMarek Behún status = "okay"; 1267109d817SMarek Behún 1277109d817SMarek Behún rtc@6f { 1287109d817SMarek Behún compatible = "microchip,mcp7940x"; 1297109d817SMarek Behún reg = <0x6f>; 1307109d817SMarek Behún }; 1317109d817SMarek Behún}; 1327109d817SMarek Behún 1337109d817SMarek Behún&pcie0 { 1347109d817SMarek Behún pinctrl-names = "default"; 1357109d817SMarek Behún pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 1367109d817SMarek Behún status = "okay"; 1377109d817SMarek Behún reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 138514ef1e6SPali Rohár /* 139514ef1e6SPali Rohár * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property 140514ef1e6SPali Rohár * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and 141*a1cc1697SPali Rohár * 2 size cells and also expects that the second range starts at 16 MB offset. Also it 142*a1cc1697SPali Rohár * expects that first range uses same address for PCI (child) and CPU (parent) cells (so 143*a1cc1697SPali Rohár * no remapping) and that this address is the lowest from all specified ranges. If these 144514ef1e6SPali Rohár * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address 145514ef1e6SPali Rohár * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window 146514ef1e6SPali Rohár * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. 147514ef1e6SPali Rohár * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in 148514ef1e6SPali Rohár * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): 149514ef1e6SPali Rohár * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 150514ef1e6SPali Rohár * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf 151514ef1e6SPali Rohár * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 152*a1cc1697SPali Rohár * Bug related to requirement of same child and parent addresses for first range is fixed 153*a1cc1697SPali Rohár * in U-Boot version 2022.04 by following commit: 154*a1cc1697SPali Rohár * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 155514ef1e6SPali Rohár */ 156514ef1e6SPali Rohár #address-cells = <3>; 157514ef1e6SPali Rohár #size-cells = <2>; 158514ef1e6SPali Rohár ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ 159514ef1e6SPali Rohár 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ 1607109d817SMarek Behún 1617109d817SMarek Behún /* enabled by U-Boot if PCIe module is present */ 1627109d817SMarek Behún status = "disabled"; 1637109d817SMarek Behún}; 1647109d817SMarek Behún 1657109d817SMarek Behún&uart0 { 1667109d817SMarek Behún status = "okay"; 1677109d817SMarek Behún}; 1687109d817SMarek Behún 1697109d817SMarek Behúnð0 { 1707109d817SMarek Behún pinctrl-names = "default"; 1717109d817SMarek Behún pinctrl-0 = <&rgmii_pins>; 1727109d817SMarek Behún phy-mode = "rgmii-id"; 1733aa669a9SMarek Behún phy-handle = <&phy1>; 1747109d817SMarek Behún status = "okay"; 1757109d817SMarek Behún}; 1767109d817SMarek Behún 1777109d817SMarek Behúnð1 { 1787109d817SMarek Behún phy-mode = "2500base-x"; 1797109d817SMarek Behún managed = "in-band-status"; 1807109d817SMarek Behún phys = <&comphy0 1>; 1817109d817SMarek Behún}; 1827109d817SMarek Behún 1837109d817SMarek Behún&sdhci0 { 1847109d817SMarek Behún wp-inverted; 1857109d817SMarek Behún bus-width = <4>; 1867109d817SMarek Behún cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 1877109d817SMarek Behún vqmmc-supply = <&vsdc_reg>; 1887109d817SMarek Behún marvell,pad-type = "sd"; 1897109d817SMarek Behún status = "okay"; 1907109d817SMarek Behún}; 1917109d817SMarek Behún 1927109d817SMarek Behún&sdhci1 { 1937109d817SMarek Behún pinctrl-names = "default"; 1947109d817SMarek Behún pinctrl-0 = <&sdio_pins>; 1957109d817SMarek Behún non-removable; 1967109d817SMarek Behún bus-width = <4>; 1977109d817SMarek Behún marvell,pad-type = "sd"; 1987109d817SMarek Behún vqmmc-supply = <&vsdio_reg>; 1997109d817SMarek Behún mmc-pwrseq = <&sdhci1_pwrseq>; 2007a2c36b0SMarek Behún /* forbid SDR104 for FCC purposes */ 2017a2c36b0SMarek Behún sdhci-caps-mask = <0x2 0x0>; 2027109d817SMarek Behún status = "okay"; 2037109d817SMarek Behún}; 2047109d817SMarek Behún 2057109d817SMarek Behún&spi0 { 2067109d817SMarek Behún status = "okay"; 2077109d817SMarek Behún pinctrl-names = "default"; 2087109d817SMarek Behún pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 2097109d817SMarek Behún assigned-clocks = <&nb_periph_clk 7>; 2107109d817SMarek Behún assigned-clock-parents = <&tbg 1>; 2117109d817SMarek Behún assigned-clock-rates = <20000000>; 2127109d817SMarek Behún 2137109d817SMarek Behún spi-flash@0 { 2147109d817SMarek Behún #address-cells = <1>; 2157109d817SMarek Behún #size-cells = <1>; 2167109d817SMarek Behún compatible = "jedec,spi-nor"; 2177109d817SMarek Behún reg = <0>; 2187109d817SMarek Behún spi-max-frequency = <20000000>; 2197109d817SMarek Behún 2207109d817SMarek Behún partitions { 2217109d817SMarek Behún compatible = "fixed-partitions"; 2227109d817SMarek Behún #address-cells = <1>; 2237109d817SMarek Behún #size-cells = <1>; 2247109d817SMarek Behún 2257109d817SMarek Behún partition@0 { 2267109d817SMarek Behún label = "secure-firmware"; 2277109d817SMarek Behún reg = <0x0 0x20000>; 2287109d817SMarek Behún }; 2297109d817SMarek Behún 2307109d817SMarek Behún partition@20000 { 231a9d9bfcaSMarek Behún label = "a53-firmware"; 2327109d817SMarek Behún reg = <0x20000 0x160000>; 2337109d817SMarek Behún }; 2347109d817SMarek Behún 2357109d817SMarek Behún partition@180000 { 2367109d817SMarek Behún label = "u-boot-env"; 2377109d817SMarek Behún reg = <0x180000 0x10000>; 2387109d817SMarek Behún }; 2397109d817SMarek Behún 2407109d817SMarek Behún partition@190000 { 2417109d817SMarek Behún label = "Rescue system"; 2427109d817SMarek Behún reg = <0x190000 0x660000>; 2437109d817SMarek Behún }; 2447109d817SMarek Behún 2457109d817SMarek Behún partition@7f0000 { 2467109d817SMarek Behún label = "dtb"; 2477109d817SMarek Behún reg = <0x7f0000 0x10000>; 2487109d817SMarek Behún }; 2497109d817SMarek Behún }; 2507109d817SMarek Behún }; 2517109d817SMarek Behún 2527109d817SMarek Behún moxtet: moxtet@1 { 2537109d817SMarek Behún #address-cells = <1>; 2547109d817SMarek Behún #size-cells = <0>; 2557109d817SMarek Behún compatible = "cznic,moxtet"; 2567109d817SMarek Behún reg = <1>; 2577109d817SMarek Behún reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 2587109d817SMarek Behún spi-max-frequency = <10000000>; 2597109d817SMarek Behún spi-cpol; 2607109d817SMarek Behún spi-cpha; 2617109d817SMarek Behún interrupt-controller; 2627109d817SMarek Behún #interrupt-cells = <1>; 2637109d817SMarek Behún interrupt-parent = <&gpiosb>; 2647109d817SMarek Behún interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 2657109d817SMarek Behún status = "okay"; 2667109d817SMarek Behún 2677109d817SMarek Behún moxtet_sfp: gpio@0 { 2687109d817SMarek Behún compatible = "cznic,moxtet-gpio"; 2697109d817SMarek Behún gpio-controller; 2707109d817SMarek Behún #gpio-cells = <2>; 2717109d817SMarek Behún reg = <0>; 2727109d817SMarek Behún status = "disabled"; 2737109d817SMarek Behún }; 2747109d817SMarek Behún }; 2757109d817SMarek Behún}; 2767109d817SMarek Behún 2777109d817SMarek Behún&usb2 { 2787109d817SMarek Behún status = "okay"; 2797109d817SMarek Behún}; 2807109d817SMarek Behún 281187c195aSMarek Behún&comphy2 { 282187c195aSMarek Behún connector { 283187c195aSMarek Behún compatible = "usb-a-connector"; 284187c195aSMarek Behún phy-supply = <&exp_usb3_vbus>; 285187c195aSMarek Behún }; 286187c195aSMarek Behún}; 287187c195aSMarek Behún 2887109d817SMarek Behún&usb3 { 2897109d817SMarek Behún status = "okay"; 2907109d817SMarek Behún phys = <&comphy2 0>; 2917109d817SMarek Behún}; 2927109d817SMarek Behún 2937109d817SMarek Behún&mdio { 2947109d817SMarek Behún pinctrl-names = "default"; 2957109d817SMarek Behún pinctrl-0 = <&smi_pins>; 2967109d817SMarek Behún status = "okay"; 2977109d817SMarek Behún 2987109d817SMarek Behún phy1: ethernet-phy@1 { 2997109d817SMarek Behún reg = <1>; 3007109d817SMarek Behún }; 3017109d817SMarek Behún 3027109d817SMarek Behún /* switch nodes are enabled by U-Boot if modules are present */ 3037109d817SMarek Behún switch0@10 { 3047109d817SMarek Behún compatible = "marvell,mv88e6190"; 3057109d817SMarek Behún reg = <0x10 0>; 3067109d817SMarek Behún dsa,member = <0 0>; 3077109d817SMarek Behún interrupt-parent = <&moxtet>; 3087109d817SMarek Behún interrupts = <MOXTET_IRQ_PERIDOT(0)>; 3097109d817SMarek Behún status = "disabled"; 3107109d817SMarek Behún 3117109d817SMarek Behún mdio { 3127109d817SMarek Behún #address-cells = <1>; 3137109d817SMarek Behún #size-cells = <0>; 3147109d817SMarek Behún 3157109d817SMarek Behún switch0phy1: switch0phy1@1 { 3167109d817SMarek Behún reg = <0x1>; 3177109d817SMarek Behún }; 3187109d817SMarek Behún 3197109d817SMarek Behún switch0phy2: switch0phy2@2 { 3207109d817SMarek Behún reg = <0x2>; 3217109d817SMarek Behún }; 3227109d817SMarek Behún 3237109d817SMarek Behún switch0phy3: switch0phy3@3 { 3247109d817SMarek Behún reg = <0x3>; 3257109d817SMarek Behún }; 3267109d817SMarek Behún 3277109d817SMarek Behún switch0phy4: switch0phy4@4 { 3287109d817SMarek Behún reg = <0x4>; 3297109d817SMarek Behún }; 3307109d817SMarek Behún 3317109d817SMarek Behún switch0phy5: switch0phy5@5 { 3327109d817SMarek Behún reg = <0x5>; 3337109d817SMarek Behún }; 3347109d817SMarek Behún 3357109d817SMarek Behún switch0phy6: switch0phy6@6 { 3367109d817SMarek Behún reg = <0x6>; 3377109d817SMarek Behún }; 3387109d817SMarek Behún 3397109d817SMarek Behún switch0phy7: switch0phy7@7 { 3407109d817SMarek Behún reg = <0x7>; 3417109d817SMarek Behún }; 3427109d817SMarek Behún 3437109d817SMarek Behún switch0phy8: switch0phy8@8 { 3447109d817SMarek Behún reg = <0x8>; 3457109d817SMarek Behún }; 3467109d817SMarek Behún }; 3477109d817SMarek Behún 3487109d817SMarek Behún ports { 3497109d817SMarek Behún #address-cells = <1>; 3507109d817SMarek Behún #size-cells = <0>; 3517109d817SMarek Behún 3527109d817SMarek Behún port@1 { 3537109d817SMarek Behún reg = <0x1>; 3547109d817SMarek Behún label = "lan1"; 3557109d817SMarek Behún phy-handle = <&switch0phy1>; 3567109d817SMarek Behún }; 3577109d817SMarek Behún 3587109d817SMarek Behún port@2 { 3597109d817SMarek Behún reg = <0x2>; 3607109d817SMarek Behún label = "lan2"; 3617109d817SMarek Behún phy-handle = <&switch0phy2>; 3627109d817SMarek Behún }; 3637109d817SMarek Behún 3647109d817SMarek Behún port@3 { 3657109d817SMarek Behún reg = <0x3>; 3667109d817SMarek Behún label = "lan3"; 3677109d817SMarek Behún phy-handle = <&switch0phy3>; 3687109d817SMarek Behún }; 3697109d817SMarek Behún 3707109d817SMarek Behún port@4 { 3717109d817SMarek Behún reg = <0x4>; 3727109d817SMarek Behún label = "lan4"; 3737109d817SMarek Behún phy-handle = <&switch0phy4>; 3747109d817SMarek Behún }; 3757109d817SMarek Behún 3767109d817SMarek Behún port@5 { 3777109d817SMarek Behún reg = <0x5>; 3787109d817SMarek Behún label = "lan5"; 3797109d817SMarek Behún phy-handle = <&switch0phy5>; 3807109d817SMarek Behún }; 3817109d817SMarek Behún 3827109d817SMarek Behún port@6 { 3837109d817SMarek Behún reg = <0x6>; 3847109d817SMarek Behún label = "lan6"; 3857109d817SMarek Behún phy-handle = <&switch0phy6>; 3867109d817SMarek Behún }; 3877109d817SMarek Behún 3887109d817SMarek Behún port@7 { 3897109d817SMarek Behún reg = <0x7>; 3907109d817SMarek Behún label = "lan7"; 3917109d817SMarek Behún phy-handle = <&switch0phy7>; 3927109d817SMarek Behún }; 3937109d817SMarek Behún 3947109d817SMarek Behún port@8 { 3957109d817SMarek Behún reg = <0x8>; 3967109d817SMarek Behún label = "lan8"; 3977109d817SMarek Behún phy-handle = <&switch0phy8>; 3987109d817SMarek Behún }; 3997109d817SMarek Behún 4007109d817SMarek Behún port@9 { 4017109d817SMarek Behún reg = <0x9>; 4027109d817SMarek Behún label = "cpu"; 4037109d817SMarek Behún ethernet = <ð1>; 4047109d817SMarek Behún phy-mode = "2500base-x"; 4057109d817SMarek Behún managed = "in-band-status"; 4067109d817SMarek Behún }; 4077109d817SMarek Behún 4087109d817SMarek Behún switch0port10: port@a { 4097109d817SMarek Behún reg = <0xa>; 4107109d817SMarek Behún label = "dsa"; 4117109d817SMarek Behún phy-mode = "2500base-x"; 4127109d817SMarek Behún managed = "in-band-status"; 4137109d817SMarek Behún link = <&switch1port9 &switch2port9>; 4147109d817SMarek Behún status = "disabled"; 4157109d817SMarek Behún }; 4167109d817SMarek Behún 4177109d817SMarek Behún port-sfp@a { 4187109d817SMarek Behún reg = <0xa>; 4197109d817SMarek Behún label = "sfp"; 4207109d817SMarek Behún sfp = <&sfp>; 4217109d817SMarek Behún phy-mode = "sgmii"; 4227109d817SMarek Behún managed = "in-band-status"; 4237109d817SMarek Behún status = "disabled"; 4247109d817SMarek Behún }; 4257109d817SMarek Behún }; 4267109d817SMarek Behún }; 4277109d817SMarek Behún 4287109d817SMarek Behún switch0@2 { 4297109d817SMarek Behún compatible = "marvell,mv88e6085"; 4307109d817SMarek Behún reg = <0x2 0>; 4317109d817SMarek Behún dsa,member = <0 0>; 4327109d817SMarek Behún interrupt-parent = <&moxtet>; 4337109d817SMarek Behún interrupts = <MOXTET_IRQ_TOPAZ>; 4347109d817SMarek Behún status = "disabled"; 4357109d817SMarek Behún 4367109d817SMarek Behún mdio { 4377109d817SMarek Behún #address-cells = <1>; 4387109d817SMarek Behún #size-cells = <0>; 4397109d817SMarek Behún 4407109d817SMarek Behún switch0phy1_topaz: switch0phy1@11 { 4417109d817SMarek Behún reg = <0x11>; 4427109d817SMarek Behún }; 4437109d817SMarek Behún 4447109d817SMarek Behún switch0phy2_topaz: switch0phy2@12 { 4457109d817SMarek Behún reg = <0x12>; 4467109d817SMarek Behún }; 4477109d817SMarek Behún 4487109d817SMarek Behún switch0phy3_topaz: switch0phy3@13 { 4497109d817SMarek Behún reg = <0x13>; 4507109d817SMarek Behún }; 4517109d817SMarek Behún 4527109d817SMarek Behún switch0phy4_topaz: switch0phy4@14 { 4537109d817SMarek Behún reg = <0x14>; 4547109d817SMarek Behún }; 4557109d817SMarek Behún }; 4567109d817SMarek Behún 4577109d817SMarek Behún ports { 4587109d817SMarek Behún #address-cells = <1>; 4597109d817SMarek Behún #size-cells = <0>; 4607109d817SMarek Behún 4617109d817SMarek Behún port@1 { 4627109d817SMarek Behún reg = <0x1>; 4637109d817SMarek Behún label = "lan1"; 4647109d817SMarek Behún phy-handle = <&switch0phy1_topaz>; 4657109d817SMarek Behún }; 4667109d817SMarek Behún 4677109d817SMarek Behún port@2 { 4687109d817SMarek Behún reg = <0x2>; 4697109d817SMarek Behún label = "lan2"; 4707109d817SMarek Behún phy-handle = <&switch0phy2_topaz>; 4717109d817SMarek Behún }; 4727109d817SMarek Behún 4737109d817SMarek Behún port@3 { 4747109d817SMarek Behún reg = <0x3>; 4757109d817SMarek Behún label = "lan3"; 4767109d817SMarek Behún phy-handle = <&switch0phy3_topaz>; 4777109d817SMarek Behún }; 4787109d817SMarek Behún 4797109d817SMarek Behún port@4 { 4807109d817SMarek Behún reg = <0x4>; 4817109d817SMarek Behún label = "lan4"; 4827109d817SMarek Behún phy-handle = <&switch0phy4_topaz>; 4837109d817SMarek Behún }; 4847109d817SMarek Behún 4857109d817SMarek Behún port@5 { 4867109d817SMarek Behún reg = <0x5>; 4877109d817SMarek Behún label = "cpu"; 4887109d817SMarek Behún phy-mode = "2500base-x"; 4897109d817SMarek Behún managed = "in-band-status"; 4907109d817SMarek Behún ethernet = <ð1>; 4917109d817SMarek Behún }; 4927109d817SMarek Behún }; 4937109d817SMarek Behún }; 4947109d817SMarek Behún 4957109d817SMarek Behún switch1@11 { 4967109d817SMarek Behún compatible = "marvell,mv88e6190"; 4977109d817SMarek Behún reg = <0x11 0>; 4987109d817SMarek Behún dsa,member = <0 1>; 4997109d817SMarek Behún interrupt-parent = <&moxtet>; 5007109d817SMarek Behún interrupts = <MOXTET_IRQ_PERIDOT(1)>; 5017109d817SMarek Behún status = "disabled"; 5027109d817SMarek Behún 5037109d817SMarek Behún mdio { 5047109d817SMarek Behún #address-cells = <1>; 5057109d817SMarek Behún #size-cells = <0>; 5067109d817SMarek Behún 5077109d817SMarek Behún switch1phy1: switch1phy1@1 { 5087109d817SMarek Behún reg = <0x1>; 5097109d817SMarek Behún }; 5107109d817SMarek Behún 5117109d817SMarek Behún switch1phy2: switch1phy2@2 { 5127109d817SMarek Behún reg = <0x2>; 5137109d817SMarek Behún }; 5147109d817SMarek Behún 5157109d817SMarek Behún switch1phy3: switch1phy3@3 { 5167109d817SMarek Behún reg = <0x3>; 5177109d817SMarek Behún }; 5187109d817SMarek Behún 5197109d817SMarek Behún switch1phy4: switch1phy4@4 { 5207109d817SMarek Behún reg = <0x4>; 5217109d817SMarek Behún }; 5227109d817SMarek Behún 5237109d817SMarek Behún switch1phy5: switch1phy5@5 { 5247109d817SMarek Behún reg = <0x5>; 5257109d817SMarek Behún }; 5267109d817SMarek Behún 5277109d817SMarek Behún switch1phy6: switch1phy6@6 { 5287109d817SMarek Behún reg = <0x6>; 5297109d817SMarek Behún }; 5307109d817SMarek Behún 5317109d817SMarek Behún switch1phy7: switch1phy7@7 { 5327109d817SMarek Behún reg = <0x7>; 5337109d817SMarek Behún }; 5347109d817SMarek Behún 5357109d817SMarek Behún switch1phy8: switch1phy8@8 { 5367109d817SMarek Behún reg = <0x8>; 5377109d817SMarek Behún }; 5387109d817SMarek Behún }; 5397109d817SMarek Behún 5407109d817SMarek Behún ports { 5417109d817SMarek Behún #address-cells = <1>; 5427109d817SMarek Behún #size-cells = <0>; 5437109d817SMarek Behún 5447109d817SMarek Behún port@1 { 5457109d817SMarek Behún reg = <0x1>; 5467109d817SMarek Behún label = "lan9"; 5477109d817SMarek Behún phy-handle = <&switch1phy1>; 5487109d817SMarek Behún }; 5497109d817SMarek Behún 5507109d817SMarek Behún port@2 { 5517109d817SMarek Behún reg = <0x2>; 5527109d817SMarek Behún label = "lan10"; 5537109d817SMarek Behún phy-handle = <&switch1phy2>; 5547109d817SMarek Behún }; 5557109d817SMarek Behún 5567109d817SMarek Behún port@3 { 5577109d817SMarek Behún reg = <0x3>; 5587109d817SMarek Behún label = "lan11"; 5597109d817SMarek Behún phy-handle = <&switch1phy3>; 5607109d817SMarek Behún }; 5617109d817SMarek Behún 5627109d817SMarek Behún port@4 { 5637109d817SMarek Behún reg = <0x4>; 5647109d817SMarek Behún label = "lan12"; 5657109d817SMarek Behún phy-handle = <&switch1phy4>; 5667109d817SMarek Behún }; 5677109d817SMarek Behún 5687109d817SMarek Behún port@5 { 5697109d817SMarek Behún reg = <0x5>; 5707109d817SMarek Behún label = "lan13"; 5717109d817SMarek Behún phy-handle = <&switch1phy5>; 5727109d817SMarek Behún }; 5737109d817SMarek Behún 5747109d817SMarek Behún port@6 { 5757109d817SMarek Behún reg = <0x6>; 5767109d817SMarek Behún label = "lan14"; 5777109d817SMarek Behún phy-handle = <&switch1phy6>; 5787109d817SMarek Behún }; 5797109d817SMarek Behún 5807109d817SMarek Behún port@7 { 5817109d817SMarek Behún reg = <0x7>; 5827109d817SMarek Behún label = "lan15"; 5837109d817SMarek Behún phy-handle = <&switch1phy7>; 5847109d817SMarek Behún }; 5857109d817SMarek Behún 5867109d817SMarek Behún port@8 { 5877109d817SMarek Behún reg = <0x8>; 5887109d817SMarek Behún label = "lan16"; 5897109d817SMarek Behún phy-handle = <&switch1phy8>; 5907109d817SMarek Behún }; 5917109d817SMarek Behún 5927109d817SMarek Behún switch1port9: port@9 { 5937109d817SMarek Behún reg = <0x9>; 5947109d817SMarek Behún label = "dsa"; 5957109d817SMarek Behún phy-mode = "2500base-x"; 5967109d817SMarek Behún managed = "in-band-status"; 5977109d817SMarek Behún link = <&switch0port10>; 5987109d817SMarek Behún }; 5997109d817SMarek Behún 6007109d817SMarek Behún switch1port10: port@a { 6017109d817SMarek Behún reg = <0xa>; 6027109d817SMarek Behún label = "dsa"; 6037109d817SMarek Behún phy-mode = "2500base-x"; 6047109d817SMarek Behún managed = "in-band-status"; 6057109d817SMarek Behún link = <&switch2port9>; 6067109d817SMarek Behún status = "disabled"; 6077109d817SMarek Behún }; 6087109d817SMarek Behún 6097109d817SMarek Behún port-sfp@a { 6107109d817SMarek Behún reg = <0xa>; 6117109d817SMarek Behún label = "sfp"; 6127109d817SMarek Behún sfp = <&sfp>; 6137109d817SMarek Behún phy-mode = "sgmii"; 6147109d817SMarek Behún managed = "in-band-status"; 6157109d817SMarek Behún status = "disabled"; 6167109d817SMarek Behún }; 6177109d817SMarek Behún }; 6187109d817SMarek Behún }; 6197109d817SMarek Behún 6207109d817SMarek Behún switch1@2 { 6217109d817SMarek Behún compatible = "marvell,mv88e6085"; 6227109d817SMarek Behún reg = <0x2 0>; 6237109d817SMarek Behún dsa,member = <0 1>; 6247109d817SMarek Behún interrupt-parent = <&moxtet>; 6257109d817SMarek Behún interrupts = <MOXTET_IRQ_TOPAZ>; 6267109d817SMarek Behún status = "disabled"; 6277109d817SMarek Behún 6287109d817SMarek Behún mdio { 6297109d817SMarek Behún #address-cells = <1>; 6307109d817SMarek Behún #size-cells = <0>; 6317109d817SMarek Behún 6327109d817SMarek Behún switch1phy1_topaz: switch1phy1@11 { 6337109d817SMarek Behún reg = <0x11>; 6347109d817SMarek Behún }; 6357109d817SMarek Behún 6367109d817SMarek Behún switch1phy2_topaz: switch1phy2@12 { 6377109d817SMarek Behún reg = <0x12>; 6387109d817SMarek Behún }; 6397109d817SMarek Behún 6407109d817SMarek Behún switch1phy3_topaz: switch1phy3@13 { 6417109d817SMarek Behún reg = <0x13>; 6427109d817SMarek Behún }; 6437109d817SMarek Behún 6447109d817SMarek Behún switch1phy4_topaz: switch1phy4@14 { 6457109d817SMarek Behún reg = <0x14>; 6467109d817SMarek Behún }; 6477109d817SMarek Behún }; 6487109d817SMarek Behún 6497109d817SMarek Behún ports { 6507109d817SMarek Behún #address-cells = <1>; 6517109d817SMarek Behún #size-cells = <0>; 6527109d817SMarek Behún 6537109d817SMarek Behún port@1 { 6547109d817SMarek Behún reg = <0x1>; 6557109d817SMarek Behún label = "lan9"; 6567109d817SMarek Behún phy-handle = <&switch1phy1_topaz>; 6577109d817SMarek Behún }; 6587109d817SMarek Behún 6597109d817SMarek Behún port@2 { 6607109d817SMarek Behún reg = <0x2>; 6617109d817SMarek Behún label = "lan10"; 6627109d817SMarek Behún phy-handle = <&switch1phy2_topaz>; 6637109d817SMarek Behún }; 6647109d817SMarek Behún 6657109d817SMarek Behún port@3 { 6667109d817SMarek Behún reg = <0x3>; 6677109d817SMarek Behún label = "lan11"; 6687109d817SMarek Behún phy-handle = <&switch1phy3_topaz>; 6697109d817SMarek Behún }; 6707109d817SMarek Behún 6717109d817SMarek Behún port@4 { 6727109d817SMarek Behún reg = <0x4>; 6737109d817SMarek Behún label = "lan12"; 6747109d817SMarek Behún phy-handle = <&switch1phy4_topaz>; 6757109d817SMarek Behún }; 6767109d817SMarek Behún 6777109d817SMarek Behún port@5 { 6787109d817SMarek Behún reg = <0x5>; 6797109d817SMarek Behún label = "dsa"; 6807109d817SMarek Behún phy-mode = "2500base-x"; 6817109d817SMarek Behún managed = "in-band-status"; 6827109d817SMarek Behún link = <&switch0port10>; 6837109d817SMarek Behún }; 6847109d817SMarek Behún }; 6857109d817SMarek Behún }; 6867109d817SMarek Behún 6877109d817SMarek Behún switch2@12 { 6887109d817SMarek Behún compatible = "marvell,mv88e6190"; 6897109d817SMarek Behún reg = <0x12 0>; 6907109d817SMarek Behún dsa,member = <0 2>; 6917109d817SMarek Behún interrupt-parent = <&moxtet>; 6927109d817SMarek Behún interrupts = <MOXTET_IRQ_PERIDOT(2)>; 6937109d817SMarek Behún status = "disabled"; 6947109d817SMarek Behún 6957109d817SMarek Behún mdio { 6967109d817SMarek Behún #address-cells = <1>; 6977109d817SMarek Behún #size-cells = <0>; 6987109d817SMarek Behún 6997109d817SMarek Behún switch2phy1: switch2phy1@1 { 7007109d817SMarek Behún reg = <0x1>; 7017109d817SMarek Behún }; 7027109d817SMarek Behún 7037109d817SMarek Behún switch2phy2: switch2phy2@2 { 7047109d817SMarek Behún reg = <0x2>; 7057109d817SMarek Behún }; 7067109d817SMarek Behún 7077109d817SMarek Behún switch2phy3: switch2phy3@3 { 7087109d817SMarek Behún reg = <0x3>; 7097109d817SMarek Behún }; 7107109d817SMarek Behún 7117109d817SMarek Behún switch2phy4: switch2phy4@4 { 7127109d817SMarek Behún reg = <0x4>; 7137109d817SMarek Behún }; 7147109d817SMarek Behún 7157109d817SMarek Behún switch2phy5: switch2phy5@5 { 7167109d817SMarek Behún reg = <0x5>; 7177109d817SMarek Behún }; 7187109d817SMarek Behún 7197109d817SMarek Behún switch2phy6: switch2phy6@6 { 7207109d817SMarek Behún reg = <0x6>; 7217109d817SMarek Behún }; 7227109d817SMarek Behún 7237109d817SMarek Behún switch2phy7: switch2phy7@7 { 7247109d817SMarek Behún reg = <0x7>; 7257109d817SMarek Behún }; 7267109d817SMarek Behún 7277109d817SMarek Behún switch2phy8: switch2phy8@8 { 7287109d817SMarek Behún reg = <0x8>; 7297109d817SMarek Behún }; 7307109d817SMarek Behún }; 7317109d817SMarek Behún 7327109d817SMarek Behún ports { 7337109d817SMarek Behún #address-cells = <1>; 7347109d817SMarek Behún #size-cells = <0>; 7357109d817SMarek Behún 7367109d817SMarek Behún port@1 { 7377109d817SMarek Behún reg = <0x1>; 7387109d817SMarek Behún label = "lan17"; 7397109d817SMarek Behún phy-handle = <&switch2phy1>; 7407109d817SMarek Behún }; 7417109d817SMarek Behún 7427109d817SMarek Behún port@2 { 7437109d817SMarek Behún reg = <0x2>; 7447109d817SMarek Behún label = "lan18"; 7457109d817SMarek Behún phy-handle = <&switch2phy2>; 7467109d817SMarek Behún }; 7477109d817SMarek Behún 7487109d817SMarek Behún port@3 { 7497109d817SMarek Behún reg = <0x3>; 7507109d817SMarek Behún label = "lan19"; 7517109d817SMarek Behún phy-handle = <&switch2phy3>; 7527109d817SMarek Behún }; 7537109d817SMarek Behún 7547109d817SMarek Behún port@4 { 7557109d817SMarek Behún reg = <0x4>; 7567109d817SMarek Behún label = "lan20"; 7577109d817SMarek Behún phy-handle = <&switch2phy4>; 7587109d817SMarek Behún }; 7597109d817SMarek Behún 7607109d817SMarek Behún port@5 { 7617109d817SMarek Behún reg = <0x5>; 7627109d817SMarek Behún label = "lan21"; 7637109d817SMarek Behún phy-handle = <&switch2phy5>; 7647109d817SMarek Behún }; 7657109d817SMarek Behún 7667109d817SMarek Behún port@6 { 7677109d817SMarek Behún reg = <0x6>; 7687109d817SMarek Behún label = "lan22"; 7697109d817SMarek Behún phy-handle = <&switch2phy6>; 7707109d817SMarek Behún }; 7717109d817SMarek Behún 7727109d817SMarek Behún port@7 { 7737109d817SMarek Behún reg = <0x7>; 7747109d817SMarek Behún label = "lan23"; 7757109d817SMarek Behún phy-handle = <&switch2phy7>; 7767109d817SMarek Behún }; 7777109d817SMarek Behún 7787109d817SMarek Behún port@8 { 7797109d817SMarek Behún reg = <0x8>; 7807109d817SMarek Behún label = "lan24"; 7817109d817SMarek Behún phy-handle = <&switch2phy8>; 7827109d817SMarek Behún }; 7837109d817SMarek Behún 7847109d817SMarek Behún switch2port9: port@9 { 7857109d817SMarek Behún reg = <0x9>; 7867109d817SMarek Behún label = "dsa"; 7877109d817SMarek Behún phy-mode = "2500base-x"; 7887109d817SMarek Behún managed = "in-band-status"; 7897109d817SMarek Behún link = <&switch1port10 &switch0port10>; 7907109d817SMarek Behún }; 7917109d817SMarek Behún 7927109d817SMarek Behún port-sfp@a { 7937109d817SMarek Behún reg = <0xa>; 7947109d817SMarek Behún label = "sfp"; 7957109d817SMarek Behún sfp = <&sfp>; 7967109d817SMarek Behún phy-mode = "sgmii"; 7977109d817SMarek Behún managed = "in-band-status"; 7987109d817SMarek Behún status = "disabled"; 7997109d817SMarek Behún }; 8007109d817SMarek Behún }; 8017109d817SMarek Behún }; 8027109d817SMarek Behún 8037109d817SMarek Behún switch2@2 { 8047109d817SMarek Behún compatible = "marvell,mv88e6085"; 8057109d817SMarek Behún reg = <0x2 0>; 8067109d817SMarek Behún dsa,member = <0 2>; 8077109d817SMarek Behún interrupt-parent = <&moxtet>; 8087109d817SMarek Behún interrupts = <MOXTET_IRQ_TOPAZ>; 8097109d817SMarek Behún status = "disabled"; 8107109d817SMarek Behún 8117109d817SMarek Behún mdio { 8127109d817SMarek Behún #address-cells = <1>; 8137109d817SMarek Behún #size-cells = <0>; 8147109d817SMarek Behún 8157109d817SMarek Behún switch2phy1_topaz: switch2phy1@11 { 8167109d817SMarek Behún reg = <0x11>; 8177109d817SMarek Behún }; 8187109d817SMarek Behún 8197109d817SMarek Behún switch2phy2_topaz: switch2phy2@12 { 8207109d817SMarek Behún reg = <0x12>; 8217109d817SMarek Behún }; 8227109d817SMarek Behún 8237109d817SMarek Behún switch2phy3_topaz: switch2phy3@13 { 8247109d817SMarek Behún reg = <0x13>; 8257109d817SMarek Behún }; 8267109d817SMarek Behún 8277109d817SMarek Behún switch2phy4_topaz: switch2phy4@14 { 8287109d817SMarek Behún reg = <0x14>; 8297109d817SMarek Behún }; 8307109d817SMarek Behún }; 8317109d817SMarek Behún 8327109d817SMarek Behún ports { 8337109d817SMarek Behún #address-cells = <1>; 8347109d817SMarek Behún #size-cells = <0>; 8357109d817SMarek Behún 8367109d817SMarek Behún port@1 { 8377109d817SMarek Behún reg = <0x1>; 8387109d817SMarek Behún label = "lan17"; 8397109d817SMarek Behún phy-handle = <&switch2phy1_topaz>; 8407109d817SMarek Behún }; 8417109d817SMarek Behún 8427109d817SMarek Behún port@2 { 8437109d817SMarek Behún reg = <0x2>; 8447109d817SMarek Behún label = "lan18"; 8457109d817SMarek Behún phy-handle = <&switch2phy2_topaz>; 8467109d817SMarek Behún }; 8477109d817SMarek Behún 8487109d817SMarek Behún port@3 { 8497109d817SMarek Behún reg = <0x3>; 8507109d817SMarek Behún label = "lan19"; 8517109d817SMarek Behún phy-handle = <&switch2phy3_topaz>; 8527109d817SMarek Behún }; 8537109d817SMarek Behún 8547109d817SMarek Behún port@4 { 8557109d817SMarek Behún reg = <0x4>; 8567109d817SMarek Behún label = "lan20"; 8577109d817SMarek Behún phy-handle = <&switch2phy4_topaz>; 8587109d817SMarek Behún }; 8597109d817SMarek Behún 8607109d817SMarek Behún port@5 { 8617109d817SMarek Behún reg = <0x5>; 8627109d817SMarek Behún label = "dsa"; 8637109d817SMarek Behún phy-mode = "2500base-x"; 8647109d817SMarek Behún managed = "in-band-status"; 8657109d817SMarek Behún link = <&switch1port10 &switch0port10>; 8667109d817SMarek Behún }; 8677109d817SMarek Behún }; 8687109d817SMarek Behún }; 8697109d817SMarek Behún}; 870