17109d817SMarek Behún// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 27109d817SMarek Behún/* 37109d817SMarek Behún * Device Tree file for CZ.NIC Turris Mox Board 47109d817SMarek Behún * 2019 by Marek Behun <marek.behun@nic.cz> 57109d817SMarek Behún */ 67109d817SMarek Behún 77109d817SMarek Behún/dts-v1/; 87109d817SMarek Behún 97109d817SMarek Behún#include <dt-bindings/bus/moxtet.h> 107109d817SMarek Behún#include <dt-bindings/gpio/gpio.h> 117109d817SMarek Behún#include <dt-bindings/input/input.h> 127109d817SMarek Behún#include "armada-372x.dtsi" 137109d817SMarek Behún 147109d817SMarek Behún/ { 157109d817SMarek Behún model = "CZ.NIC Turris Mox Board"; 167109d817SMarek Behún compatible = "cznic,turris-mox", "marvell,armada3720", 177109d817SMarek Behún "marvell,armada3710"; 187109d817SMarek Behún 197109d817SMarek Behún aliases { 207109d817SMarek Behún spi0 = &spi0; 217109d817SMarek Behún ethernet1 = ð1; 227109d817SMarek Behún }; 237109d817SMarek Behún 247109d817SMarek Behún chosen { 257109d817SMarek Behún stdout-path = "serial0:115200n8"; 267109d817SMarek Behún }; 277109d817SMarek Behún 287109d817SMarek Behún memory@0 { 297109d817SMarek Behún device_type = "memory"; 307109d817SMarek Behún reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 317109d817SMarek Behún }; 327109d817SMarek Behún 337109d817SMarek Behún leds { 347109d817SMarek Behún compatible = "gpio-leds"; 357109d817SMarek Behún red { 367109d817SMarek Behún label = "mox:red:activity"; 377109d817SMarek Behún gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; 387109d817SMarek Behún linux,default-trigger = "default-on"; 397109d817SMarek Behún }; 407109d817SMarek Behún }; 417109d817SMarek Behún 427109d817SMarek Behún gpio-keys { 437109d817SMarek Behún compatible = "gpio-keys"; 447109d817SMarek Behún 457109d817SMarek Behún reset { 467109d817SMarek Behún label = "reset"; 477109d817SMarek Behún linux,code = <KEY_RESTART>; 487109d817SMarek Behún gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; 497109d817SMarek Behún debounce-interval = <60>; 507109d817SMarek Behún }; 517109d817SMarek Behún }; 527109d817SMarek Behún 537109d817SMarek Behún exp_usb3_vbus: usb3-vbus { 547109d817SMarek Behún compatible = "regulator-fixed"; 557109d817SMarek Behún regulator-name = "usb3-vbus"; 567109d817SMarek Behún regulator-min-microvolt = <5000000>; 577109d817SMarek Behún regulator-max-microvolt = <5000000>; 587109d817SMarek Behún enable-active-high; 597109d817SMarek Behún regulator-always-on; 607109d817SMarek Behún gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; 617109d817SMarek Behún }; 627109d817SMarek Behún 637109d817SMarek Behún vsdc_reg: vsdc-reg { 647109d817SMarek Behún compatible = "regulator-gpio"; 657109d817SMarek Behún regulator-name = "vsdc"; 667109d817SMarek Behún regulator-min-microvolt = <1800000>; 677109d817SMarek Behún regulator-max-microvolt = <3300000>; 687109d817SMarek Behún regulator-boot-on; 697109d817SMarek Behún 707109d817SMarek Behún gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 717109d817SMarek Behún gpios-states = <0>; 727109d817SMarek Behún states = <1800000 0x1 737109d817SMarek Behún 3300000 0x0>; 747109d817SMarek Behún enable-active-high; 757109d817SMarek Behún }; 767109d817SMarek Behún 777109d817SMarek Behún vsdio_reg: vsdio-reg { 787109d817SMarek Behún compatible = "regulator-gpio"; 797109d817SMarek Behún regulator-name = "vsdio"; 807109d817SMarek Behún regulator-min-microvolt = <1800000>; 817109d817SMarek Behún regulator-max-microvolt = <3300000>; 827109d817SMarek Behún regulator-boot-on; 837109d817SMarek Behún 847109d817SMarek Behún gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>; 857109d817SMarek Behún gpios-states = <0>; 867109d817SMarek Behún states = <1800000 0x1 877109d817SMarek Behún 3300000 0x0>; 887109d817SMarek Behún enable-active-high; 897109d817SMarek Behún }; 907109d817SMarek Behún 917109d817SMarek Behún sdhci1_pwrseq: sdhci1-pwrseq { 927109d817SMarek Behún compatible = "mmc-pwrseq-simple"; 937109d817SMarek Behún reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>; 947109d817SMarek Behún status = "okay"; 957109d817SMarek Behún }; 967109d817SMarek Behún 977109d817SMarek Behún sfp: sfp { 987109d817SMarek Behún compatible = "sff,sfp+"; 997109d817SMarek Behún i2c-bus = <&i2c0>; 1007109d817SMarek Behún los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; 1017109d817SMarek Behún tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; 1027109d817SMarek Behún mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; 1037109d817SMarek Behún tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; 1047109d817SMarek Behún rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; 1057109d817SMarek Behún 1067109d817SMarek Behún /* enabled by U-Boot if SFP module is present */ 1077109d817SMarek Behún status = "disabled"; 1087109d817SMarek Behún }; 1097109d817SMarek Behún}; 1107109d817SMarek Behún 1117109d817SMarek Behún&i2c0 { 1127109d817SMarek Behún pinctrl-names = "default"; 1137109d817SMarek Behún pinctrl-0 = <&i2c1_pins>; 1147109d817SMarek Behún clock-frequency = <100000>; 1157109d817SMarek Behún status = "okay"; 1167109d817SMarek Behún 1177109d817SMarek Behún rtc@6f { 1187109d817SMarek Behún compatible = "microchip,mcp7940x"; 1197109d817SMarek Behún reg = <0x6f>; 1207109d817SMarek Behún }; 1217109d817SMarek Behún}; 1227109d817SMarek Behún 1237109d817SMarek Behún&pcie_reset_pins { 1247109d817SMarek Behún function = "gpio"; 1257109d817SMarek Behún}; 1267109d817SMarek Behún 1277109d817SMarek Behún&pcie0 { 1287109d817SMarek Behún pinctrl-names = "default"; 1297109d817SMarek Behún pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 1307109d817SMarek Behún status = "okay"; 1317109d817SMarek Behún max-link-speed = <2>; 1327109d817SMarek Behún reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 1337109d817SMarek Behún phys = <&comphy1 0>; 1347109d817SMarek Behún 1357109d817SMarek Behún /* enabled by U-Boot if PCIe module is present */ 1367109d817SMarek Behún status = "disabled"; 1377109d817SMarek Behún}; 1387109d817SMarek Behún 1397109d817SMarek Behún&uart0 { 1407109d817SMarek Behún status = "okay"; 1417109d817SMarek Behún}; 1427109d817SMarek Behún 1437109d817SMarek Behúnð0 { 1447109d817SMarek Behún pinctrl-names = "default"; 1457109d817SMarek Behún pinctrl-0 = <&rgmii_pins>; 1467109d817SMarek Behún phy-mode = "rgmii-id"; 1477109d817SMarek Behún phy = <&phy1>; 1487109d817SMarek Behún status = "okay"; 1497109d817SMarek Behún}; 1507109d817SMarek Behún 1517109d817SMarek Behúnð1 { 1527109d817SMarek Behún phy-mode = "2500base-x"; 1537109d817SMarek Behún managed = "in-band-status"; 1547109d817SMarek Behún phys = <&comphy0 1>; 1557109d817SMarek Behún}; 1567109d817SMarek Behún 1577109d817SMarek Behún&sdhci0 { 1587109d817SMarek Behún wp-inverted; 1597109d817SMarek Behún bus-width = <4>; 1607109d817SMarek Behún cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>; 1617109d817SMarek Behún vqmmc-supply = <&vsdc_reg>; 1627109d817SMarek Behún marvell,pad-type = "sd"; 1637109d817SMarek Behún status = "okay"; 1647109d817SMarek Behún}; 1657109d817SMarek Behún 1667109d817SMarek Behún&sdhci1 { 1677109d817SMarek Behún pinctrl-names = "default"; 1687109d817SMarek Behún pinctrl-0 = <&sdio_pins>; 1697109d817SMarek Behún non-removable; 1707109d817SMarek Behún bus-width = <4>; 1717109d817SMarek Behún marvell,pad-type = "sd"; 1727109d817SMarek Behún vqmmc-supply = <&vsdio_reg>; 1737109d817SMarek Behún mmc-pwrseq = <&sdhci1_pwrseq>; 1747109d817SMarek Behún status = "okay"; 1757109d817SMarek Behún}; 1767109d817SMarek Behún 1777109d817SMarek Behún&spi0 { 1787109d817SMarek Behún status = "okay"; 1797109d817SMarek Behún pinctrl-names = "default"; 1807109d817SMarek Behún pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>; 1817109d817SMarek Behún assigned-clocks = <&nb_periph_clk 7>; 1827109d817SMarek Behún assigned-clock-parents = <&tbg 1>; 1837109d817SMarek Behún assigned-clock-rates = <20000000>; 1847109d817SMarek Behún 1857109d817SMarek Behún spi-flash@0 { 1867109d817SMarek Behún #address-cells = <1>; 1877109d817SMarek Behún #size-cells = <1>; 1887109d817SMarek Behún compatible = "jedec,spi-nor"; 1897109d817SMarek Behún reg = <0>; 1907109d817SMarek Behún spi-max-frequency = <20000000>; 1917109d817SMarek Behún 1927109d817SMarek Behún partitions { 1937109d817SMarek Behún compatible = "fixed-partitions"; 1947109d817SMarek Behún #address-cells = <1>; 1957109d817SMarek Behún #size-cells = <1>; 1967109d817SMarek Behún 1977109d817SMarek Behún partition@0 { 1987109d817SMarek Behún label = "secure-firmware"; 1997109d817SMarek Behún reg = <0x0 0x20000>; 2007109d817SMarek Behún }; 2017109d817SMarek Behún 2027109d817SMarek Behún partition@20000 { 2037109d817SMarek Behún label = "u-boot"; 2047109d817SMarek Behún reg = <0x20000 0x160000>; 2057109d817SMarek Behún }; 2067109d817SMarek Behún 2077109d817SMarek Behún partition@180000 { 2087109d817SMarek Behún label = "u-boot-env"; 2097109d817SMarek Behún reg = <0x180000 0x10000>; 2107109d817SMarek Behún }; 2117109d817SMarek Behún 2127109d817SMarek Behún partition@190000 { 2137109d817SMarek Behún label = "Rescue system"; 2147109d817SMarek Behún reg = <0x190000 0x660000>; 2157109d817SMarek Behún }; 2167109d817SMarek Behún 2177109d817SMarek Behún partition@7f0000 { 2187109d817SMarek Behún label = "dtb"; 2197109d817SMarek Behún reg = <0x7f0000 0x10000>; 2207109d817SMarek Behún }; 2217109d817SMarek Behún }; 2227109d817SMarek Behún }; 2237109d817SMarek Behún 2247109d817SMarek Behún moxtet: moxtet@1 { 2257109d817SMarek Behún #address-cells = <1>; 2267109d817SMarek Behún #size-cells = <0>; 2277109d817SMarek Behún compatible = "cznic,moxtet"; 2287109d817SMarek Behún reg = <1>; 2297109d817SMarek Behún reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 2307109d817SMarek Behún spi-max-frequency = <10000000>; 2317109d817SMarek Behún spi-cpol; 2327109d817SMarek Behún spi-cpha; 2337109d817SMarek Behún interrupt-controller; 2347109d817SMarek Behún #interrupt-cells = <1>; 2357109d817SMarek Behún interrupt-parent = <&gpiosb>; 2367109d817SMarek Behún interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 2377109d817SMarek Behún status = "okay"; 2387109d817SMarek Behún 2397109d817SMarek Behún moxtet_sfp: gpio@0 { 2407109d817SMarek Behún compatible = "cznic,moxtet-gpio"; 2417109d817SMarek Behún gpio-controller; 2427109d817SMarek Behún #gpio-cells = <2>; 2437109d817SMarek Behún reg = <0>; 2447109d817SMarek Behún status = "disabled"; 2457109d817SMarek Behún }; 2467109d817SMarek Behún }; 2477109d817SMarek Behún}; 2487109d817SMarek Behún 2497109d817SMarek Behún&usb2 { 2507109d817SMarek Behún status = "okay"; 2517109d817SMarek Behún}; 2527109d817SMarek Behún 253187c195aSMarek Behún&comphy2 { 254187c195aSMarek Behún connector { 255187c195aSMarek Behún compatible = "usb-a-connector"; 256187c195aSMarek Behún phy-supply = <&exp_usb3_vbus>; 257187c195aSMarek Behún }; 258187c195aSMarek Behún}; 259187c195aSMarek Behún 2607109d817SMarek Behún&usb3 { 2617109d817SMarek Behún status = "okay"; 2627109d817SMarek Behún phys = <&comphy2 0>; 2637109d817SMarek Behún}; 2647109d817SMarek Behún 2657109d817SMarek Behún&mdio { 2667109d817SMarek Behún pinctrl-names = "default"; 2677109d817SMarek Behún pinctrl-0 = <&smi_pins>; 2687109d817SMarek Behún status = "okay"; 2697109d817SMarek Behún 2707109d817SMarek Behún phy1: ethernet-phy@1 { 2717109d817SMarek Behún reg = <1>; 2727109d817SMarek Behún }; 2737109d817SMarek Behún 2747109d817SMarek Behún /* switch nodes are enabled by U-Boot if modules are present */ 2757109d817SMarek Behún switch0@10 { 2767109d817SMarek Behún compatible = "marvell,mv88e6190"; 2777109d817SMarek Behún reg = <0x10 0>; 2787109d817SMarek Behún dsa,member = <0 0>; 2797109d817SMarek Behún interrupt-parent = <&moxtet>; 2807109d817SMarek Behún interrupts = <MOXTET_IRQ_PERIDOT(0)>; 2817109d817SMarek Behún status = "disabled"; 2827109d817SMarek Behún 2837109d817SMarek Behún mdio { 2847109d817SMarek Behún #address-cells = <1>; 2857109d817SMarek Behún #size-cells = <0>; 2867109d817SMarek Behún 2877109d817SMarek Behún switch0phy1: switch0phy1@1 { 2887109d817SMarek Behún reg = <0x1>; 2897109d817SMarek Behún }; 2907109d817SMarek Behún 2917109d817SMarek Behún switch0phy2: switch0phy2@2 { 2927109d817SMarek Behún reg = <0x2>; 2937109d817SMarek Behún }; 2947109d817SMarek Behún 2957109d817SMarek Behún switch0phy3: switch0phy3@3 { 2967109d817SMarek Behún reg = <0x3>; 2977109d817SMarek Behún }; 2987109d817SMarek Behún 2997109d817SMarek Behún switch0phy4: switch0phy4@4 { 3007109d817SMarek Behún reg = <0x4>; 3017109d817SMarek Behún }; 3027109d817SMarek Behún 3037109d817SMarek Behún switch0phy5: switch0phy5@5 { 3047109d817SMarek Behún reg = <0x5>; 3057109d817SMarek Behún }; 3067109d817SMarek Behún 3077109d817SMarek Behún switch0phy6: switch0phy6@6 { 3087109d817SMarek Behún reg = <0x6>; 3097109d817SMarek Behún }; 3107109d817SMarek Behún 3117109d817SMarek Behún switch0phy7: switch0phy7@7 { 3127109d817SMarek Behún reg = <0x7>; 3137109d817SMarek Behún }; 3147109d817SMarek Behún 3157109d817SMarek Behún switch0phy8: switch0phy8@8 { 3167109d817SMarek Behún reg = <0x8>; 3177109d817SMarek Behún }; 3187109d817SMarek Behún }; 3197109d817SMarek Behún 3207109d817SMarek Behún ports { 3217109d817SMarek Behún #address-cells = <1>; 3227109d817SMarek Behún #size-cells = <0>; 3237109d817SMarek Behún 3247109d817SMarek Behún port@1 { 3257109d817SMarek Behún reg = <0x1>; 3267109d817SMarek Behún label = "lan1"; 3277109d817SMarek Behún phy-handle = <&switch0phy1>; 3287109d817SMarek Behún }; 3297109d817SMarek Behún 3307109d817SMarek Behún port@2 { 3317109d817SMarek Behún reg = <0x2>; 3327109d817SMarek Behún label = "lan2"; 3337109d817SMarek Behún phy-handle = <&switch0phy2>; 3347109d817SMarek Behún }; 3357109d817SMarek Behún 3367109d817SMarek Behún port@3 { 3377109d817SMarek Behún reg = <0x3>; 3387109d817SMarek Behún label = "lan3"; 3397109d817SMarek Behún phy-handle = <&switch0phy3>; 3407109d817SMarek Behún }; 3417109d817SMarek Behún 3427109d817SMarek Behún port@4 { 3437109d817SMarek Behún reg = <0x4>; 3447109d817SMarek Behún label = "lan4"; 3457109d817SMarek Behún phy-handle = <&switch0phy4>; 3467109d817SMarek Behún }; 3477109d817SMarek Behún 3487109d817SMarek Behún port@5 { 3497109d817SMarek Behún reg = <0x5>; 3507109d817SMarek Behún label = "lan5"; 3517109d817SMarek Behún phy-handle = <&switch0phy5>; 3527109d817SMarek Behún }; 3537109d817SMarek Behún 3547109d817SMarek Behún port@6 { 3557109d817SMarek Behún reg = <0x6>; 3567109d817SMarek Behún label = "lan6"; 3577109d817SMarek Behún phy-handle = <&switch0phy6>; 3587109d817SMarek Behún }; 3597109d817SMarek Behún 3607109d817SMarek Behún port@7 { 3617109d817SMarek Behún reg = <0x7>; 3627109d817SMarek Behún label = "lan7"; 3637109d817SMarek Behún phy-handle = <&switch0phy7>; 3647109d817SMarek Behún }; 3657109d817SMarek Behún 3667109d817SMarek Behún port@8 { 3677109d817SMarek Behún reg = <0x8>; 3687109d817SMarek Behún label = "lan8"; 3697109d817SMarek Behún phy-handle = <&switch0phy8>; 3707109d817SMarek Behún }; 3717109d817SMarek Behún 3727109d817SMarek Behún port@9 { 3737109d817SMarek Behún reg = <0x9>; 3747109d817SMarek Behún label = "cpu"; 3757109d817SMarek Behún ethernet = <ð1>; 3767109d817SMarek Behún phy-mode = "2500base-x"; 3777109d817SMarek Behún managed = "in-band-status"; 3787109d817SMarek Behún }; 3797109d817SMarek Behún 3807109d817SMarek Behún switch0port10: port@a { 3817109d817SMarek Behún reg = <0xa>; 3827109d817SMarek Behún label = "dsa"; 3837109d817SMarek Behún phy-mode = "2500base-x"; 3847109d817SMarek Behún managed = "in-band-status"; 3857109d817SMarek Behún link = <&switch1port9 &switch2port9>; 3867109d817SMarek Behún status = "disabled"; 3877109d817SMarek Behún }; 3887109d817SMarek Behún 3897109d817SMarek Behún port-sfp@a { 3907109d817SMarek Behún reg = <0xa>; 3917109d817SMarek Behún label = "sfp"; 3927109d817SMarek Behún sfp = <&sfp>; 3937109d817SMarek Behún phy-mode = "sgmii"; 3947109d817SMarek Behún managed = "in-band-status"; 3957109d817SMarek Behún status = "disabled"; 3967109d817SMarek Behún }; 3977109d817SMarek Behún }; 3987109d817SMarek Behún }; 3997109d817SMarek Behún 4007109d817SMarek Behún switch0@2 { 4017109d817SMarek Behún compatible = "marvell,mv88e6085"; 4027109d817SMarek Behún reg = <0x2 0>; 4037109d817SMarek Behún dsa,member = <0 0>; 4047109d817SMarek Behún interrupt-parent = <&moxtet>; 4057109d817SMarek Behún interrupts = <MOXTET_IRQ_TOPAZ>; 4067109d817SMarek Behún status = "disabled"; 4077109d817SMarek Behún 4087109d817SMarek Behún mdio { 4097109d817SMarek Behún #address-cells = <1>; 4107109d817SMarek Behún #size-cells = <0>; 4117109d817SMarek Behún 4127109d817SMarek Behún switch0phy1_topaz: switch0phy1@11 { 4137109d817SMarek Behún reg = <0x11>; 4147109d817SMarek Behún }; 4157109d817SMarek Behún 4167109d817SMarek Behún switch0phy2_topaz: switch0phy2@12 { 4177109d817SMarek Behún reg = <0x12>; 4187109d817SMarek Behún }; 4197109d817SMarek Behún 4207109d817SMarek Behún switch0phy3_topaz: switch0phy3@13 { 4217109d817SMarek Behún reg = <0x13>; 4227109d817SMarek Behún }; 4237109d817SMarek Behún 4247109d817SMarek Behún switch0phy4_topaz: switch0phy4@14 { 4257109d817SMarek Behún reg = <0x14>; 4267109d817SMarek Behún }; 4277109d817SMarek Behún }; 4287109d817SMarek Behún 4297109d817SMarek Behún ports { 4307109d817SMarek Behún #address-cells = <1>; 4317109d817SMarek Behún #size-cells = <0>; 4327109d817SMarek Behún 4337109d817SMarek Behún port@1 { 4347109d817SMarek Behún reg = <0x1>; 4357109d817SMarek Behún label = "lan1"; 4367109d817SMarek Behún phy-handle = <&switch0phy1_topaz>; 4377109d817SMarek Behún }; 4387109d817SMarek Behún 4397109d817SMarek Behún port@2 { 4407109d817SMarek Behún reg = <0x2>; 4417109d817SMarek Behún label = "lan2"; 4427109d817SMarek Behún phy-handle = <&switch0phy2_topaz>; 4437109d817SMarek Behún }; 4447109d817SMarek Behún 4457109d817SMarek Behún port@3 { 4467109d817SMarek Behún reg = <0x3>; 4477109d817SMarek Behún label = "lan3"; 4487109d817SMarek Behún phy-handle = <&switch0phy3_topaz>; 4497109d817SMarek Behún }; 4507109d817SMarek Behún 4517109d817SMarek Behún port@4 { 4527109d817SMarek Behún reg = <0x4>; 4537109d817SMarek Behún label = "lan4"; 4547109d817SMarek Behún phy-handle = <&switch0phy4_topaz>; 4557109d817SMarek Behún }; 4567109d817SMarek Behún 4577109d817SMarek Behún port@5 { 4587109d817SMarek Behún reg = <0x5>; 4597109d817SMarek Behún label = "cpu"; 4607109d817SMarek Behún phy-mode = "2500base-x"; 4617109d817SMarek Behún managed = "in-band-status"; 4627109d817SMarek Behún ethernet = <ð1>; 4637109d817SMarek Behún }; 4647109d817SMarek Behún }; 4657109d817SMarek Behún }; 4667109d817SMarek Behún 4677109d817SMarek Behún switch1@11 { 4687109d817SMarek Behún compatible = "marvell,mv88e6190"; 4697109d817SMarek Behún reg = <0x11 0>; 4707109d817SMarek Behún dsa,member = <0 1>; 4717109d817SMarek Behún interrupt-parent = <&moxtet>; 4727109d817SMarek Behún interrupts = <MOXTET_IRQ_PERIDOT(1)>; 4737109d817SMarek Behún status = "disabled"; 4747109d817SMarek Behún 4757109d817SMarek Behún mdio { 4767109d817SMarek Behún #address-cells = <1>; 4777109d817SMarek Behún #size-cells = <0>; 4787109d817SMarek Behún 4797109d817SMarek Behún switch1phy1: switch1phy1@1 { 4807109d817SMarek Behún reg = <0x1>; 4817109d817SMarek Behún }; 4827109d817SMarek Behún 4837109d817SMarek Behún switch1phy2: switch1phy2@2 { 4847109d817SMarek Behún reg = <0x2>; 4857109d817SMarek Behún }; 4867109d817SMarek Behún 4877109d817SMarek Behún switch1phy3: switch1phy3@3 { 4887109d817SMarek Behún reg = <0x3>; 4897109d817SMarek Behún }; 4907109d817SMarek Behún 4917109d817SMarek Behún switch1phy4: switch1phy4@4 { 4927109d817SMarek Behún reg = <0x4>; 4937109d817SMarek Behún }; 4947109d817SMarek Behún 4957109d817SMarek Behún switch1phy5: switch1phy5@5 { 4967109d817SMarek Behún reg = <0x5>; 4977109d817SMarek Behún }; 4987109d817SMarek Behún 4997109d817SMarek Behún switch1phy6: switch1phy6@6 { 5007109d817SMarek Behún reg = <0x6>; 5017109d817SMarek Behún }; 5027109d817SMarek Behún 5037109d817SMarek Behún switch1phy7: switch1phy7@7 { 5047109d817SMarek Behún reg = <0x7>; 5057109d817SMarek Behún }; 5067109d817SMarek Behún 5077109d817SMarek Behún switch1phy8: switch1phy8@8 { 5087109d817SMarek Behún reg = <0x8>; 5097109d817SMarek Behún }; 5107109d817SMarek Behún }; 5117109d817SMarek Behún 5127109d817SMarek Behún ports { 5137109d817SMarek Behún #address-cells = <1>; 5147109d817SMarek Behún #size-cells = <0>; 5157109d817SMarek Behún 5167109d817SMarek Behún port@1 { 5177109d817SMarek Behún reg = <0x1>; 5187109d817SMarek Behún label = "lan9"; 5197109d817SMarek Behún phy-handle = <&switch1phy1>; 5207109d817SMarek Behún }; 5217109d817SMarek Behún 5227109d817SMarek Behún port@2 { 5237109d817SMarek Behún reg = <0x2>; 5247109d817SMarek Behún label = "lan10"; 5257109d817SMarek Behún phy-handle = <&switch1phy2>; 5267109d817SMarek Behún }; 5277109d817SMarek Behún 5287109d817SMarek Behún port@3 { 5297109d817SMarek Behún reg = <0x3>; 5307109d817SMarek Behún label = "lan11"; 5317109d817SMarek Behún phy-handle = <&switch1phy3>; 5327109d817SMarek Behún }; 5337109d817SMarek Behún 5347109d817SMarek Behún port@4 { 5357109d817SMarek Behún reg = <0x4>; 5367109d817SMarek Behún label = "lan12"; 5377109d817SMarek Behún phy-handle = <&switch1phy4>; 5387109d817SMarek Behún }; 5397109d817SMarek Behún 5407109d817SMarek Behún port@5 { 5417109d817SMarek Behún reg = <0x5>; 5427109d817SMarek Behún label = "lan13"; 5437109d817SMarek Behún phy-handle = <&switch1phy5>; 5447109d817SMarek Behún }; 5457109d817SMarek Behún 5467109d817SMarek Behún port@6 { 5477109d817SMarek Behún reg = <0x6>; 5487109d817SMarek Behún label = "lan14"; 5497109d817SMarek Behún phy-handle = <&switch1phy6>; 5507109d817SMarek Behún }; 5517109d817SMarek Behún 5527109d817SMarek Behún port@7 { 5537109d817SMarek Behún reg = <0x7>; 5547109d817SMarek Behún label = "lan15"; 5557109d817SMarek Behún phy-handle = <&switch1phy7>; 5567109d817SMarek Behún }; 5577109d817SMarek Behún 5587109d817SMarek Behún port@8 { 5597109d817SMarek Behún reg = <0x8>; 5607109d817SMarek Behún label = "lan16"; 5617109d817SMarek Behún phy-handle = <&switch1phy8>; 5627109d817SMarek Behún }; 5637109d817SMarek Behún 5647109d817SMarek Behún switch1port9: port@9 { 5657109d817SMarek Behún reg = <0x9>; 5667109d817SMarek Behún label = "dsa"; 5677109d817SMarek Behún phy-mode = "2500base-x"; 5687109d817SMarek Behún managed = "in-band-status"; 5697109d817SMarek Behún link = <&switch0port10>; 5707109d817SMarek Behún }; 5717109d817SMarek Behún 5727109d817SMarek Behún switch1port10: port@a { 5737109d817SMarek Behún reg = <0xa>; 5747109d817SMarek Behún label = "dsa"; 5757109d817SMarek Behún phy-mode = "2500base-x"; 5767109d817SMarek Behún managed = "in-band-status"; 5777109d817SMarek Behún link = <&switch2port9>; 5787109d817SMarek Behún status = "disabled"; 5797109d817SMarek Behún }; 5807109d817SMarek Behún 5817109d817SMarek Behún port-sfp@a { 5827109d817SMarek Behún reg = <0xa>; 5837109d817SMarek Behún label = "sfp"; 5847109d817SMarek Behún sfp = <&sfp>; 5857109d817SMarek Behún phy-mode = "sgmii"; 5867109d817SMarek Behún managed = "in-band-status"; 5877109d817SMarek Behún status = "disabled"; 5887109d817SMarek Behún }; 5897109d817SMarek Behún }; 5907109d817SMarek Behún }; 5917109d817SMarek Behún 5927109d817SMarek Behún switch1@2 { 5937109d817SMarek Behún compatible = "marvell,mv88e6085"; 5947109d817SMarek Behún reg = <0x2 0>; 5957109d817SMarek Behún dsa,member = <0 1>; 5967109d817SMarek Behún interrupt-parent = <&moxtet>; 5977109d817SMarek Behún interrupts = <MOXTET_IRQ_TOPAZ>; 5987109d817SMarek Behún status = "disabled"; 5997109d817SMarek Behún 6007109d817SMarek Behún mdio { 6017109d817SMarek Behún #address-cells = <1>; 6027109d817SMarek Behún #size-cells = <0>; 6037109d817SMarek Behún 6047109d817SMarek Behún switch1phy1_topaz: switch1phy1@11 { 6057109d817SMarek Behún reg = <0x11>; 6067109d817SMarek Behún }; 6077109d817SMarek Behún 6087109d817SMarek Behún switch1phy2_topaz: switch1phy2@12 { 6097109d817SMarek Behún reg = <0x12>; 6107109d817SMarek Behún }; 6117109d817SMarek Behún 6127109d817SMarek Behún switch1phy3_topaz: switch1phy3@13 { 6137109d817SMarek Behún reg = <0x13>; 6147109d817SMarek Behún }; 6157109d817SMarek Behún 6167109d817SMarek Behún switch1phy4_topaz: switch1phy4@14 { 6177109d817SMarek Behún reg = <0x14>; 6187109d817SMarek Behún }; 6197109d817SMarek Behún }; 6207109d817SMarek Behún 6217109d817SMarek Behún ports { 6227109d817SMarek Behún #address-cells = <1>; 6237109d817SMarek Behún #size-cells = <0>; 6247109d817SMarek Behún 6257109d817SMarek Behún port@1 { 6267109d817SMarek Behún reg = <0x1>; 6277109d817SMarek Behún label = "lan9"; 6287109d817SMarek Behún phy-handle = <&switch1phy1_topaz>; 6297109d817SMarek Behún }; 6307109d817SMarek Behún 6317109d817SMarek Behún port@2 { 6327109d817SMarek Behún reg = <0x2>; 6337109d817SMarek Behún label = "lan10"; 6347109d817SMarek Behún phy-handle = <&switch1phy2_topaz>; 6357109d817SMarek Behún }; 6367109d817SMarek Behún 6377109d817SMarek Behún port@3 { 6387109d817SMarek Behún reg = <0x3>; 6397109d817SMarek Behún label = "lan11"; 6407109d817SMarek Behún phy-handle = <&switch1phy3_topaz>; 6417109d817SMarek Behún }; 6427109d817SMarek Behún 6437109d817SMarek Behún port@4 { 6447109d817SMarek Behún reg = <0x4>; 6457109d817SMarek Behún label = "lan12"; 6467109d817SMarek Behún phy-handle = <&switch1phy4_topaz>; 6477109d817SMarek Behún }; 6487109d817SMarek Behún 6497109d817SMarek Behún port@5 { 6507109d817SMarek Behún reg = <0x5>; 6517109d817SMarek Behún label = "dsa"; 6527109d817SMarek Behún phy-mode = "2500base-x"; 6537109d817SMarek Behún managed = "in-band-status"; 6547109d817SMarek Behún link = <&switch0port10>; 6557109d817SMarek Behún }; 6567109d817SMarek Behún }; 6577109d817SMarek Behún }; 6587109d817SMarek Behún 6597109d817SMarek Behún switch2@12 { 6607109d817SMarek Behún compatible = "marvell,mv88e6190"; 6617109d817SMarek Behún reg = <0x12 0>; 6627109d817SMarek Behún dsa,member = <0 2>; 6637109d817SMarek Behún interrupt-parent = <&moxtet>; 6647109d817SMarek Behún interrupts = <MOXTET_IRQ_PERIDOT(2)>; 6657109d817SMarek Behún status = "disabled"; 6667109d817SMarek Behún 6677109d817SMarek Behún mdio { 6687109d817SMarek Behún #address-cells = <1>; 6697109d817SMarek Behún #size-cells = <0>; 6707109d817SMarek Behún 6717109d817SMarek Behún switch2phy1: switch2phy1@1 { 6727109d817SMarek Behún reg = <0x1>; 6737109d817SMarek Behún }; 6747109d817SMarek Behún 6757109d817SMarek Behún switch2phy2: switch2phy2@2 { 6767109d817SMarek Behún reg = <0x2>; 6777109d817SMarek Behún }; 6787109d817SMarek Behún 6797109d817SMarek Behún switch2phy3: switch2phy3@3 { 6807109d817SMarek Behún reg = <0x3>; 6817109d817SMarek Behún }; 6827109d817SMarek Behún 6837109d817SMarek Behún switch2phy4: switch2phy4@4 { 6847109d817SMarek Behún reg = <0x4>; 6857109d817SMarek Behún }; 6867109d817SMarek Behún 6877109d817SMarek Behún switch2phy5: switch2phy5@5 { 6887109d817SMarek Behún reg = <0x5>; 6897109d817SMarek Behún }; 6907109d817SMarek Behún 6917109d817SMarek Behún switch2phy6: switch2phy6@6 { 6927109d817SMarek Behún reg = <0x6>; 6937109d817SMarek Behún }; 6947109d817SMarek Behún 6957109d817SMarek Behún switch2phy7: switch2phy7@7 { 6967109d817SMarek Behún reg = <0x7>; 6977109d817SMarek Behún }; 6987109d817SMarek Behún 6997109d817SMarek Behún switch2phy8: switch2phy8@8 { 7007109d817SMarek Behún reg = <0x8>; 7017109d817SMarek Behún }; 7027109d817SMarek Behún }; 7037109d817SMarek Behún 7047109d817SMarek Behún ports { 7057109d817SMarek Behún #address-cells = <1>; 7067109d817SMarek Behún #size-cells = <0>; 7077109d817SMarek Behún 7087109d817SMarek Behún port@1 { 7097109d817SMarek Behún reg = <0x1>; 7107109d817SMarek Behún label = "lan17"; 7117109d817SMarek Behún phy-handle = <&switch2phy1>; 7127109d817SMarek Behún }; 7137109d817SMarek Behún 7147109d817SMarek Behún port@2 { 7157109d817SMarek Behún reg = <0x2>; 7167109d817SMarek Behún label = "lan18"; 7177109d817SMarek Behún phy-handle = <&switch2phy2>; 7187109d817SMarek Behún }; 7197109d817SMarek Behún 7207109d817SMarek Behún port@3 { 7217109d817SMarek Behún reg = <0x3>; 7227109d817SMarek Behún label = "lan19"; 7237109d817SMarek Behún phy-handle = <&switch2phy3>; 7247109d817SMarek Behún }; 7257109d817SMarek Behún 7267109d817SMarek Behún port@4 { 7277109d817SMarek Behún reg = <0x4>; 7287109d817SMarek Behún label = "lan20"; 7297109d817SMarek Behún phy-handle = <&switch2phy4>; 7307109d817SMarek Behún }; 7317109d817SMarek Behún 7327109d817SMarek Behún port@5 { 7337109d817SMarek Behún reg = <0x5>; 7347109d817SMarek Behún label = "lan21"; 7357109d817SMarek Behún phy-handle = <&switch2phy5>; 7367109d817SMarek Behún }; 7377109d817SMarek Behún 7387109d817SMarek Behún port@6 { 7397109d817SMarek Behún reg = <0x6>; 7407109d817SMarek Behún label = "lan22"; 7417109d817SMarek Behún phy-handle = <&switch2phy6>; 7427109d817SMarek Behún }; 7437109d817SMarek Behún 7447109d817SMarek Behún port@7 { 7457109d817SMarek Behún reg = <0x7>; 7467109d817SMarek Behún label = "lan23"; 7477109d817SMarek Behún phy-handle = <&switch2phy7>; 7487109d817SMarek Behún }; 7497109d817SMarek Behún 7507109d817SMarek Behún port@8 { 7517109d817SMarek Behún reg = <0x8>; 7527109d817SMarek Behún label = "lan24"; 7537109d817SMarek Behún phy-handle = <&switch2phy8>; 7547109d817SMarek Behún }; 7557109d817SMarek Behún 7567109d817SMarek Behún switch2port9: port@9 { 7577109d817SMarek Behún reg = <0x9>; 7587109d817SMarek Behún label = "dsa"; 7597109d817SMarek Behún phy-mode = "2500base-x"; 7607109d817SMarek Behún managed = "in-band-status"; 7617109d817SMarek Behún link = <&switch1port10 &switch0port10>; 7627109d817SMarek Behún }; 7637109d817SMarek Behún 7647109d817SMarek Behún port-sfp@a { 7657109d817SMarek Behún reg = <0xa>; 7667109d817SMarek Behún label = "sfp"; 7677109d817SMarek Behún sfp = <&sfp>; 7687109d817SMarek Behún phy-mode = "sgmii"; 7697109d817SMarek Behún managed = "in-band-status"; 7707109d817SMarek Behún status = "disabled"; 7717109d817SMarek Behún }; 7727109d817SMarek Behún }; 7737109d817SMarek Behún }; 7747109d817SMarek Behún 7757109d817SMarek Behún switch2@2 { 7767109d817SMarek Behún compatible = "marvell,mv88e6085"; 7777109d817SMarek Behún reg = <0x2 0>; 7787109d817SMarek Behún dsa,member = <0 2>; 7797109d817SMarek Behún interrupt-parent = <&moxtet>; 7807109d817SMarek Behún interrupts = <MOXTET_IRQ_TOPAZ>; 7817109d817SMarek Behún status = "disabled"; 7827109d817SMarek Behún 7837109d817SMarek Behún mdio { 7847109d817SMarek Behún #address-cells = <1>; 7857109d817SMarek Behún #size-cells = <0>; 7867109d817SMarek Behún 7877109d817SMarek Behún switch2phy1_topaz: switch2phy1@11 { 7887109d817SMarek Behún reg = <0x11>; 7897109d817SMarek Behún }; 7907109d817SMarek Behún 7917109d817SMarek Behún switch2phy2_topaz: switch2phy2@12 { 7927109d817SMarek Behún reg = <0x12>; 7937109d817SMarek Behún }; 7947109d817SMarek Behún 7957109d817SMarek Behún switch2phy3_topaz: switch2phy3@13 { 7967109d817SMarek Behún reg = <0x13>; 7977109d817SMarek Behún }; 7987109d817SMarek Behún 7997109d817SMarek Behún switch2phy4_topaz: switch2phy4@14 { 8007109d817SMarek Behún reg = <0x14>; 8017109d817SMarek Behún }; 8027109d817SMarek Behún }; 8037109d817SMarek Behún 8047109d817SMarek Behún ports { 8057109d817SMarek Behún #address-cells = <1>; 8067109d817SMarek Behún #size-cells = <0>; 8077109d817SMarek Behún 8087109d817SMarek Behún port@1 { 8097109d817SMarek Behún reg = <0x1>; 8107109d817SMarek Behún label = "lan17"; 8117109d817SMarek Behún phy-handle = <&switch2phy1_topaz>; 8127109d817SMarek Behún }; 8137109d817SMarek Behún 8147109d817SMarek Behún port@2 { 8157109d817SMarek Behún reg = <0x2>; 8167109d817SMarek Behún label = "lan18"; 8177109d817SMarek Behún phy-handle = <&switch2phy2_topaz>; 8187109d817SMarek Behún }; 8197109d817SMarek Behún 8207109d817SMarek Behún port@3 { 8217109d817SMarek Behún reg = <0x3>; 8227109d817SMarek Behún label = "lan19"; 8237109d817SMarek Behún phy-handle = <&switch2phy3_topaz>; 8247109d817SMarek Behún }; 8257109d817SMarek Behún 8267109d817SMarek Behún port@4 { 8277109d817SMarek Behún reg = <0x4>; 8287109d817SMarek Behún label = "lan20"; 8297109d817SMarek Behún phy-handle = <&switch2phy4_topaz>; 8307109d817SMarek Behún }; 8317109d817SMarek Behún 8327109d817SMarek Behún port@5 { 8337109d817SMarek Behún reg = <0x5>; 8347109d817SMarek Behún label = "dsa"; 8357109d817SMarek Behún phy-mode = "2500base-x"; 8367109d817SMarek Behún managed = "in-band-status"; 8377109d817SMarek Behún link = <&switch1port10 &switch0port10>; 8387109d817SMarek Behún }; 8397109d817SMarek Behún }; 8407109d817SMarek Behún }; 8417109d817SMarek Behún}; 842