1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/agilex-clock.h> 10 11/ { 12 compatible = "intel,socfpga-agilex"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x1000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x1>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 }; 60 }; 61 62 pmu { 63 compatible = "arm,armv8-pmuv3"; 64 interrupts = <0 170 4>, 65 <0 171 4>, 66 <0 172 4>, 67 <0 173 4>; 68 interrupt-affinity = <&cpu0>, 69 <&cpu1>, 70 <&cpu2>, 71 <&cpu3>; 72 interrupt-parent = <&intc>; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 intc: intc@fffc1000 { 81 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0x0 0xfffc1000 0x0 0x1000>, 85 <0x0 0xfffc2000 0x0 0x2000>, 86 <0x0 0xfffc4000 0x0 0x2000>, 87 <0x0 0xfffc6000 0x0 0x2000>; 88 }; 89 90 soc { 91 #address-cells = <1>; 92 #size-cells = <1>; 93 compatible = "simple-bus"; 94 device_type = "soc"; 95 interrupt-parent = <&intc>; 96 ranges = <0 0 0 0xffffffff>; 97 98 base_fpga_region { 99 #address-cells = <0x1>; 100 #size-cells = <0x1>; 101 compatible = "fpga-region"; 102 fpga-mgr = <&fpga_mgr>; 103 }; 104 105 clkmgr: clock-controller@ffd10000 { 106 compatible = "intel,agilex-clkmgr"; 107 reg = <0xffd10000 0x1000>; 108 #clock-cells = <1>; 109 }; 110 111 clocks { 112 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 }; 116 117 cb_intosc_ls_clk: cb-intosc-ls-clk { 118 #clock-cells = <0>; 119 compatible = "fixed-clock"; 120 }; 121 122 f2s_free_clk: f2s-free-clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 }; 126 127 osc1: osc1 { 128 #clock-cells = <0>; 129 compatible = "fixed-clock"; 130 }; 131 132 qspi_clk: qspi-clk { 133 #clock-cells = <0>; 134 compatible = "fixed-clock"; 135 clock-frequency = <200000000>; 136 }; 137 }; 138 139 gmac0: ethernet@ff800000 { 140 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 141 reg = <0xff800000 0x2000>; 142 interrupts = <0 90 4>; 143 interrupt-names = "macirq"; 144 mac-address = [00 00 00 00 00 00]; 145 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 146 reset-names = "stmmaceth", "stmmaceth-ocp"; 147 tx-fifo-depth = <16384>; 148 rx-fifo-depth = <16384>; 149 snps,multicast-filter-bins = <256>; 150 iommus = <&smmu 1>; 151 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 152 clocks = <&clkmgr AGILEX_EMAC0_CLK>; 153 clock-names = "stmmaceth"; 154 status = "disabled"; 155 }; 156 157 gmac1: ethernet@ff802000 { 158 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 159 reg = <0xff802000 0x2000>; 160 interrupts = <0 91 4>; 161 interrupt-names = "macirq"; 162 mac-address = [00 00 00 00 00 00]; 163 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 164 reset-names = "stmmaceth", "stmmaceth-ocp"; 165 tx-fifo-depth = <16384>; 166 rx-fifo-depth = <16384>; 167 snps,multicast-filter-bins = <256>; 168 iommus = <&smmu 2>; 169 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 170 clocks = <&clkmgr AGILEX_EMAC1_CLK>; 171 clock-names = "stmmaceth"; 172 status = "disabled"; 173 }; 174 175 gmac2: ethernet@ff804000 { 176 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 177 reg = <0xff804000 0x2000>; 178 interrupts = <0 92 4>; 179 interrupt-names = "macirq"; 180 mac-address = [00 00 00 00 00 00]; 181 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 182 reset-names = "stmmaceth", "stmmaceth-ocp"; 183 tx-fifo-depth = <16384>; 184 rx-fifo-depth = <16384>; 185 snps,multicast-filter-bins = <256>; 186 iommus = <&smmu 3>; 187 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 188 clocks = <&clkmgr AGILEX_EMAC2_CLK>; 189 clock-names = "stmmaceth"; 190 status = "disabled"; 191 }; 192 193 gpio0: gpio@ffc03200 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "snps,dw-apb-gpio"; 197 reg = <0xffc03200 0x100>; 198 resets = <&rst GPIO0_RESET>; 199 status = "disabled"; 200 201 porta: gpio-controller@0 { 202 compatible = "snps,dw-apb-gpio-port"; 203 gpio-controller; 204 #gpio-cells = <2>; 205 snps,nr-gpios = <24>; 206 reg = <0>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 interrupts = <0 110 4>; 210 }; 211 }; 212 213 gpio1: gpio@ffc03300 { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 compatible = "snps,dw-apb-gpio"; 217 reg = <0xffc03300 0x100>; 218 resets = <&rst GPIO1_RESET>; 219 status = "disabled"; 220 221 portb: gpio-controller@0 { 222 compatible = "snps,dw-apb-gpio-port"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 snps,nr-gpios = <24>; 226 reg = <0>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 interrupts = <0 111 4>; 230 }; 231 }; 232 233 i2c0: i2c@ffc02800 { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 compatible = "snps,designware-i2c"; 237 reg = <0xffc02800 0x100>; 238 interrupts = <0 103 4>; 239 resets = <&rst I2C0_RESET>; 240 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 241 status = "disabled"; 242 }; 243 244 i2c1: i2c@ffc02900 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 compatible = "snps,designware-i2c"; 248 reg = <0xffc02900 0x100>; 249 interrupts = <0 104 4>; 250 resets = <&rst I2C1_RESET>; 251 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 252 status = "disabled"; 253 }; 254 255 i2c2: i2c@ffc02a00 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "snps,designware-i2c"; 259 reg = <0xffc02a00 0x100>; 260 interrupts = <0 105 4>; 261 resets = <&rst I2C2_RESET>; 262 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 263 status = "disabled"; 264 }; 265 266 i2c3: i2c@ffc02b00 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "snps,designware-i2c"; 270 reg = <0xffc02b00 0x100>; 271 interrupts = <0 106 4>; 272 resets = <&rst I2C3_RESET>; 273 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 274 status = "disabled"; 275 }; 276 277 i2c4: i2c@ffc02c00 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "snps,designware-i2c"; 281 reg = <0xffc02c00 0x100>; 282 interrupts = <0 107 4>; 283 resets = <&rst I2C4_RESET>; 284 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 285 status = "disabled"; 286 }; 287 288 mmc: dwmmc0@ff808000 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 compatible = "altr,socfpga-dw-mshc"; 292 reg = <0xff808000 0x1000>; 293 interrupts = <0 96 4>; 294 fifo-depth = <0x400>; 295 resets = <&rst SDMMC_RESET>; 296 reset-names = "reset"; 297 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 298 <&clkmgr AGILEX_SDMMC_CLK>; 299 clock-names = "biu", "ciu"; 300 iommus = <&smmu 5>; 301 status = "disabled"; 302 }; 303 304 nand: nand@ffb90000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "altr,socfpga-denali-nand"; 308 reg = <0xffb90000 0x10000>, 309 <0xffb80000 0x1000>; 310 reg-names = "nand_data", "denali_reg"; 311 interrupts = <0 97 4>; 312 clocks = <&clkmgr AGILEX_NAND_CLK>, 313 <&clkmgr AGILEX_NAND_X_CLK>, 314 <&clkmgr AGILEX_NAND_ECC_CLK>; 315 clock-names = "nand", "nand_x", "ecc"; 316 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 317 status = "disabled"; 318 }; 319 320 ocram: sram@ffe00000 { 321 compatible = "mmio-sram"; 322 reg = <0xffe00000 0x40000>; 323 }; 324 325 pdma: pdma@ffda0000 { 326 compatible = "arm,pl330", "arm,primecell"; 327 reg = <0xffda0000 0x1000>; 328 interrupts = <0 81 4>, 329 <0 82 4>, 330 <0 83 4>, 331 <0 84 4>, 332 <0 85 4>, 333 <0 86 4>, 334 <0 87 4>, 335 <0 88 4>, 336 <0 89 4>; 337 #dma-cells = <1>; 338 #dma-channels = <8>; 339 #dma-requests = <32>; 340 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 341 reset-names = "dma", "dma-ocp"; 342 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 343 clock-names = "apb_pclk"; 344 }; 345 346 rst: rstmgr@ffd11000 { 347 #reset-cells = <1>; 348 compatible = "altr,stratix10-rst-mgr"; 349 reg = <0xffd11000 0x100>; 350 }; 351 352 smmu: iommu@fa000000 { 353 compatible = "arm,mmu-500", "arm,smmu-v2"; 354 reg = <0xfa000000 0x40000>; 355 #global-interrupts = <2>; 356 #iommu-cells = <1>; 357 interrupt-parent = <&intc>; 358 interrupts = <0 128 4>, /* Global Secure Fault */ 359 <0 129 4>, /* Global Non-secure Fault */ 360 /* Non-secure Context Interrupts (32) */ 361 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 362 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 363 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 364 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 365 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 366 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 367 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 368 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 369 stream-match-mask = <0x7ff0>; 370 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 371 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 372 <&clkmgr AGILEX_L4_MAIN_CLK>; 373 status = "disabled"; 374 }; 375 376 spi0: spi@ffda4000 { 377 compatible = "snps,dw-apb-ssi"; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 reg = <0xffda4000 0x1000>; 381 interrupts = <0 99 4>; 382 resets = <&rst SPIM0_RESET>; 383 reg-io-width = <4>; 384 num-cs = <4>; 385 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 386 status = "disabled"; 387 }; 388 389 spi1: spi@ffda5000 { 390 compatible = "snps,dw-apb-ssi"; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 reg = <0xffda5000 0x1000>; 394 interrupts = <0 100 4>; 395 resets = <&rst SPIM1_RESET>; 396 reg-io-width = <4>; 397 num-cs = <4>; 398 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 399 status = "disabled"; 400 }; 401 402 sysmgr: sysmgr@ffd12000 { 403 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 404 reg = <0xffd12000 0x500>; 405 }; 406 407 /* Local timer */ 408 timer { 409 compatible = "arm,armv8-timer"; 410 interrupts = <1 13 0xf08>, 411 <1 14 0xf08>, 412 <1 11 0xf08>, 413 <1 10 0xf08>; 414 }; 415 416 timer0: timer0@ffc03000 { 417 compatible = "snps,dw-apb-timer"; 418 interrupts = <0 113 4>; 419 reg = <0xffc03000 0x100>; 420 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 421 clock-names = "timer"; 422 }; 423 424 timer1: timer1@ffc03100 { 425 compatible = "snps,dw-apb-timer"; 426 interrupts = <0 114 4>; 427 reg = <0xffc03100 0x100>; 428 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 429 clock-names = "timer"; 430 }; 431 432 timer2: timer2@ffd00000 { 433 compatible = "snps,dw-apb-timer"; 434 interrupts = <0 115 4>; 435 reg = <0xffd00000 0x100>; 436 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 437 clock-names = "timer"; 438 }; 439 440 timer3: timer3@ffd00100 { 441 compatible = "snps,dw-apb-timer"; 442 interrupts = <0 116 4>; 443 reg = <0xffd00100 0x100>; 444 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 445 clock-names = "timer"; 446 }; 447 448 uart0: serial0@ffc02000 { 449 compatible = "snps,dw-apb-uart"; 450 reg = <0xffc02000 0x100>; 451 interrupts = <0 108 4>; 452 reg-shift = <2>; 453 reg-io-width = <4>; 454 resets = <&rst UART0_RESET>; 455 status = "disabled"; 456 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 457 }; 458 459 uart1: serial1@ffc02100 { 460 compatible = "snps,dw-apb-uart"; 461 reg = <0xffc02100 0x100>; 462 interrupts = <0 109 4>; 463 reg-shift = <2>; 464 reg-io-width = <4>; 465 resets = <&rst UART1_RESET>; 466 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 467 status = "disabled"; 468 }; 469 470 usbphy0: usbphy@0 { 471 #phy-cells = <0>; 472 compatible = "usb-nop-xceiv"; 473 status = "okay"; 474 }; 475 476 usb0: usb@ffb00000 { 477 compatible = "snps,dwc2"; 478 reg = <0xffb00000 0x40000>; 479 interrupts = <0 93 4>; 480 phys = <&usbphy0>; 481 phy-names = "usb2-phy"; 482 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 483 reset-names = "dwc2", "dwc2-ecc"; 484 clocks = <&clkmgr AGILEX_USB_CLK>; 485 iommus = <&smmu 6>; 486 status = "disabled"; 487 }; 488 489 usb1: usb@ffb40000 { 490 compatible = "snps,dwc2"; 491 reg = <0xffb40000 0x40000>; 492 interrupts = <0 94 4>; 493 phys = <&usbphy0>; 494 phy-names = "usb2-phy"; 495 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 496 reset-names = "dwc2", "dwc2-ecc"; 497 iommus = <&smmu 7>; 498 clocks = <&clkmgr AGILEX_USB_CLK>; 499 status = "disabled"; 500 }; 501 502 watchdog0: watchdog@ffd00200 { 503 compatible = "snps,dw-wdt"; 504 reg = <0xffd00200 0x100>; 505 interrupts = <0 117 4>; 506 resets = <&rst WATCHDOG0_RESET>; 507 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 508 status = "disabled"; 509 }; 510 511 watchdog1: watchdog@ffd00300 { 512 compatible = "snps,dw-wdt"; 513 reg = <0xffd00300 0x100>; 514 interrupts = <0 118 4>; 515 resets = <&rst WATCHDOG1_RESET>; 516 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 517 status = "disabled"; 518 }; 519 520 watchdog2: watchdog@ffd00400 { 521 compatible = "snps,dw-wdt"; 522 reg = <0xffd00400 0x100>; 523 interrupts = <0 125 4>; 524 resets = <&rst WATCHDOG2_RESET>; 525 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 526 status = "disabled"; 527 }; 528 529 watchdog3: watchdog@ffd00500 { 530 compatible = "snps,dw-wdt"; 531 reg = <0xffd00500 0x100>; 532 interrupts = <0 126 4>; 533 resets = <&rst WATCHDOG3_RESET>; 534 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 535 status = "disabled"; 536 }; 537 538 sdr: sdr@f8011100 { 539 compatible = "altr,sdr-ctl", "syscon"; 540 reg = <0xf8011100 0xc0>; 541 }; 542 543 eccmgr { 544 compatible = "altr,socfpga-s10-ecc-manager", 545 "altr,socfpga-a10-ecc-manager"; 546 altr,sysmgr-syscon = <&sysmgr>; 547 #address-cells = <1>; 548 #size-cells = <1>; 549 interrupts = <0 15 4>; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 ranges; 553 554 sdramedac { 555 compatible = "altr,sdram-edac-s10"; 556 altr,sdr-syscon = <&sdr>; 557 interrupts = <16 4>; 558 }; 559 560 ocram-ecc@ff8cc000 { 561 compatible = "altr,socfpga-s10-ocram-ecc", 562 "altr,socfpga-a10-ocram-ecc"; 563 reg = <0xff8cc000 0x100>; 564 altr,ecc-parent = <&ocram>; 565 interrupts = <1 4>; 566 }; 567 568 usb0-ecc@ff8c4000 { 569 compatible = "altr,socfpga-s10-usb-ecc", 570 "altr,socfpga-usb-ecc"; 571 reg = <0xff8c4000 0x100>; 572 altr,ecc-parent = <&usb0>; 573 interrupts = <2 4>; 574 }; 575 576 emac0-rx-ecc@ff8c0000 { 577 compatible = "altr,socfpga-s10-eth-mac-ecc", 578 "altr,socfpga-eth-mac-ecc"; 579 reg = <0xff8c0000 0x100>; 580 altr,ecc-parent = <&gmac0>; 581 interrupts = <4 4>; 582 }; 583 584 emac0-tx-ecc@ff8c0400 { 585 compatible = "altr,socfpga-s10-eth-mac-ecc", 586 "altr,socfpga-eth-mac-ecc"; 587 reg = <0xff8c0400 0x100>; 588 altr,ecc-parent = <&gmac0>; 589 interrupts = <5 4>; 590 }; 591 592 sdmmca-ecc@ff8c8c00 { 593 compatible = "altr,socfpga-s10-sdmmc-ecc", 594 "altr,socfpga-sdmmc-ecc"; 595 reg = <0xff8c8c00 0x100>; 596 altr,ecc-parent = <&mmc>; 597 interrupts = <14 4>, 598 <15 4>; 599 }; 600 }; 601 602 qspi: spi@ff8d2000 { 603 compatible = "cdns,qspi-nor"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0xff8d2000 0x100>, 607 <0xff900000 0x100000>; 608 interrupts = <0 3 4>; 609 cdns,fifo-depth = <128>; 610 cdns,fifo-width = <4>; 611 cdns,trigger-address = <0x00000000>; 612 clocks = <&qspi_clk>; 613 614 status = "disabled"; 615 }; 616 617 firmware { 618 svc { 619 compatible = "intel,agilex-svc"; 620 method = "smc"; 621 memory-region = <&service_reserved>; 622 623 fpga_mgr: fpga-mgr { 624 compatible = "intel,agilex-soc-fpga-mgr"; 625 }; 626 }; 627 }; 628 }; 629}; 630