1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/agilex-clock.h> 10 11/ { 12 compatible = "intel,socfpga-agilex"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x1000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x1>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 }; 60 }; 61 62 pmu { 63 compatible = "arm,armv8-pmuv3"; 64 interrupts = <0 170 4>, 65 <0 171 4>, 66 <0 172 4>, 67 <0 173 4>; 68 interrupt-affinity = <&cpu0>, 69 <&cpu1>, 70 <&cpu2>, 71 <&cpu3>; 72 interrupt-parent = <&intc>; 73 }; 74 75 psci { 76 compatible = "arm,psci-0.2"; 77 method = "smc"; 78 }; 79 80 intc: intc@fffc1000 { 81 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0x0 0xfffc1000 0x0 0x1000>, 85 <0x0 0xfffc2000 0x0 0x2000>, 86 <0x0 0xfffc4000 0x0 0x2000>, 87 <0x0 0xfffc6000 0x0 0x2000>; 88 }; 89 90 soc { 91 #address-cells = <1>; 92 #size-cells = <1>; 93 compatible = "simple-bus"; 94 device_type = "soc"; 95 interrupt-parent = <&intc>; 96 ranges = <0 0 0 0xffffffff>; 97 98 base_fpga_region { 99 #address-cells = <0x1>; 100 #size-cells = <0x1>; 101 compatible = "fpga-region"; 102 fpga-mgr = <&fpga_mgr>; 103 }; 104 105 clkmgr: clock-controller@ffd10000 { 106 compatible = "intel,agilex-clkmgr"; 107 reg = <0xffd10000 0x1000>; 108 #clock-cells = <1>; 109 }; 110 111 clocks { 112 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 }; 116 117 cb_intosc_ls_clk: cb-intosc-ls-clk { 118 #clock-cells = <0>; 119 compatible = "fixed-clock"; 120 }; 121 122 f2s_free_clk: f2s-free-clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 }; 126 127 osc1: osc1 { 128 #clock-cells = <0>; 129 compatible = "fixed-clock"; 130 }; 131 132 qspi_clk: qspi-clk { 133 #clock-cells = <0>; 134 compatible = "fixed-clock"; 135 clock-frequency = <200000000>; 136 }; 137 }; 138 139 gmac0: ethernet@ff800000 { 140 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 141 reg = <0xff800000 0x2000>; 142 interrupts = <0 90 4>; 143 interrupt-names = "macirq"; 144 mac-address = [00 00 00 00 00 00]; 145 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 146 reset-names = "stmmaceth", "stmmaceth-ocp"; 147 tx-fifo-depth = <16384>; 148 rx-fifo-depth = <16384>; 149 snps,multicast-filter-bins = <256>; 150 iommus = <&smmu 1>; 151 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 152 clocks = <&clkmgr AGILEX_EMAC0_CLK>; 153 clock-names = "stmmaceth"; 154 status = "disabled"; 155 }; 156 157 gmac1: ethernet@ff802000 { 158 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 159 reg = <0xff802000 0x2000>; 160 interrupts = <0 91 4>; 161 interrupt-names = "macirq"; 162 mac-address = [00 00 00 00 00 00]; 163 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 164 reset-names = "stmmaceth", "stmmaceth-ocp"; 165 tx-fifo-depth = <16384>; 166 rx-fifo-depth = <16384>; 167 snps,multicast-filter-bins = <256>; 168 iommus = <&smmu 2>; 169 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 170 clocks = <&clkmgr AGILEX_EMAC1_CLK>; 171 clock-names = "stmmaceth"; 172 status = "disabled"; 173 }; 174 175 gmac2: ethernet@ff804000 { 176 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 177 reg = <0xff804000 0x2000>; 178 interrupts = <0 92 4>; 179 interrupt-names = "macirq"; 180 mac-address = [00 00 00 00 00 00]; 181 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 182 reset-names = "stmmaceth", "stmmaceth-ocp"; 183 tx-fifo-depth = <16384>; 184 rx-fifo-depth = <16384>; 185 snps,multicast-filter-bins = <256>; 186 iommus = <&smmu 3>; 187 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 188 clocks = <&clkmgr AGILEX_EMAC2_CLK>; 189 clock-names = "stmmaceth"; 190 status = "disabled"; 191 }; 192 193 gpio0: gpio@ffc03200 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "snps,dw-apb-gpio"; 197 reg = <0xffc03200 0x100>; 198 resets = <&rst GPIO0_RESET>; 199 status = "disabled"; 200 201 porta: gpio-controller@0 { 202 compatible = "snps,dw-apb-gpio-port"; 203 gpio-controller; 204 #gpio-cells = <2>; 205 snps,nr-gpios = <24>; 206 reg = <0>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 interrupts = <0 110 4>; 210 }; 211 }; 212 213 gpio1: gpio@ffc03300 { 214 #address-cells = <1>; 215 #size-cells = <0>; 216 compatible = "snps,dw-apb-gpio"; 217 reg = <0xffc03300 0x100>; 218 resets = <&rst GPIO1_RESET>; 219 status = "disabled"; 220 221 portb: gpio-controller@0 { 222 compatible = "snps,dw-apb-gpio-port"; 223 gpio-controller; 224 #gpio-cells = <2>; 225 snps,nr-gpios = <24>; 226 reg = <0>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 interrupts = <0 111 4>; 230 }; 231 }; 232 233 i2c0: i2c@ffc02800 { 234 #address-cells = <1>; 235 #size-cells = <0>; 236 compatible = "snps,designware-i2c"; 237 reg = <0xffc02800 0x100>; 238 interrupts = <0 103 4>; 239 resets = <&rst I2C0_RESET>; 240 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 241 status = "disabled"; 242 }; 243 244 i2c1: i2c@ffc02900 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 compatible = "snps,designware-i2c"; 248 reg = <0xffc02900 0x100>; 249 interrupts = <0 104 4>; 250 resets = <&rst I2C1_RESET>; 251 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 252 status = "disabled"; 253 }; 254 255 i2c2: i2c@ffc02a00 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "snps,designware-i2c"; 259 reg = <0xffc02a00 0x100>; 260 interrupts = <0 105 4>; 261 resets = <&rst I2C2_RESET>; 262 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 263 status = "disabled"; 264 }; 265 266 i2c3: i2c@ffc02b00 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "snps,designware-i2c"; 270 reg = <0xffc02b00 0x100>; 271 interrupts = <0 106 4>; 272 resets = <&rst I2C3_RESET>; 273 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 274 status = "disabled"; 275 }; 276 277 i2c4: i2c@ffc02c00 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "snps,designware-i2c"; 281 reg = <0xffc02c00 0x100>; 282 interrupts = <0 107 4>; 283 resets = <&rst I2C4_RESET>; 284 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 285 status = "disabled"; 286 }; 287 288 mmc: dwmmc0@ff808000 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 compatible = "altr,socfpga-dw-mshc"; 292 reg = <0xff808000 0x1000>; 293 interrupts = <0 96 4>; 294 fifo-depth = <0x400>; 295 resets = <&rst SDMMC_RESET>; 296 reset-names = "reset"; 297 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 298 <&clkmgr AGILEX_SDMMC_CLK>; 299 clock-names = "biu", "ciu"; 300 iommus = <&smmu 5>; 301 status = "disabled"; 302 }; 303 304 nand: nand@ffb90000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "altr,socfpga-denali-nand"; 308 reg = <0xffb90000 0x10000>, 309 <0xffb80000 0x1000>; 310 reg-names = "nand_data", "denali_reg"; 311 interrupts = <0 97 4>; 312 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 313 status = "disabled"; 314 }; 315 316 ocram: sram@ffe00000 { 317 compatible = "mmio-sram"; 318 reg = <0xffe00000 0x40000>; 319 }; 320 321 pdma: pdma@ffda0000 { 322 compatible = "arm,pl330", "arm,primecell"; 323 reg = <0xffda0000 0x1000>; 324 interrupts = <0 81 4>, 325 <0 82 4>, 326 <0 83 4>, 327 <0 84 4>, 328 <0 85 4>, 329 <0 86 4>, 330 <0 87 4>, 331 <0 88 4>, 332 <0 89 4>; 333 #dma-cells = <1>; 334 #dma-channels = <8>; 335 #dma-requests = <32>; 336 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 337 reset-names = "dma", "dma-ocp"; 338 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 339 clock-names = "apb_pclk"; 340 }; 341 342 rst: rstmgr@ffd11000 { 343 #reset-cells = <1>; 344 compatible = "altr,stratix10-rst-mgr"; 345 reg = <0xffd11000 0x100>; 346 }; 347 348 smmu: iommu@fa000000 { 349 compatible = "arm,mmu-500", "arm,smmu-v2"; 350 reg = <0xfa000000 0x40000>; 351 #global-interrupts = <2>; 352 #iommu-cells = <1>; 353 interrupt-parent = <&intc>; 354 interrupts = <0 128 4>, /* Global Secure Fault */ 355 <0 129 4>, /* Global Non-secure Fault */ 356 /* Non-secure Context Interrupts (32) */ 357 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 358 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 359 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 360 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 361 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 362 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 363 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 364 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 365 stream-match-mask = <0x7ff0>; 366 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 367 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 368 <&clkmgr AGILEX_L4_MAIN_CLK>; 369 status = "disabled"; 370 }; 371 372 spi0: spi@ffda4000 { 373 compatible = "snps,dw-apb-ssi"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0xffda4000 0x1000>; 377 interrupts = <0 99 4>; 378 resets = <&rst SPIM0_RESET>; 379 reg-io-width = <4>; 380 num-cs = <4>; 381 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 382 status = "disabled"; 383 }; 384 385 spi1: spi@ffda5000 { 386 compatible = "snps,dw-apb-ssi"; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 reg = <0xffda5000 0x1000>; 390 interrupts = <0 100 4>; 391 resets = <&rst SPIM1_RESET>; 392 reg-io-width = <4>; 393 num-cs = <4>; 394 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 395 status = "disabled"; 396 }; 397 398 sysmgr: sysmgr@ffd12000 { 399 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 400 reg = <0xffd12000 0x500>; 401 }; 402 403 /* Local timer */ 404 timer { 405 compatible = "arm,armv8-timer"; 406 interrupts = <1 13 0xf08>, 407 <1 14 0xf08>, 408 <1 11 0xf08>, 409 <1 10 0xf08>; 410 }; 411 412 timer0: timer0@ffc03000 { 413 compatible = "snps,dw-apb-timer"; 414 interrupts = <0 113 4>; 415 reg = <0xffc03000 0x100>; 416 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 417 clock-names = "timer"; 418 }; 419 420 timer1: timer1@ffc03100 { 421 compatible = "snps,dw-apb-timer"; 422 interrupts = <0 114 4>; 423 reg = <0xffc03100 0x100>; 424 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 425 clock-names = "timer"; 426 }; 427 428 timer2: timer2@ffd00000 { 429 compatible = "snps,dw-apb-timer"; 430 interrupts = <0 115 4>; 431 reg = <0xffd00000 0x100>; 432 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 433 clock-names = "timer"; 434 }; 435 436 timer3: timer3@ffd00100 { 437 compatible = "snps,dw-apb-timer"; 438 interrupts = <0 116 4>; 439 reg = <0xffd00100 0x100>; 440 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 441 clock-names = "timer"; 442 }; 443 444 uart0: serial0@ffc02000 { 445 compatible = "snps,dw-apb-uart"; 446 reg = <0xffc02000 0x100>; 447 interrupts = <0 108 4>; 448 reg-shift = <2>; 449 reg-io-width = <4>; 450 resets = <&rst UART0_RESET>; 451 status = "disabled"; 452 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 453 }; 454 455 uart1: serial1@ffc02100 { 456 compatible = "snps,dw-apb-uart"; 457 reg = <0xffc02100 0x100>; 458 interrupts = <0 109 4>; 459 reg-shift = <2>; 460 reg-io-width = <4>; 461 resets = <&rst UART1_RESET>; 462 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 463 status = "disabled"; 464 }; 465 466 usbphy0: usbphy@0 { 467 #phy-cells = <0>; 468 compatible = "usb-nop-xceiv"; 469 status = "okay"; 470 }; 471 472 usb0: usb@ffb00000 { 473 compatible = "snps,dwc2"; 474 reg = <0xffb00000 0x40000>; 475 interrupts = <0 93 4>; 476 phys = <&usbphy0>; 477 phy-names = "usb2-phy"; 478 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 479 reset-names = "dwc2", "dwc2-ecc"; 480 clocks = <&clkmgr AGILEX_USB_CLK>; 481 iommus = <&smmu 6>; 482 status = "disabled"; 483 }; 484 485 usb1: usb@ffb40000 { 486 compatible = "snps,dwc2"; 487 reg = <0xffb40000 0x40000>; 488 interrupts = <0 94 4>; 489 phys = <&usbphy0>; 490 phy-names = "usb2-phy"; 491 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 492 reset-names = "dwc2", "dwc2-ecc"; 493 iommus = <&smmu 7>; 494 clocks = <&clkmgr AGILEX_USB_CLK>; 495 status = "disabled"; 496 }; 497 498 watchdog0: watchdog@ffd00200 { 499 compatible = "snps,dw-wdt"; 500 reg = <0xffd00200 0x100>; 501 interrupts = <0 117 4>; 502 resets = <&rst WATCHDOG0_RESET>; 503 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 504 status = "disabled"; 505 }; 506 507 watchdog1: watchdog@ffd00300 { 508 compatible = "snps,dw-wdt"; 509 reg = <0xffd00300 0x100>; 510 interrupts = <0 118 4>; 511 resets = <&rst WATCHDOG1_RESET>; 512 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 513 status = "disabled"; 514 }; 515 516 watchdog2: watchdog@ffd00400 { 517 compatible = "snps,dw-wdt"; 518 reg = <0xffd00400 0x100>; 519 interrupts = <0 125 4>; 520 resets = <&rst WATCHDOG2_RESET>; 521 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 522 status = "disabled"; 523 }; 524 525 watchdog3: watchdog@ffd00500 { 526 compatible = "snps,dw-wdt"; 527 reg = <0xffd00500 0x100>; 528 interrupts = <0 126 4>; 529 resets = <&rst WATCHDOG3_RESET>; 530 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 531 status = "disabled"; 532 }; 533 534 sdr: sdr@f8011100 { 535 compatible = "altr,sdr-ctl", "syscon"; 536 reg = <0xf8011100 0xc0>; 537 }; 538 539 eccmgr { 540 compatible = "altr,socfpga-s10-ecc-manager", 541 "altr,socfpga-a10-ecc-manager"; 542 altr,sysmgr-syscon = <&sysmgr>; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 interrupts = <0 15 4>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 ranges; 549 550 sdramedac { 551 compatible = "altr,sdram-edac-s10"; 552 altr,sdr-syscon = <&sdr>; 553 interrupts = <16 4>; 554 }; 555 556 ocram-ecc@ff8cc000 { 557 compatible = "altr,socfpga-s10-ocram-ecc", 558 "altr,socfpga-a10-ocram-ecc"; 559 reg = <0xff8cc000 0x100>; 560 altr,ecc-parent = <&ocram>; 561 interrupts = <1 4>; 562 }; 563 564 usb0-ecc@ff8c4000 { 565 compatible = "altr,socfpga-s10-usb-ecc", 566 "altr,socfpga-usb-ecc"; 567 reg = <0xff8c4000 0x100>; 568 altr,ecc-parent = <&usb0>; 569 interrupts = <2 4>; 570 }; 571 572 emac0-rx-ecc@ff8c0000 { 573 compatible = "altr,socfpga-s10-eth-mac-ecc", 574 "altr,socfpga-eth-mac-ecc"; 575 reg = <0xff8c0000 0x100>; 576 altr,ecc-parent = <&gmac0>; 577 interrupts = <4 4>; 578 }; 579 580 emac0-tx-ecc@ff8c0400 { 581 compatible = "altr,socfpga-s10-eth-mac-ecc", 582 "altr,socfpga-eth-mac-ecc"; 583 reg = <0xff8c0400 0x100>; 584 altr,ecc-parent = <&gmac0>; 585 interrupts = <5 4>; 586 }; 587 588 sdmmca-ecc@ff8c8c00 { 589 compatible = "altr,socfpga-s10-sdmmc-ecc", 590 "altr,socfpga-sdmmc-ecc"; 591 reg = <0xff8c8c00 0x100>; 592 altr,ecc-parent = <&mmc>; 593 interrupts = <14 4>, 594 <15 4>; 595 }; 596 }; 597 598 qspi: spi@ff8d2000 { 599 compatible = "cdns,qspi-nor"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 reg = <0xff8d2000 0x100>, 603 <0xff900000 0x100000>; 604 interrupts = <0 3 4>; 605 cdns,fifo-depth = <128>; 606 cdns,fifo-width = <4>; 607 cdns,trigger-address = <0x00000000>; 608 clocks = <&qspi_clk>; 609 610 status = "disabled"; 611 }; 612 613 firmware { 614 svc { 615 compatible = "intel,agilex-svc"; 616 method = "smc"; 617 memory-region = <&service_reserved>; 618 619 fpga_mgr: fpga-mgr { 620 compatible = "intel,agilex-soc-fpga-mgr"; 621 }; 622 }; 623 }; 624 }; 625}; 626