1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 compatible = "intel,socfpga-agilex"; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 reserved-memory { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 ranges; 19 20 service_reserved: svcbuffer@0 { 21 compatible = "shared-dma-pool"; 22 reg = <0x0 0x0 0x0 0x1000000>; 23 alignment = <0x1000>; 24 no-map; 25 }; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "arm,cortex-a53"; 34 device_type = "cpu"; 35 enable-method = "psci"; 36 reg = <0x0>; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "arm,cortex-a53"; 41 device_type = "cpu"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 }; 45 46 cpu2: cpu@2 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 reg = <0x2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 reg = <0x3>; 58 }; 59 }; 60 61 pmu { 62 compatible = "arm,armv8-pmuv3"; 63 interrupts = <0 120 8>, 64 <0 121 8>, 65 <0 122 8>, 66 <0 123 8>; 67 interrupt-affinity = <&cpu0>, 68 <&cpu1>, 69 <&cpu2>, 70 <&cpu3>; 71 interrupt-parent = <&intc>; 72 }; 73 74 psci { 75 compatible = "arm,psci-0.2"; 76 method = "smc"; 77 }; 78 79 intc: intc@fffc1000 { 80 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 81 #interrupt-cells = <3>; 82 interrupt-controller; 83 reg = <0x0 0xfffc1000 0x0 0x1000>, 84 <0x0 0xfffc2000 0x0 0x2000>, 85 <0x0 0xfffc4000 0x0 0x2000>, 86 <0x0 0xfffc6000 0x0 0x2000>; 87 }; 88 89 soc { 90 #address-cells = <1>; 91 #size-cells = <1>; 92 compatible = "simple-bus"; 93 device_type = "soc"; 94 interrupt-parent = <&intc>; 95 ranges = <0 0 0 0xffffffff>; 96 97 base_fpga_region { 98 #address-cells = <0x1>; 99 #size-cells = <0x1>; 100 compatible = "fpga-region"; 101 fpga-mgr = <&fpga_mgr>; 102 }; 103 104 gmac0: ethernet@ff800000 { 105 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 106 reg = <0xff800000 0x2000>; 107 interrupts = <0 90 4>; 108 interrupt-names = "macirq"; 109 mac-address = [00 00 00 00 00 00]; 110 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 111 reset-names = "stmmaceth", "stmmaceth-ocp"; 112 tx-fifo-depth = <16384>; 113 rx-fifo-depth = <16384>; 114 snps,multicast-filter-bins = <256>; 115 iommus = <&smmu 1>; 116 status = "disabled"; 117 }; 118 119 gmac1: ethernet@ff802000 { 120 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 121 reg = <0xff802000 0x2000>; 122 interrupts = <0 91 4>; 123 interrupt-names = "macirq"; 124 mac-address = [00 00 00 00 00 00]; 125 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 126 reset-names = "stmmaceth", "stmmaceth-ocp"; 127 tx-fifo-depth = <16384>; 128 rx-fifo-depth = <16384>; 129 snps,multicast-filter-bins = <256>; 130 iommus = <&smmu 2>; 131 status = "disabled"; 132 }; 133 134 gmac2: ethernet@ff804000 { 135 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 136 reg = <0xff804000 0x2000>; 137 interrupts = <0 92 4>; 138 interrupt-names = "macirq"; 139 mac-address = [00 00 00 00 00 00]; 140 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 141 reset-names = "stmmaceth", "stmmaceth-ocp"; 142 tx-fifo-depth = <16384>; 143 rx-fifo-depth = <16384>; 144 snps,multicast-filter-bins = <256>; 145 iommus = <&smmu 3>; 146 status = "disabled"; 147 }; 148 149 gpio0: gpio@ffc03200 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 compatible = "snps,dw-apb-gpio"; 153 reg = <0xffc03200 0x100>; 154 resets = <&rst GPIO0_RESET>; 155 status = "disabled"; 156 157 porta: gpio-controller@0 { 158 compatible = "snps,dw-apb-gpio-port"; 159 gpio-controller; 160 #gpio-cells = <2>; 161 snps,nr-gpios = <24>; 162 reg = <0>; 163 interrupt-controller; 164 #interrupt-cells = <2>; 165 interrupts = <0 110 4>; 166 }; 167 }; 168 169 gpio1: gpio@ffc03300 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "snps,dw-apb-gpio"; 173 reg = <0xffc03300 0x100>; 174 resets = <&rst GPIO1_RESET>; 175 status = "disabled"; 176 177 portb: gpio-controller@0 { 178 compatible = "snps,dw-apb-gpio-port"; 179 gpio-controller; 180 #gpio-cells = <2>; 181 snps,nr-gpios = <24>; 182 reg = <0>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 interrupts = <0 111 4>; 186 }; 187 }; 188 189 i2c0: i2c@ffc02800 { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 compatible = "snps,designware-i2c"; 193 reg = <0xffc02800 0x100>; 194 interrupts = <0 103 4>; 195 resets = <&rst I2C0_RESET>; 196 status = "disabled"; 197 }; 198 199 i2c1: i2c@ffc02900 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 compatible = "snps,designware-i2c"; 203 reg = <0xffc02900 0x100>; 204 interrupts = <0 104 4>; 205 resets = <&rst I2C1_RESET>; 206 status = "disabled"; 207 }; 208 209 i2c2: i2c@ffc02a00 { 210 #address-cells = <1>; 211 #size-cells = <0>; 212 compatible = "snps,designware-i2c"; 213 reg = <0xffc02a00 0x100>; 214 interrupts = <0 105 4>; 215 resets = <&rst I2C2_RESET>; 216 status = "disabled"; 217 }; 218 219 i2c3: i2c@ffc02b00 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 compatible = "snps,designware-i2c"; 223 reg = <0xffc02b00 0x100>; 224 interrupts = <0 106 4>; 225 resets = <&rst I2C3_RESET>; 226 status = "disabled"; 227 }; 228 229 i2c4: i2c@ffc02c00 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "snps,designware-i2c"; 233 reg = <0xffc02c00 0x100>; 234 interrupts = <0 107 4>; 235 resets = <&rst I2C4_RESET>; 236 status = "disabled"; 237 }; 238 239 mmc: dwmmc0@ff808000 { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 compatible = "altr,socfpga-dw-mshc"; 243 reg = <0xff808000 0x1000>; 244 interrupts = <0 96 4>; 245 fifo-depth = <0x400>; 246 resets = <&rst SDMMC_RESET>; 247 reset-names = "reset"; 248 iommus = <&smmu 5>; 249 status = "disabled"; 250 }; 251 252 nand: nand@ffb90000 { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 compatible = "altr,socfpga-denali-nand"; 256 reg = <0xffb90000 0x10000>, 257 <0xffb80000 0x1000>; 258 reg-names = "nand_data", "denali_reg"; 259 interrupts = <0 97 4>; 260 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 261 status = "disabled"; 262 }; 263 264 ocram: sram@ffe00000 { 265 compatible = "mmio-sram"; 266 reg = <0xffe00000 0x40000>; 267 }; 268 269 pdma: pdma@ffda0000 { 270 compatible = "arm,pl330", "arm,primecell"; 271 reg = <0xffda0000 0x1000>; 272 interrupts = <0 81 4>, 273 <0 82 4>, 274 <0 83 4>, 275 <0 84 4>, 276 <0 85 4>, 277 <0 86 4>, 278 <0 87 4>, 279 <0 88 4>, 280 <0 89 4>; 281 #dma-cells = <1>; 282 #dma-channels = <8>; 283 #dma-requests = <32>; 284 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 285 reset-names = "dma", "dma-ocp"; 286 }; 287 288 rst: rstmgr@ffd11000 { 289 #reset-cells = <1>; 290 compatible = "altr,stratix10-rst-mgr"; 291 reg = <0xffd11000 0x100>; 292 }; 293 294 smmu: iommu@fa000000 { 295 compatible = "arm,mmu-500", "arm,smmu-v2"; 296 reg = <0xfa000000 0x40000>; 297 #global-interrupts = <2>; 298 #iommu-cells = <1>; 299 interrupt-parent = <&intc>; 300 interrupts = <0 128 4>, /* Global Secure Fault */ 301 <0 129 4>, /* Global Non-secure Fault */ 302 /* Non-secure Context Interrupts (32) */ 303 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 304 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 305 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 306 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 307 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 308 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 309 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 310 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 311 stream-match-mask = <0x7ff0>; 312 status = "disabled"; 313 }; 314 315 spi0: spi@ffda4000 { 316 compatible = "snps,dw-apb-ssi"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <0xffda4000 0x1000>; 320 interrupts = <0 99 4>; 321 resets = <&rst SPIM0_RESET>; 322 reg-io-width = <4>; 323 num-cs = <4>; 324 status = "disabled"; 325 }; 326 327 spi1: spi@ffda5000 { 328 compatible = "snps,dw-apb-ssi"; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 reg = <0xffda5000 0x1000>; 332 interrupts = <0 100 4>; 333 resets = <&rst SPIM1_RESET>; 334 reg-io-width = <4>; 335 num-cs = <4>; 336 status = "disabled"; 337 }; 338 339 sysmgr: sysmgr@ffd12000 { 340 compatible = "altr,sys-mgr", "syscon"; 341 reg = <0xffd12000 0x500>; 342 }; 343 344 /* Local timer */ 345 timer { 346 compatible = "arm,armv8-timer"; 347 interrupts = <1 13 0xf08>, 348 <1 14 0xf08>, 349 <1 11 0xf08>, 350 <1 10 0xf08>; 351 }; 352 353 timer0: timer0@ffc03000 { 354 compatible = "snps,dw-apb-timer"; 355 interrupts = <0 113 4>; 356 reg = <0xffc03000 0x100>; 357 }; 358 359 timer1: timer1@ffc03100 { 360 compatible = "snps,dw-apb-timer"; 361 interrupts = <0 114 4>; 362 reg = <0xffc03100 0x100>; 363 }; 364 365 timer2: timer2@ffd00000 { 366 compatible = "snps,dw-apb-timer"; 367 interrupts = <0 115 4>; 368 reg = <0xffd00000 0x100>; 369 }; 370 371 timer3: timer3@ffd00100 { 372 compatible = "snps,dw-apb-timer"; 373 interrupts = <0 116 4>; 374 reg = <0xffd00100 0x100>; 375 }; 376 377 uart0: serial0@ffc02000 { 378 compatible = "snps,dw-apb-uart"; 379 reg = <0xffc02000 0x100>; 380 interrupts = <0 108 4>; 381 reg-shift = <2>; 382 reg-io-width = <4>; 383 resets = <&rst UART0_RESET>; 384 status = "disabled"; 385 }; 386 387 uart1: serial1@ffc02100 { 388 compatible = "snps,dw-apb-uart"; 389 reg = <0xffc02100 0x100>; 390 interrupts = <0 109 4>; 391 reg-shift = <2>; 392 reg-io-width = <4>; 393 resets = <&rst UART1_RESET>; 394 status = "disabled"; 395 }; 396 397 usbphy0: usbphy@0 { 398 #phy-cells = <0>; 399 compatible = "usb-nop-xceiv"; 400 status = "okay"; 401 }; 402 403 usb0: usb@ffb00000 { 404 compatible = "snps,dwc2"; 405 reg = <0xffb00000 0x40000>; 406 interrupts = <0 93 4>; 407 phys = <&usbphy0>; 408 phy-names = "usb2-phy"; 409 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 410 reset-names = "dwc2", "dwc2-ecc"; 411 iommus = <&smmu 6>; 412 status = "disabled"; 413 }; 414 415 usb1: usb@ffb40000 { 416 compatible = "snps,dwc2"; 417 reg = <0xffb40000 0x40000>; 418 interrupts = <0 94 4>; 419 phys = <&usbphy0>; 420 phy-names = "usb2-phy"; 421 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 422 reset-names = "dwc2", "dwc2-ecc"; 423 iommus = <&smmu 7>; 424 status = "disabled"; 425 }; 426 427 watchdog0: watchdog@ffd00200 { 428 compatible = "snps,dw-wdt"; 429 reg = <0xffd00200 0x100>; 430 interrupts = <0 117 4>; 431 resets = <&rst WATCHDOG0_RESET>; 432 status = "disabled"; 433 }; 434 435 watchdog1: watchdog@ffd00300 { 436 compatible = "snps,dw-wdt"; 437 reg = <0xffd00300 0x100>; 438 interrupts = <0 118 4>; 439 resets = <&rst WATCHDOG1_RESET>; 440 status = "disabled"; 441 }; 442 443 watchdog2: watchdog@ffd00400 { 444 compatible = "snps,dw-wdt"; 445 reg = <0xffd00400 0x100>; 446 interrupts = <0 125 4>; 447 resets = <&rst WATCHDOG2_RESET>; 448 status = "disabled"; 449 }; 450 451 watchdog3: watchdog@ffd00500 { 452 compatible = "snps,dw-wdt"; 453 reg = <0xffd00500 0x100>; 454 interrupts = <0 126 4>; 455 resets = <&rst WATCHDOG3_RESET>; 456 status = "disabled"; 457 }; 458 459 sdr: sdr@f8011100 { 460 compatible = "altr,sdr-ctl", "syscon"; 461 reg = <0xf8011100 0xc0>; 462 }; 463 464 eccmgr { 465 compatible = "altr,socfpga-s10-ecc-manager", 466 "altr,socfpga-a10-ecc-manager"; 467 altr,sysmgr-syscon = <&sysmgr>; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 interrupts = <0 15 4>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 ranges; 474 475 sdramedac { 476 compatible = "altr,sdram-edac-s10"; 477 altr,sdr-syscon = <&sdr>; 478 interrupts = <16 4>; 479 }; 480 481 ocram-ecc@ff8cc000 { 482 compatible = "altr,socfpga-s10-ocram-ecc", 483 "altr,socfpga-a10-ocram-ecc"; 484 reg = <0xff8cc000 0x100>; 485 altr,ecc-parent = <&ocram>; 486 interrupts = <1 4>; 487 }; 488 489 usb0-ecc@ff8c4000 { 490 compatible = "altr,socfpga-s10-usb-ecc", 491 "altr,socfpga-usb-ecc"; 492 reg = <0xff8c4000 0x100>; 493 altr,ecc-parent = <&usb0>; 494 interrupts = <2 4>; 495 }; 496 497 emac0-rx-ecc@ff8c0000 { 498 compatible = "altr,socfpga-s10-eth-mac-ecc", 499 "altr,socfpga-eth-mac-ecc"; 500 reg = <0xff8c0000 0x100>; 501 altr,ecc-parent = <&gmac0>; 502 interrupts = <4 4>; 503 }; 504 505 emac0-tx-ecc@ff8c0400 { 506 compatible = "altr,socfpga-s10-eth-mac-ecc", 507 "altr,socfpga-eth-mac-ecc"; 508 reg = <0xff8c0400 0x100>; 509 altr,ecc-parent = <&gmac0>; 510 interrupts = <5 4>; 511 }; 512 513 sdmmca-ecc@ff8c8c00 { 514 compatible = "altr,socfpga-s10-sdmmc-ecc", 515 "altr,socfpga-sdmmc-ecc"; 516 reg = <0xff8c8c00 0x100>; 517 altr,ecc-parent = <&mmc>; 518 interrupts = <14 4>, 519 <15 4>; 520 }; 521 }; 522 523 qspi: spi@ff8d2000 { 524 compatible = "cdns,qspi-nor"; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 reg = <0xff8d2000 0x100>, 528 <0xff900000 0x100000>; 529 interrupts = <0 3 4>; 530 cdns,fifo-depth = <128>; 531 cdns,fifo-width = <4>; 532 cdns,trigger-address = <0x00000000>; 533 534 status = "disabled"; 535 }; 536 537 firmware { 538 svc { 539 compatible = "intel,stratix10-svc"; 540 method = "smc"; 541 memory-region = <&service_reserved>; 542 543 fpga_mgr: fpga-mgr { 544 compatible = "intel,stratix10-soc-fpga-mgr"; 545 }; 546 }; 547 }; 548 }; 549}; 550