1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &lsio_gpio0; 21 gpio1 = &lsio_gpio1; 22 gpio2 = &lsio_gpio2; 23 gpio3 = &lsio_gpio3; 24 gpio4 = &lsio_gpio4; 25 gpio5 = &lsio_gpio5; 26 gpio6 = &lsio_gpio6; 27 gpio7 = &lsio_gpio7; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 mmc2 = &usdhc3; 31 serial0 = &adma_lpuart0; 32 mu1 = &lsio_mu1; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 /* We have 1 clusters with 4 Cortex-A35 cores */ 40 A35_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&A35_L2>; 46 clocks = <&clk IMX_A35_CLK>; 47 operating-points-v2 = <&a35_opp_table>; 48 #cooling-cells = <2>; 49 }; 50 51 A35_1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35"; 54 reg = <0x0 0x1>; 55 enable-method = "psci"; 56 next-level-cache = <&A35_L2>; 57 clocks = <&clk IMX_A35_CLK>; 58 operating-points-v2 = <&a35_opp_table>; 59 #cooling-cells = <2>; 60 }; 61 62 A35_2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a35"; 65 reg = <0x0 0x2>; 66 enable-method = "psci"; 67 next-level-cache = <&A35_L2>; 68 clocks = <&clk IMX_A35_CLK>; 69 operating-points-v2 = <&a35_opp_table>; 70 #cooling-cells = <2>; 71 }; 72 73 A35_3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a35"; 76 reg = <0x0 0x3>; 77 enable-method = "psci"; 78 next-level-cache = <&A35_L2>; 79 clocks = <&clk IMX_A35_CLK>; 80 operating-points-v2 = <&a35_opp_table>; 81 #cooling-cells = <2>; 82 }; 83 84 A35_L2: l2-cache0 { 85 compatible = "cache"; 86 }; 87 }; 88 89 a35_opp_table: opp-table { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-900000000 { 94 opp-hz = /bits/ 64 <900000000>; 95 opp-microvolt = <1000000>; 96 clock-latency-ns = <150000>; 97 }; 98 99 opp-1200000000 { 100 opp-hz = /bits/ 64 <1200000000>; 101 opp-microvolt = <1100000>; 102 clock-latency-ns = <150000>; 103 opp-suspend; 104 }; 105 }; 106 107 gic: interrupt-controller@51a00000 { 108 compatible = "arm,gic-v3"; 109 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 110 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 116 pmu { 117 compatible = "arm,armv8-pmuv3"; 118 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 psci { 122 compatible = "arm,psci-1.0"; 123 method = "smc"; 124 }; 125 126 scu { 127 compatible = "fsl,imx-scu"; 128 mbox-names = "tx0", "tx1", "tx2", "tx3", 129 "rx0", "rx1", "rx2", "rx3", 130 "gip3"; 131 mboxes = <&lsio_mu1 0 0 132 &lsio_mu1 0 1 133 &lsio_mu1 0 2 134 &lsio_mu1 0 3 135 &lsio_mu1 1 0 136 &lsio_mu1 1 1 137 &lsio_mu1 1 2 138 &lsio_mu1 1 3 139 &lsio_mu1 3 3>; 140 141 clk: clock-controller { 142 compatible = "fsl,imx8qxp-clk"; 143 #clock-cells = <1>; 144 clocks = <&xtal32k &xtal24m>; 145 clock-names = "xtal_32KHz", "xtal_24Mhz"; 146 }; 147 148 iomuxc: pinctrl { 149 compatible = "fsl,imx8qxp-iomuxc"; 150 }; 151 152 pd: imx8qx-pd { 153 compatible = "fsl,imx8qxp-scu-pd"; 154 #power-domain-cells = <1>; 155 }; 156 157 rtc: rtc { 158 compatible = "fsl,imx8qxp-sc-rtc"; 159 }; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 165 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 166 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 167 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 168 }; 169 170 xtal32k: clock-xtal32k { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <32768>; 174 clock-output-names = "xtal_32KHz"; 175 }; 176 177 xtal24m: clock-xtal24m { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <24000000>; 181 clock-output-names = "xtal_24MHz"; 182 }; 183 184 adma_subsys: bus@59000000 { 185 compatible = "simple-bus"; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 189 190 adma_lpcg: clock-controller@59000000 { 191 compatible = "fsl,imx8qxp-lpcg-adma"; 192 reg = <0x59000000 0x2000000>; 193 #clock-cells = <1>; 194 }; 195 196 adma_lpuart0: serial@5a060000 { 197 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 198 reg = <0x5a060000 0x1000>; 199 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-parent = <&gic>; 201 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 202 clock-names = "ipg"; 203 power-domains = <&pd IMX_SC_R_UART_0>; 204 status = "disabled"; 205 }; 206 207 adma_lpuart1: serial@5a070000 { 208 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 209 reg = <0x5a070000 0x1000>; 210 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-parent = <&gic>; 212 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 213 clock-names = "ipg"; 214 power-domains = <&pd IMX_SC_R_UART_1>; 215 status = "disabled"; 216 }; 217 218 adma_lpuart2: serial@5a080000 { 219 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 220 reg = <0x5a080000 0x1000>; 221 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 222 interrupt-parent = <&gic>; 223 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 224 clock-names = "ipg"; 225 power-domains = <&pd IMX_SC_R_UART_2>; 226 status = "disabled"; 227 }; 228 229 adma_lpuart3: serial@5a090000 { 230 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 231 reg = <0x5a090000 0x1000>; 232 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-parent = <&gic>; 234 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 235 clock-names = "ipg"; 236 power-domains = <&pd IMX_SC_R_UART_3>; 237 status = "disabled"; 238 }; 239 240 adma_i2c0: i2c@5a800000 { 241 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 242 reg = <0x5a800000 0x4000>; 243 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 244 interrupt-parent = <&gic>; 245 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 246 clock-names = "per"; 247 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 248 assigned-clock-rates = <24000000>; 249 power-domains = <&pd IMX_SC_R_I2C_0>; 250 status = "disabled"; 251 }; 252 253 adma_i2c1: i2c@5a810000 { 254 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 255 reg = <0x5a810000 0x4000>; 256 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-parent = <&gic>; 258 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 259 clock-names = "per"; 260 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 261 assigned-clock-rates = <24000000>; 262 power-domains = <&pd IMX_SC_R_I2C_1>; 263 status = "disabled"; 264 }; 265 266 adma_i2c2: i2c@5a820000 { 267 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 268 reg = <0x5a820000 0x4000>; 269 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-parent = <&gic>; 271 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 272 clock-names = "per"; 273 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 274 assigned-clock-rates = <24000000>; 275 power-domains = <&pd IMX_SC_R_I2C_2>; 276 status = "disabled"; 277 }; 278 279 adma_i2c3: i2c@5a830000 { 280 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 281 reg = <0x5a830000 0x4000>; 282 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-parent = <&gic>; 284 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 285 clock-names = "per"; 286 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 287 assigned-clock-rates = <24000000>; 288 power-domains = <&pd IMX_SC_R_I2C_3>; 289 status = "disabled"; 290 }; 291 }; 292 293 conn_subsys: bus@5b000000 { 294 compatible = "simple-bus"; 295 #address-cells = <1>; 296 #size-cells = <1>; 297 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 298 299 conn_lpcg: clock-controller@5b200000 { 300 compatible = "fsl,imx8qxp-lpcg-conn"; 301 reg = <0x5b200000 0xb0000>; 302 #clock-cells = <1>; 303 }; 304 305 usdhc1: mmc@5b010000 { 306 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 309 reg = <0x5b010000 0x10000>; 310 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 311 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 312 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 313 clock-names = "ipg", "per", "ahb"; 314 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 315 assigned-clock-rates = <200000000>; 316 power-domains = <&pd IMX_SC_R_SDHC_0>; 317 status = "disabled"; 318 }; 319 320 usdhc2: mmc@5b020000 { 321 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 322 interrupt-parent = <&gic>; 323 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 324 reg = <0x5b020000 0x10000>; 325 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 326 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 327 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 328 clock-names = "ipg", "per", "ahb"; 329 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 330 assigned-clock-rates = <200000000>; 331 power-domains = <&pd IMX_SC_R_SDHC_1>; 332 fsl,tuning-start-tap = <20>; 333 fsl,tuning-step= <2>; 334 status = "disabled"; 335 }; 336 337 usdhc3: mmc@5b030000 { 338 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 339 interrupt-parent = <&gic>; 340 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 341 reg = <0x5b030000 0x10000>; 342 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 343 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 344 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 345 clock-names = "ipg", "per", "ahb"; 346 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 347 assigned-clock-rates = <200000000>; 348 power-domains = <&pd IMX_SC_R_SDHC_2>; 349 status = "disabled"; 350 }; 351 352 fec1: ethernet@5b040000 { 353 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 354 reg = <0x5b040000 0x10000>; 355 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 360 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 361 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 362 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 363 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 364 fsl,num-tx-queues=<3>; 365 fsl,num-rx-queues=<3>; 366 power-domains = <&pd IMX_SC_R_ENET_0>; 367 status = "disabled"; 368 }; 369 370 fec2: ethernet@5b050000 { 371 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 372 reg = <0x5b050000 0x10000>; 373 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 378 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 379 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 380 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 381 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 382 fsl,num-tx-queues=<3>; 383 fsl,num-rx-queues=<3>; 384 power-domains = <&pd IMX_SC_R_ENET_1>; 385 status = "disabled"; 386 }; 387 }; 388 389 lsio_subsys: bus@5d000000 { 390 compatible = "simple-bus"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 394 395 lsio_lpcg: clock-controller@5d400000 { 396 compatible = "fsl,imx8qxp-lpcg-lsio"; 397 reg = <0x5d400000 0x400000>; 398 #clock-cells = <1>; 399 }; 400 401 lsio_mu0: mailbox@5d1b0000 { 402 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 403 reg = <0x5d1b0000 0x10000>; 404 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 405 #mbox-cells = <2>; 406 status = "disabled"; 407 }; 408 409 lsio_mu1: mailbox@5d1c0000 { 410 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 411 reg = <0x5d1c0000 0x10000>; 412 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 413 #mbox-cells = <2>; 414 }; 415 416 lsio_mu2: mailbox@5d1d0000 { 417 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 418 reg = <0x5d1d0000 0x10000>; 419 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 420 #mbox-cells = <2>; 421 status = "disabled"; 422 }; 423 424 lsio_mu3: mailbox@5d1e0000 { 425 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 426 reg = <0x5d1e0000 0x10000>; 427 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 428 #mbox-cells = <2>; 429 status = "disabled"; 430 }; 431 432 lsio_mu4: mailbox@5d1f0000 { 433 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 434 reg = <0x5d1f0000 0x10000>; 435 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 436 #mbox-cells = <2>; 437 status = "disabled"; 438 }; 439 440 lsio_gpio0: gpio@5d080000 { 441 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 442 reg = <0x5d080000 0x10000>; 443 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 power-domains = <&pd IMX_SC_R_GPIO_0>; 449 }; 450 451 lsio_gpio1: gpio@5d090000 { 452 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 453 reg = <0x5d090000 0x10000>; 454 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 455 gpio-controller; 456 #gpio-cells = <2>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 power-domains = <&pd IMX_SC_R_GPIO_1>; 460 }; 461 462 lsio_gpio2: gpio@5d0a0000 { 463 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 464 reg = <0x5d0a0000 0x10000>; 465 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 power-domains = <&pd IMX_SC_R_GPIO_2>; 471 }; 472 473 lsio_gpio3: gpio@5d0b0000 { 474 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 475 reg = <0x5d0b0000 0x10000>; 476 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 power-domains = <&pd IMX_SC_R_GPIO_3>; 482 }; 483 484 lsio_gpio4: gpio@5d0c0000 { 485 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 486 reg = <0x5d0c0000 0x10000>; 487 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 488 gpio-controller; 489 #gpio-cells = <2>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 power-domains = <&pd IMX_SC_R_GPIO_4>; 493 }; 494 495 lsio_gpio5: gpio@5d0d0000 { 496 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 497 reg = <0x5d0d0000 0x10000>; 498 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 power-domains = <&pd IMX_SC_R_GPIO_5>; 504 }; 505 506 lsio_gpio6: gpio@5d0e0000 { 507 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 508 reg = <0x5d0e0000 0x10000>; 509 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 510 gpio-controller; 511 #gpio-cells = <2>; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 power-domains = <&pd IMX_SC_R_GPIO_6>; 515 }; 516 517 lsio_gpio7: gpio@5d0f0000 { 518 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 519 reg = <0x5d0f0000 0x10000>; 520 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 521 gpio-controller; 522 #gpio-cells = <2>; 523 interrupt-controller; 524 #interrupt-cells = <2>; 525 power-domains = <&pd IMX_SC_R_GPIO_7>; 526 }; 527 }; 528 529 watchdog { 530 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 531 timeout-sec = <60>; 532 }; 533}; 534