1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &lsio_gpio0; 21 gpio1 = &lsio_gpio1; 22 gpio2 = &lsio_gpio2; 23 gpio3 = &lsio_gpio3; 24 gpio4 = &lsio_gpio4; 25 gpio5 = &lsio_gpio5; 26 gpio6 = &lsio_gpio6; 27 gpio7 = &lsio_gpio7; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 mmc2 = &usdhc3; 31 serial0 = &adma_lpuart0; 32 mu1 = &lsio_mu1; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 /* We have 1 clusters with 4 Cortex-A35 cores */ 40 A35_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&A35_L2>; 46 clocks = <&clk IMX_A35_CLK>; 47 operating-points-v2 = <&a35_opp_table>; 48 #cooling-cells = <2>; 49 }; 50 51 A35_1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35"; 54 reg = <0x0 0x1>; 55 enable-method = "psci"; 56 next-level-cache = <&A35_L2>; 57 clocks = <&clk IMX_A35_CLK>; 58 operating-points-v2 = <&a35_opp_table>; 59 #cooling-cells = <2>; 60 }; 61 62 A35_2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a35"; 65 reg = <0x0 0x2>; 66 enable-method = "psci"; 67 next-level-cache = <&A35_L2>; 68 clocks = <&clk IMX_A35_CLK>; 69 operating-points-v2 = <&a35_opp_table>; 70 #cooling-cells = <2>; 71 }; 72 73 A35_3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a35"; 76 reg = <0x0 0x3>; 77 enable-method = "psci"; 78 next-level-cache = <&A35_L2>; 79 clocks = <&clk IMX_A35_CLK>; 80 operating-points-v2 = <&a35_opp_table>; 81 #cooling-cells = <2>; 82 }; 83 84 A35_L2: l2-cache0 { 85 compatible = "cache"; 86 }; 87 }; 88 89 a35_opp_table: opp-table { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-900000000 { 94 opp-hz = /bits/ 64 <900000000>; 95 opp-microvolt = <1000000>; 96 clock-latency-ns = <150000>; 97 }; 98 99 opp-1200000000 { 100 opp-hz = /bits/ 64 <1200000000>; 101 opp-microvolt = <1100000>; 102 clock-latency-ns = <150000>; 103 opp-suspend; 104 }; 105 }; 106 107 gic: interrupt-controller@51a00000 { 108 compatible = "arm,gic-v3"; 109 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 110 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 116 pmu { 117 compatible = "arm,armv8-pmuv3"; 118 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 psci { 122 compatible = "arm,psci-1.0"; 123 method = "smc"; 124 }; 125 126 scu { 127 compatible = "fsl,imx-scu"; 128 mbox-names = "tx0", "tx1", "tx2", "tx3", 129 "rx0", "rx1", "rx2", "rx3", 130 "gip3"; 131 mboxes = <&lsio_mu1 0 0 132 &lsio_mu1 0 1 133 &lsio_mu1 0 2 134 &lsio_mu1 0 3 135 &lsio_mu1 1 0 136 &lsio_mu1 1 1 137 &lsio_mu1 1 2 138 &lsio_mu1 1 3 139 &lsio_mu1 3 3>; 140 141 clk: clock-controller { 142 compatible = "fsl,imx8qxp-clk"; 143 #clock-cells = <1>; 144 clocks = <&xtal32k &xtal24m>; 145 clock-names = "xtal_32KHz", "xtal_24Mhz"; 146 }; 147 148 iomuxc: pinctrl { 149 compatible = "fsl,imx8qxp-iomuxc"; 150 }; 151 152 pd: imx8qx-pd { 153 compatible = "fsl,imx8qxp-scu-pd"; 154 #power-domain-cells = <1>; 155 }; 156 157 rtc: rtc { 158 compatible = "fsl,imx8qxp-sc-rtc"; 159 }; 160 161 watchdog { 162 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 163 timeout-sec = <60>; 164 }; 165 }; 166 167 timer { 168 compatible = "arm,armv8-timer"; 169 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 170 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 171 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 172 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 173 }; 174 175 xtal32k: clock-xtal32k { 176 compatible = "fixed-clock"; 177 #clock-cells = <0>; 178 clock-frequency = <32768>; 179 clock-output-names = "xtal_32KHz"; 180 }; 181 182 xtal24m: clock-xtal24m { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency = <24000000>; 186 clock-output-names = "xtal_24MHz"; 187 }; 188 189 adma_subsys: bus@59000000 { 190 compatible = "simple-bus"; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 194 195 adma_lpcg: clock-controller@59000000 { 196 compatible = "fsl,imx8qxp-lpcg-adma"; 197 reg = <0x59000000 0x2000000>; 198 #clock-cells = <1>; 199 }; 200 201 adma_lpuart0: serial@5a060000 { 202 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 203 reg = <0x5a060000 0x1000>; 204 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-parent = <&gic>; 206 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 207 clock-names = "ipg"; 208 power-domains = <&pd IMX_SC_R_UART_0>; 209 status = "disabled"; 210 }; 211 212 adma_lpuart1: serial@5a070000 { 213 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 214 reg = <0x5a070000 0x1000>; 215 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-parent = <&gic>; 217 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 218 clock-names = "ipg"; 219 power-domains = <&pd IMX_SC_R_UART_1>; 220 status = "disabled"; 221 }; 222 223 adma_lpuart2: serial@5a080000 { 224 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 225 reg = <0x5a080000 0x1000>; 226 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-parent = <&gic>; 228 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 229 clock-names = "ipg"; 230 power-domains = <&pd IMX_SC_R_UART_2>; 231 status = "disabled"; 232 }; 233 234 adma_lpuart3: serial@5a090000 { 235 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 236 reg = <0x5a090000 0x1000>; 237 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 238 interrupt-parent = <&gic>; 239 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 240 clock-names = "ipg"; 241 power-domains = <&pd IMX_SC_R_UART_3>; 242 status = "disabled"; 243 }; 244 245 adma_i2c0: i2c@5a800000 { 246 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 247 reg = <0x5a800000 0x4000>; 248 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 249 interrupt-parent = <&gic>; 250 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 251 clock-names = "per"; 252 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 253 assigned-clock-rates = <24000000>; 254 power-domains = <&pd IMX_SC_R_I2C_0>; 255 status = "disabled"; 256 }; 257 258 adma_i2c1: i2c@5a810000 { 259 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 260 reg = <0x5a810000 0x4000>; 261 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-parent = <&gic>; 263 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 264 clock-names = "per"; 265 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 266 assigned-clock-rates = <24000000>; 267 power-domains = <&pd IMX_SC_R_I2C_1>; 268 status = "disabled"; 269 }; 270 271 adma_i2c2: i2c@5a820000 { 272 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 273 reg = <0x5a820000 0x4000>; 274 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-parent = <&gic>; 276 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 277 clock-names = "per"; 278 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 279 assigned-clock-rates = <24000000>; 280 power-domains = <&pd IMX_SC_R_I2C_2>; 281 status = "disabled"; 282 }; 283 284 adma_i2c3: i2c@5a830000 { 285 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 286 reg = <0x5a830000 0x4000>; 287 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 288 interrupt-parent = <&gic>; 289 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 290 clock-names = "per"; 291 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 292 assigned-clock-rates = <24000000>; 293 power-domains = <&pd IMX_SC_R_I2C_3>; 294 status = "disabled"; 295 }; 296 }; 297 298 conn_subsys: bus@5b000000 { 299 compatible = "simple-bus"; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 303 304 conn_lpcg: clock-controller@5b200000 { 305 compatible = "fsl,imx8qxp-lpcg-conn"; 306 reg = <0x5b200000 0xb0000>; 307 #clock-cells = <1>; 308 }; 309 310 usdhc1: mmc@5b010000 { 311 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 312 interrupt-parent = <&gic>; 313 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 314 reg = <0x5b010000 0x10000>; 315 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 316 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 317 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 318 clock-names = "ipg", "per", "ahb"; 319 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 320 assigned-clock-rates = <200000000>; 321 power-domains = <&pd IMX_SC_R_SDHC_0>; 322 status = "disabled"; 323 }; 324 325 usdhc2: mmc@5b020000 { 326 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 327 interrupt-parent = <&gic>; 328 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 329 reg = <0x5b020000 0x10000>; 330 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 331 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 332 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 333 clock-names = "ipg", "per", "ahb"; 334 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 335 assigned-clock-rates = <200000000>; 336 power-domains = <&pd IMX_SC_R_SDHC_1>; 337 fsl,tuning-start-tap = <20>; 338 fsl,tuning-step= <2>; 339 status = "disabled"; 340 }; 341 342 usdhc3: mmc@5b030000 { 343 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 344 interrupt-parent = <&gic>; 345 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 346 reg = <0x5b030000 0x10000>; 347 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 348 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 349 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 350 clock-names = "ipg", "per", "ahb"; 351 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 352 assigned-clock-rates = <200000000>; 353 power-domains = <&pd IMX_SC_R_SDHC_2>; 354 status = "disabled"; 355 }; 356 357 fec1: ethernet@5b040000 { 358 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 359 reg = <0x5b040000 0x10000>; 360 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 365 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 366 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 367 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 368 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 369 fsl,num-tx-queues=<3>; 370 fsl,num-rx-queues=<3>; 371 power-domains = <&pd IMX_SC_R_ENET_0>; 372 status = "disabled"; 373 }; 374 375 fec2: ethernet@5b050000 { 376 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 377 reg = <0x5b050000 0x10000>; 378 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 383 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 384 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 385 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 386 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 387 fsl,num-tx-queues=<3>; 388 fsl,num-rx-queues=<3>; 389 power-domains = <&pd IMX_SC_R_ENET_1>; 390 status = "disabled"; 391 }; 392 }; 393 394 lsio_subsys: bus@5d000000 { 395 compatible = "simple-bus"; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 399 400 lsio_lpcg: clock-controller@5d400000 { 401 compatible = "fsl,imx8qxp-lpcg-lsio"; 402 reg = <0x5d400000 0x400000>; 403 #clock-cells = <1>; 404 }; 405 406 lsio_mu0: mailbox@5d1b0000 { 407 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 408 reg = <0x5d1b0000 0x10000>; 409 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 410 #mbox-cells = <2>; 411 status = "disabled"; 412 }; 413 414 lsio_mu1: mailbox@5d1c0000 { 415 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 416 reg = <0x5d1c0000 0x10000>; 417 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 418 #mbox-cells = <2>; 419 }; 420 421 lsio_mu2: mailbox@5d1d0000 { 422 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 423 reg = <0x5d1d0000 0x10000>; 424 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 425 #mbox-cells = <2>; 426 status = "disabled"; 427 }; 428 429 lsio_mu3: mailbox@5d1e0000 { 430 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 431 reg = <0x5d1e0000 0x10000>; 432 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 433 #mbox-cells = <2>; 434 status = "disabled"; 435 }; 436 437 lsio_mu4: mailbox@5d1f0000 { 438 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 439 reg = <0x5d1f0000 0x10000>; 440 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 441 #mbox-cells = <2>; 442 status = "disabled"; 443 }; 444 445 lsio_gpio0: gpio@5d080000 { 446 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 447 reg = <0x5d080000 0x10000>; 448 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 449 gpio-controller; 450 #gpio-cells = <2>; 451 interrupt-controller; 452 #interrupt-cells = <2>; 453 power-domains = <&pd IMX_SC_R_GPIO_0>; 454 }; 455 456 lsio_gpio1: gpio@5d090000 { 457 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 458 reg = <0x5d090000 0x10000>; 459 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 power-domains = <&pd IMX_SC_R_GPIO_1>; 465 }; 466 467 lsio_gpio2: gpio@5d0a0000 { 468 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 469 reg = <0x5d0a0000 0x10000>; 470 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 interrupt-controller; 474 #interrupt-cells = <2>; 475 power-domains = <&pd IMX_SC_R_GPIO_2>; 476 }; 477 478 lsio_gpio3: gpio@5d0b0000 { 479 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 480 reg = <0x5d0b0000 0x10000>; 481 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 power-domains = <&pd IMX_SC_R_GPIO_3>; 487 }; 488 489 lsio_gpio4: gpio@5d0c0000 { 490 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 491 reg = <0x5d0c0000 0x10000>; 492 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 power-domains = <&pd IMX_SC_R_GPIO_4>; 498 }; 499 500 lsio_gpio5: gpio@5d0d0000 { 501 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 502 reg = <0x5d0d0000 0x10000>; 503 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 504 gpio-controller; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 power-domains = <&pd IMX_SC_R_GPIO_5>; 509 }; 510 511 lsio_gpio6: gpio@5d0e0000 { 512 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 513 reg = <0x5d0e0000 0x10000>; 514 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 power-domains = <&pd IMX_SC_R_GPIO_6>; 520 }; 521 522 lsio_gpio7: gpio@5d0f0000 { 523 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 524 reg = <0x5d0f0000 0x10000>; 525 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 interrupt-controller; 529 #interrupt-cells = <2>; 530 power-domains = <&pd IMX_SC_R_GPIO_7>; 531 }; 532 }; 533}; 534