1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 gpio0 = &lsio_gpio0; 21 gpio1 = &lsio_gpio1; 22 gpio2 = &lsio_gpio2; 23 gpio3 = &lsio_gpio3; 24 gpio4 = &lsio_gpio4; 25 gpio5 = &lsio_gpio5; 26 gpio6 = &lsio_gpio6; 27 gpio7 = &lsio_gpio7; 28 mmc0 = &usdhc1; 29 mmc1 = &usdhc2; 30 mmc2 = &usdhc3; 31 mu1 = &lsio_mu1; 32 serial0 = &adma_lpuart0; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 /* We have 1 clusters with 4 Cortex-A35 cores */ 40 A35_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&A35_L2>; 46 clocks = <&clk IMX_A35_CLK>; 47 operating-points-v2 = <&a35_opp_table>; 48 #cooling-cells = <2>; 49 }; 50 51 A35_1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35"; 54 reg = <0x0 0x1>; 55 enable-method = "psci"; 56 next-level-cache = <&A35_L2>; 57 clocks = <&clk IMX_A35_CLK>; 58 operating-points-v2 = <&a35_opp_table>; 59 #cooling-cells = <2>; 60 }; 61 62 A35_2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a35"; 65 reg = <0x0 0x2>; 66 enable-method = "psci"; 67 next-level-cache = <&A35_L2>; 68 clocks = <&clk IMX_A35_CLK>; 69 operating-points-v2 = <&a35_opp_table>; 70 #cooling-cells = <2>; 71 }; 72 73 A35_3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a35"; 76 reg = <0x0 0x3>; 77 enable-method = "psci"; 78 next-level-cache = <&A35_L2>; 79 clocks = <&clk IMX_A35_CLK>; 80 operating-points-v2 = <&a35_opp_table>; 81 #cooling-cells = <2>; 82 }; 83 84 A35_L2: l2-cache0 { 85 compatible = "cache"; 86 }; 87 }; 88 89 a35_opp_table: opp-table { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-900000000 { 94 opp-hz = /bits/ 64 <900000000>; 95 opp-microvolt = <1000000>; 96 clock-latency-ns = <150000>; 97 }; 98 99 opp-1200000000 { 100 opp-hz = /bits/ 64 <1200000000>; 101 opp-microvolt = <1100000>; 102 clock-latency-ns = <150000>; 103 opp-suspend; 104 }; 105 }; 106 107 gic: interrupt-controller@51a00000 { 108 compatible = "arm,gic-v3"; 109 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 110 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 116 reserved-memory { 117 #address-cells = <2>; 118 #size-cells = <2>; 119 ranges; 120 121 dsp_reserved: dsp@92400000 { 122 reg = <0 0x92400000 0 0x2000000>; 123 no-map; 124 }; 125 }; 126 127 pmu { 128 compatible = "arm,armv8-pmuv3"; 129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 psci { 133 compatible = "arm,psci-1.0"; 134 method = "smc"; 135 }; 136 137 scu { 138 compatible = "fsl,imx-scu"; 139 mbox-names = "tx0", "tx1", "tx2", "tx3", 140 "rx0", "rx1", "rx2", "rx3", 141 "gip3"; 142 mboxes = <&lsio_mu1 0 0 143 &lsio_mu1 0 1 144 &lsio_mu1 0 2 145 &lsio_mu1 0 3 146 &lsio_mu1 1 0 147 &lsio_mu1 1 1 148 &lsio_mu1 1 2 149 &lsio_mu1 1 3 150 &lsio_mu1 3 3>; 151 152 clk: clock-controller { 153 compatible = "fsl,imx8qxp-clk"; 154 #clock-cells = <1>; 155 clocks = <&xtal32k &xtal24m>; 156 clock-names = "xtal_32KHz", "xtal_24Mhz"; 157 }; 158 159 iomuxc: pinctrl { 160 compatible = "fsl,imx8qxp-iomuxc"; 161 }; 162 163 ocotp: imx8qx-ocotp { 164 compatible = "fsl,imx8qxp-scu-ocotp"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 }; 168 169 pd: imx8qx-pd { 170 compatible = "fsl,imx8qxp-scu-pd"; 171 #power-domain-cells = <1>; 172 }; 173 174 rtc: rtc { 175 compatible = "fsl,imx8qxp-sc-rtc"; 176 }; 177 178 watchdog { 179 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 180 timeout-sec = <60>; 181 }; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 190 }; 191 192 xtal32k: clock-xtal32k { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <32768>; 196 clock-output-names = "xtal_32KHz"; 197 }; 198 199 xtal24m: clock-xtal24m { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <24000000>; 203 clock-output-names = "xtal_24MHz"; 204 }; 205 206 adma_subsys: bus@59000000 { 207 compatible = "simple-bus"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 211 212 adma_lpcg: clock-controller@59000000 { 213 compatible = "fsl,imx8qxp-lpcg-adma"; 214 reg = <0x59000000 0x2000000>; 215 #clock-cells = <1>; 216 }; 217 218 adma_dsp: dsp@596e8000 { 219 compatible = "fsl,imx8qxp-dsp"; 220 reg = <0x596e8000 0x88000>; 221 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 222 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 223 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 224 clock-names = "ipg", "ocram", "core"; 225 power-domains = <&pd IMX_SC_R_MU_13A>, 226 <&pd IMX_SC_R_MU_13B>, 227 <&pd IMX_SC_R_DSP>, 228 <&pd IMX_SC_R_DSP_RAM>; 229 mbox-names = "txdb0", "txdb1", 230 "rxdb0", "rxdb1"; 231 mboxes = <&lsio_mu13 2 0>, 232 <&lsio_mu13 2 1>, 233 <&lsio_mu13 3 0>, 234 <&lsio_mu13 3 1>; 235 memory-region = <&dsp_reserved>; 236 status = "disabled"; 237 }; 238 239 adma_lpuart0: serial@5a060000 { 240 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 241 reg = <0x5a060000 0x1000>; 242 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 243 interrupt-parent = <&gic>; 244 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 245 clock-names = "ipg"; 246 power-domains = <&pd IMX_SC_R_UART_0>; 247 status = "disabled"; 248 }; 249 250 adma_lpuart1: serial@5a070000 { 251 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 252 reg = <0x5a070000 0x1000>; 253 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 254 interrupt-parent = <&gic>; 255 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 256 clock-names = "ipg"; 257 power-domains = <&pd IMX_SC_R_UART_1>; 258 status = "disabled"; 259 }; 260 261 adma_lpuart2: serial@5a080000 { 262 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 263 reg = <0x5a080000 0x1000>; 264 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-parent = <&gic>; 266 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 267 clock-names = "ipg"; 268 power-domains = <&pd IMX_SC_R_UART_2>; 269 status = "disabled"; 270 }; 271 272 adma_lpuart3: serial@5a090000 { 273 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 274 reg = <0x5a090000 0x1000>; 275 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-parent = <&gic>; 277 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 278 clock-names = "ipg"; 279 power-domains = <&pd IMX_SC_R_UART_3>; 280 status = "disabled"; 281 }; 282 283 adma_i2c0: i2c@5a800000 { 284 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 285 reg = <0x5a800000 0x4000>; 286 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-parent = <&gic>; 288 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 289 clock-names = "per"; 290 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 291 assigned-clock-rates = <24000000>; 292 power-domains = <&pd IMX_SC_R_I2C_0>; 293 status = "disabled"; 294 }; 295 296 adma_i2c1: i2c@5a810000 { 297 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 298 reg = <0x5a810000 0x4000>; 299 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-parent = <&gic>; 301 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 302 clock-names = "per"; 303 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 304 assigned-clock-rates = <24000000>; 305 power-domains = <&pd IMX_SC_R_I2C_1>; 306 status = "disabled"; 307 }; 308 309 adma_i2c2: i2c@5a820000 { 310 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 311 reg = <0x5a820000 0x4000>; 312 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-parent = <&gic>; 314 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 315 clock-names = "per"; 316 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 317 assigned-clock-rates = <24000000>; 318 power-domains = <&pd IMX_SC_R_I2C_2>; 319 status = "disabled"; 320 }; 321 322 adma_i2c3: i2c@5a830000 { 323 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 324 reg = <0x5a830000 0x4000>; 325 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 326 interrupt-parent = <&gic>; 327 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 328 clock-names = "per"; 329 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 330 assigned-clock-rates = <24000000>; 331 power-domains = <&pd IMX_SC_R_I2C_3>; 332 status = "disabled"; 333 }; 334 }; 335 336 conn_subsys: bus@5b000000 { 337 compatible = "simple-bus"; 338 #address-cells = <1>; 339 #size-cells = <1>; 340 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 341 342 conn_lpcg: clock-controller@5b200000 { 343 compatible = "fsl,imx8qxp-lpcg-conn"; 344 reg = <0x5b200000 0xb0000>; 345 #clock-cells = <1>; 346 }; 347 348 usdhc1: mmc@5b010000 { 349 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 350 interrupt-parent = <&gic>; 351 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 352 reg = <0x5b010000 0x10000>; 353 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 354 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 355 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 356 clock-names = "ipg", "per", "ahb"; 357 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 358 assigned-clock-rates = <200000000>; 359 power-domains = <&pd IMX_SC_R_SDHC_0>; 360 status = "disabled"; 361 }; 362 363 usdhc2: mmc@5b020000 { 364 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 365 interrupt-parent = <&gic>; 366 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 367 reg = <0x5b020000 0x10000>; 368 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 369 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 370 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 371 clock-names = "ipg", "per", "ahb"; 372 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 373 assigned-clock-rates = <200000000>; 374 power-domains = <&pd IMX_SC_R_SDHC_1>; 375 fsl,tuning-start-tap = <20>; 376 fsl,tuning-step= <2>; 377 status = "disabled"; 378 }; 379 380 usdhc3: mmc@5b030000 { 381 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 382 interrupt-parent = <&gic>; 383 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 384 reg = <0x5b030000 0x10000>; 385 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 386 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 387 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 388 clock-names = "ipg", "per", "ahb"; 389 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 390 assigned-clock-rates = <200000000>; 391 power-domains = <&pd IMX_SC_R_SDHC_2>; 392 status = "disabled"; 393 }; 394 395 fec1: ethernet@5b040000 { 396 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 397 reg = <0x5b040000 0x10000>; 398 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 403 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 404 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 405 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 406 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 407 fsl,num-tx-queues=<3>; 408 fsl,num-rx-queues=<3>; 409 power-domains = <&pd IMX_SC_R_ENET_0>; 410 status = "disabled"; 411 }; 412 413 fec2: ethernet@5b050000 { 414 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 415 reg = <0x5b050000 0x10000>; 416 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 421 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 422 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 423 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 424 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 425 fsl,num-tx-queues=<3>; 426 fsl,num-rx-queues=<3>; 427 power-domains = <&pd IMX_SC_R_ENET_1>; 428 status = "disabled"; 429 }; 430 }; 431 432 ddr_subsyss: bus@5c000000 { 433 compatible = "simple-bus"; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 437 438 ddr-pmu@5c020000 { 439 compatible = "fsl,imx8-ddr-pmu"; 440 reg = <0x5c020000 0x10000>; 441 interrupt-parent = <&gic>; 442 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 443 }; 444 }; 445 446 lsio_subsys: bus@5d000000 { 447 compatible = "simple-bus"; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 451 452 lsio_gpio0: gpio@5d080000 { 453 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 454 reg = <0x5d080000 0x10000>; 455 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 456 gpio-controller; 457 #gpio-cells = <2>; 458 interrupt-controller; 459 #interrupt-cells = <2>; 460 power-domains = <&pd IMX_SC_R_GPIO_0>; 461 }; 462 463 lsio_gpio1: gpio@5d090000 { 464 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 465 reg = <0x5d090000 0x10000>; 466 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 power-domains = <&pd IMX_SC_R_GPIO_1>; 472 }; 473 474 lsio_gpio2: gpio@5d0a0000 { 475 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 476 reg = <0x5d0a0000 0x10000>; 477 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 478 gpio-controller; 479 #gpio-cells = <2>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 power-domains = <&pd IMX_SC_R_GPIO_2>; 483 }; 484 485 lsio_gpio3: gpio@5d0b0000 { 486 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 487 reg = <0x5d0b0000 0x10000>; 488 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 489 gpio-controller; 490 #gpio-cells = <2>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 power-domains = <&pd IMX_SC_R_GPIO_3>; 494 }; 495 496 lsio_gpio4: gpio@5d0c0000 { 497 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 498 reg = <0x5d0c0000 0x10000>; 499 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 500 gpio-controller; 501 #gpio-cells = <2>; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 power-domains = <&pd IMX_SC_R_GPIO_4>; 505 }; 506 507 lsio_gpio5: gpio@5d0d0000 { 508 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 509 reg = <0x5d0d0000 0x10000>; 510 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 511 gpio-controller; 512 #gpio-cells = <2>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 power-domains = <&pd IMX_SC_R_GPIO_5>; 516 }; 517 518 lsio_gpio6: gpio@5d0e0000 { 519 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 520 reg = <0x5d0e0000 0x10000>; 521 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupt-controller; 525 #interrupt-cells = <2>; 526 power-domains = <&pd IMX_SC_R_GPIO_6>; 527 }; 528 529 lsio_gpio7: gpio@5d0f0000 { 530 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 531 reg = <0x5d0f0000 0x10000>; 532 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 power-domains = <&pd IMX_SC_R_GPIO_7>; 538 }; 539 540 lsio_mu0: mailbox@5d1b0000 { 541 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 542 reg = <0x5d1b0000 0x10000>; 543 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 544 #mbox-cells = <2>; 545 status = "disabled"; 546 }; 547 548 lsio_mu1: mailbox@5d1c0000 { 549 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 550 reg = <0x5d1c0000 0x10000>; 551 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 552 #mbox-cells = <2>; 553 }; 554 555 lsio_mu2: mailbox@5d1d0000 { 556 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 557 reg = <0x5d1d0000 0x10000>; 558 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 559 #mbox-cells = <2>; 560 status = "disabled"; 561 }; 562 563 lsio_mu3: mailbox@5d1e0000 { 564 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 565 reg = <0x5d1e0000 0x10000>; 566 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 567 #mbox-cells = <2>; 568 status = "disabled"; 569 }; 570 571 lsio_mu4: mailbox@5d1f0000 { 572 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 573 reg = <0x5d1f0000 0x10000>; 574 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 575 #mbox-cells = <2>; 576 status = "disabled"; 577 }; 578 579 lsio_mu13: mailbox@5d280000 { 580 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 581 reg = <0x5d280000 0x10000>; 582 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 583 #mbox-cells = <2>; 584 power-domains = <&pd IMX_SC_R_MU_13A>; 585 }; 586 587 lsio_lpcg: clock-controller@5d400000 { 588 compatible = "fsl,imx8qxp-lpcg-lsio"; 589 reg = <0x5d400000 0x400000>; 590 #clock-cells = <1>; 591 }; 592 }; 593}; 594