1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/pads-imx8qxp.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &lsio_gpio0; 22 gpio1 = &lsio_gpio1; 23 gpio2 = &lsio_gpio2; 24 gpio3 = &lsio_gpio3; 25 gpio4 = &lsio_gpio4; 26 gpio5 = &lsio_gpio5; 27 gpio6 = &lsio_gpio6; 28 gpio7 = &lsio_gpio7; 29 mmc0 = &usdhc1; 30 mmc1 = &usdhc2; 31 mmc2 = &usdhc3; 32 mu1 = &lsio_mu1; 33 serial0 = &adma_lpuart0; 34 serial1 = &adma_lpuart1; 35 serial2 = &adma_lpuart2; 36 serial3 = &adma_lpuart3; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 /* We have 1 clusters with 4 Cortex-A35 cores */ 44 A35_0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&A35_L2>; 50 clocks = <&clk IMX_A35_CLK>; 51 operating-points-v2 = <&a35_opp_table>; 52 #cooling-cells = <2>; 53 }; 54 55 A35_1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35"; 58 reg = <0x0 0x1>; 59 enable-method = "psci"; 60 next-level-cache = <&A35_L2>; 61 clocks = <&clk IMX_A35_CLK>; 62 operating-points-v2 = <&a35_opp_table>; 63 #cooling-cells = <2>; 64 }; 65 66 A35_2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 next-level-cache = <&A35_L2>; 72 clocks = <&clk IMX_A35_CLK>; 73 operating-points-v2 = <&a35_opp_table>; 74 #cooling-cells = <2>; 75 }; 76 77 A35_3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a35"; 80 reg = <0x0 0x3>; 81 enable-method = "psci"; 82 next-level-cache = <&A35_L2>; 83 clocks = <&clk IMX_A35_CLK>; 84 operating-points-v2 = <&a35_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A35_L2: l2-cache0 { 89 compatible = "cache"; 90 }; 91 }; 92 93 a35_opp_table: opp-table { 94 compatible = "operating-points-v2"; 95 opp-shared; 96 97 opp-900000000 { 98 opp-hz = /bits/ 64 <900000000>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <150000>; 101 }; 102 103 opp-1200000000 { 104 opp-hz = /bits/ 64 <1200000000>; 105 opp-microvolt = <1100000>; 106 clock-latency-ns = <150000>; 107 opp-suspend; 108 }; 109 }; 110 111 gic: interrupt-controller@51a00000 { 112 compatible = "arm,gic-v3"; 113 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 114 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 115 #interrupt-cells = <3>; 116 interrupt-controller; 117 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 118 }; 119 120 reserved-memory { 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges; 124 125 dsp_reserved: dsp@92400000 { 126 reg = <0 0x92400000 0 0x2000000>; 127 no-map; 128 }; 129 }; 130 131 pmu { 132 compatible = "arm,armv8-pmuv3"; 133 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 136 psci { 137 compatible = "arm,psci-1.0"; 138 method = "smc"; 139 }; 140 141 scu { 142 compatible = "fsl,imx-scu"; 143 mbox-names = "tx0", "tx1", "tx2", "tx3", 144 "rx0", "rx1", "rx2", "rx3", 145 "gip3"; 146 mboxes = <&lsio_mu1 0 0 147 &lsio_mu1 0 1 148 &lsio_mu1 0 2 149 &lsio_mu1 0 3 150 &lsio_mu1 1 0 151 &lsio_mu1 1 1 152 &lsio_mu1 1 2 153 &lsio_mu1 1 3 154 &lsio_mu1 3 3>; 155 156 clk: clock-controller { 157 compatible = "fsl,imx8qxp-clk"; 158 #clock-cells = <1>; 159 clocks = <&xtal32k &xtal24m>; 160 clock-names = "xtal_32KHz", "xtal_24Mhz"; 161 }; 162 163 iomuxc: pinctrl { 164 compatible = "fsl,imx8qxp-iomuxc"; 165 }; 166 167 ocotp: imx8qx-ocotp { 168 compatible = "fsl,imx8qxp-scu-ocotp"; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 }; 172 173 pd: imx8qx-pd { 174 compatible = "fsl,imx8qxp-scu-pd"; 175 #power-domain-cells = <1>; 176 }; 177 178 scu_key: scu-key { 179 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 180 linux,keycodes = <KEY_POWER>; 181 status = "disabled"; 182 }; 183 184 rtc: rtc { 185 compatible = "fsl,imx8qxp-sc-rtc"; 186 }; 187 188 watchdog { 189 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 190 timeout-sec = <60>; 191 }; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 197 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 198 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 199 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 200 }; 201 202 xtal32k: clock-xtal32k { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <32768>; 206 clock-output-names = "xtal_32KHz"; 207 }; 208 209 xtal24m: clock-xtal24m { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <24000000>; 213 clock-output-names = "xtal_24MHz"; 214 }; 215 216 adma_subsys: bus@59000000 { 217 compatible = "simple-bus"; 218 #address-cells = <1>; 219 #size-cells = <1>; 220 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 221 222 adma_lpcg: clock-controller@59000000 { 223 compatible = "fsl,imx8qxp-lpcg-adma"; 224 reg = <0x59000000 0x2000000>; 225 #clock-cells = <1>; 226 }; 227 228 adma_dsp: dsp@596e8000 { 229 compatible = "fsl,imx8qxp-dsp"; 230 reg = <0x596e8000 0x88000>; 231 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 232 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 233 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 234 clock-names = "ipg", "ocram", "core"; 235 power-domains = <&pd IMX_SC_R_MU_13A>, 236 <&pd IMX_SC_R_MU_13B>, 237 <&pd IMX_SC_R_DSP>, 238 <&pd IMX_SC_R_DSP_RAM>; 239 mbox-names = "txdb0", "txdb1", 240 "rxdb0", "rxdb1"; 241 mboxes = <&lsio_mu13 2 0>, 242 <&lsio_mu13 2 1>, 243 <&lsio_mu13 3 0>, 244 <&lsio_mu13 3 1>; 245 memory-region = <&dsp_reserved>; 246 status = "disabled"; 247 }; 248 249 adma_lpuart0: serial@5a060000 { 250 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 251 reg = <0x5a060000 0x1000>; 252 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-parent = <&gic>; 254 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 255 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 256 clock-names = "ipg", "baud"; 257 power-domains = <&pd IMX_SC_R_UART_0>; 258 status = "disabled"; 259 }; 260 261 adma_lpuart1: serial@5a070000 { 262 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 263 reg = <0x5a070000 0x1000>; 264 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-parent = <&gic>; 266 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 267 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 268 clock-names = "ipg", "baud"; 269 power-domains = <&pd IMX_SC_R_UART_1>; 270 status = "disabled"; 271 }; 272 273 adma_lpuart2: serial@5a080000 { 274 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 275 reg = <0x5a080000 0x1000>; 276 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-parent = <&gic>; 278 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 279 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 280 clock-names = "ipg", "baud"; 281 power-domains = <&pd IMX_SC_R_UART_2>; 282 status = "disabled"; 283 }; 284 285 adma_lpuart3: serial@5a090000 { 286 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 287 reg = <0x5a090000 0x1000>; 288 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-parent = <&gic>; 290 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 291 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 292 clock-names = "ipg", "baud"; 293 power-domains = <&pd IMX_SC_R_UART_3>; 294 status = "disabled"; 295 }; 296 297 adma_i2c0: i2c@5a800000 { 298 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 299 reg = <0x5a800000 0x4000>; 300 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-parent = <&gic>; 302 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 303 clock-names = "per"; 304 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 305 assigned-clock-rates = <24000000>; 306 power-domains = <&pd IMX_SC_R_I2C_0>; 307 status = "disabled"; 308 }; 309 310 adma_i2c1: i2c@5a810000 { 311 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 312 reg = <0x5a810000 0x4000>; 313 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-parent = <&gic>; 315 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 316 clock-names = "per"; 317 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 318 assigned-clock-rates = <24000000>; 319 power-domains = <&pd IMX_SC_R_I2C_1>; 320 status = "disabled"; 321 }; 322 323 adma_i2c2: i2c@5a820000 { 324 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 325 reg = <0x5a820000 0x4000>; 326 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 327 interrupt-parent = <&gic>; 328 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 329 clock-names = "per"; 330 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 331 assigned-clock-rates = <24000000>; 332 power-domains = <&pd IMX_SC_R_I2C_2>; 333 status = "disabled"; 334 }; 335 336 adma_i2c3: i2c@5a830000 { 337 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 338 reg = <0x5a830000 0x4000>; 339 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-parent = <&gic>; 341 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 342 clock-names = "per"; 343 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 344 assigned-clock-rates = <24000000>; 345 power-domains = <&pd IMX_SC_R_I2C_3>; 346 status = "disabled"; 347 }; 348 }; 349 350 conn_subsys: bus@5b000000 { 351 compatible = "simple-bus"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 355 356 conn_lpcg: clock-controller@5b200000 { 357 compatible = "fsl,imx8qxp-lpcg-conn"; 358 reg = <0x5b200000 0xb0000>; 359 #clock-cells = <1>; 360 }; 361 362 usdhc1: mmc@5b010000 { 363 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 364 interrupt-parent = <&gic>; 365 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 366 reg = <0x5b010000 0x10000>; 367 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 368 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 369 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 370 clock-names = "ipg", "per", "ahb"; 371 power-domains = <&pd IMX_SC_R_SDHC_0>; 372 status = "disabled"; 373 }; 374 375 usdhc2: mmc@5b020000 { 376 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 377 interrupt-parent = <&gic>; 378 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 379 reg = <0x5b020000 0x10000>; 380 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 381 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 382 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 383 clock-names = "ipg", "per", "ahb"; 384 power-domains = <&pd IMX_SC_R_SDHC_1>; 385 fsl,tuning-start-tap = <20>; 386 fsl,tuning-step= <2>; 387 status = "disabled"; 388 }; 389 390 usdhc3: mmc@5b030000 { 391 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 392 interrupt-parent = <&gic>; 393 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 394 reg = <0x5b030000 0x10000>; 395 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 396 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 397 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 398 clock-names = "ipg", "per", "ahb"; 399 power-domains = <&pd IMX_SC_R_SDHC_2>; 400 status = "disabled"; 401 }; 402 403 fec1: ethernet@5b040000 { 404 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 405 reg = <0x5b040000 0x10000>; 406 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 411 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 412 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 413 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 414 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 415 fsl,num-tx-queues=<3>; 416 fsl,num-rx-queues=<3>; 417 power-domains = <&pd IMX_SC_R_ENET_0>; 418 status = "disabled"; 419 }; 420 421 fec2: ethernet@5b050000 { 422 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 423 reg = <0x5b050000 0x10000>; 424 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 429 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 430 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 431 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 432 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 433 fsl,num-tx-queues=<3>; 434 fsl,num-rx-queues=<3>; 435 power-domains = <&pd IMX_SC_R_ENET_1>; 436 status = "disabled"; 437 }; 438 }; 439 440 ddr_subsyss: bus@5c000000 { 441 compatible = "simple-bus"; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 445 446 ddr-pmu@5c020000 { 447 compatible = "fsl,imx8-ddr-pmu"; 448 reg = <0x5c020000 0x10000>; 449 interrupt-parent = <&gic>; 450 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 451 }; 452 }; 453 454 lsio_subsys: bus@5d000000 { 455 compatible = "simple-bus"; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 459 460 lsio_gpio0: gpio@5d080000 { 461 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 462 reg = <0x5d080000 0x10000>; 463 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 464 gpio-controller; 465 #gpio-cells = <2>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 power-domains = <&pd IMX_SC_R_GPIO_0>; 469 }; 470 471 lsio_gpio1: gpio@5d090000 { 472 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 473 reg = <0x5d090000 0x10000>; 474 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 475 gpio-controller; 476 #gpio-cells = <2>; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 power-domains = <&pd IMX_SC_R_GPIO_1>; 480 }; 481 482 lsio_gpio2: gpio@5d0a0000 { 483 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 484 reg = <0x5d0a0000 0x10000>; 485 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 486 gpio-controller; 487 #gpio-cells = <2>; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 power-domains = <&pd IMX_SC_R_GPIO_2>; 491 }; 492 493 lsio_gpio3: gpio@5d0b0000 { 494 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 495 reg = <0x5d0b0000 0x10000>; 496 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 power-domains = <&pd IMX_SC_R_GPIO_3>; 502 }; 503 504 lsio_gpio4: gpio@5d0c0000 { 505 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 506 reg = <0x5d0c0000 0x10000>; 507 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 power-domains = <&pd IMX_SC_R_GPIO_4>; 513 }; 514 515 lsio_gpio5: gpio@5d0d0000 { 516 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 517 reg = <0x5d0d0000 0x10000>; 518 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 power-domains = <&pd IMX_SC_R_GPIO_5>; 524 }; 525 526 lsio_gpio6: gpio@5d0e0000 { 527 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 528 reg = <0x5d0e0000 0x10000>; 529 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 power-domains = <&pd IMX_SC_R_GPIO_6>; 535 }; 536 537 lsio_gpio7: gpio@5d0f0000 { 538 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 539 reg = <0x5d0f0000 0x10000>; 540 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 541 gpio-controller; 542 #gpio-cells = <2>; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 power-domains = <&pd IMX_SC_R_GPIO_7>; 546 }; 547 548 lsio_mu0: mailbox@5d1b0000 { 549 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 550 reg = <0x5d1b0000 0x10000>; 551 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 552 #mbox-cells = <2>; 553 status = "disabled"; 554 }; 555 556 lsio_mu1: mailbox@5d1c0000 { 557 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 558 reg = <0x5d1c0000 0x10000>; 559 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 560 #mbox-cells = <2>; 561 }; 562 563 lsio_mu2: mailbox@5d1d0000 { 564 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 565 reg = <0x5d1d0000 0x10000>; 566 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 567 #mbox-cells = <2>; 568 status = "disabled"; 569 }; 570 571 lsio_mu3: mailbox@5d1e0000 { 572 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 573 reg = <0x5d1e0000 0x10000>; 574 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 575 #mbox-cells = <2>; 576 status = "disabled"; 577 }; 578 579 lsio_mu4: mailbox@5d1f0000 { 580 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 581 reg = <0x5d1f0000 0x10000>; 582 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 583 #mbox-cells = <2>; 584 status = "disabled"; 585 }; 586 587 lsio_mu13: mailbox@5d280000 { 588 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 589 reg = <0x5d280000 0x10000>; 590 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 591 #mbox-cells = <2>; 592 power-domains = <&pd IMX_SC_R_MU_13A>; 593 }; 594 595 lsio_lpcg: clock-controller@5d400000 { 596 compatible = "fsl,imx8qxp-lpcg-lsio"; 597 reg = <0x5d400000 0x400000>; 598 #clock-cells = <1>; 599 }; 600 }; 601}; 602