1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc0 = &usdhc1; 21 mmc1 = &usdhc2; 22 mmc2 = &usdhc3; 23 serial0 = &adma_lpuart0; 24 }; 25 26 cpus { 27 #address-cells = <2>; 28 #size-cells = <0>; 29 30 /* We have 1 clusters with 4 Cortex-A35 cores */ 31 A35_0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a35"; 34 reg = <0x0 0x0>; 35 enable-method = "psci"; 36 next-level-cache = <&A35_L2>; 37 clocks = <&clk IMX_A35_CLK>; 38 operating-points-v2 = <&a35_opp_table>; 39 #cooling-cells = <2>; 40 }; 41 42 A35_1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x1>; 46 enable-method = "psci"; 47 next-level-cache = <&A35_L2>; 48 clocks = <&clk IMX_A35_CLK>; 49 operating-points-v2 = <&a35_opp_table>; 50 #cooling-cells = <2>; 51 }; 52 53 A35_2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35"; 56 reg = <0x0 0x2>; 57 enable-method = "psci"; 58 next-level-cache = <&A35_L2>; 59 clocks = <&clk IMX_A35_CLK>; 60 operating-points-v2 = <&a35_opp_table>; 61 #cooling-cells = <2>; 62 }; 63 64 A35_3: cpu@3 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a35"; 67 reg = <0x0 0x3>; 68 enable-method = "psci"; 69 next-level-cache = <&A35_L2>; 70 clocks = <&clk IMX_A35_CLK>; 71 operating-points-v2 = <&a35_opp_table>; 72 #cooling-cells = <2>; 73 }; 74 75 A35_L2: l2-cache0 { 76 compatible = "cache"; 77 }; 78 }; 79 80 a35_opp_table: opp-table { 81 compatible = "operating-points-v2"; 82 opp-shared; 83 84 opp-900000000 { 85 opp-hz = /bits/ 64 <900000000>; 86 opp-microvolt = <1000000>; 87 clock-latency-ns = <150000>; 88 }; 89 90 opp-1200000000 { 91 opp-hz = /bits/ 64 <1200000000>; 92 opp-microvolt = <1100000>; 93 clock-latency-ns = <150000>; 94 opp-suspend; 95 }; 96 }; 97 98 gic: interrupt-controller@51a00000 { 99 compatible = "arm,gic-v3"; 100 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 101 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 pmu { 108 compatible = "arm,armv8-pmuv3"; 109 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 psci { 113 compatible = "arm,psci-1.0"; 114 method = "smc"; 115 }; 116 117 scu { 118 compatible = "fsl,imx-scu"; 119 mbox-names = "tx0", "tx1", "tx2", "tx3", 120 "rx0", "rx1", "rx2", "rx3"; 121 mboxes = <&lsio_mu1 0 0 122 &lsio_mu1 0 1 123 &lsio_mu1 0 2 124 &lsio_mu1 0 3 125 &lsio_mu1 1 0 126 &lsio_mu1 1 1 127 &lsio_mu1 1 2 128 &lsio_mu1 1 3>; 129 130 clk: clock-controller { 131 compatible = "fsl,imx8qxp-clk"; 132 #clock-cells = <1>; 133 clocks = <&xtal32k &xtal24m>; 134 clock-names = "xtal_32KHz", "xtal_24Mhz"; 135 }; 136 137 iomuxc: pinctrl { 138 compatible = "fsl,imx8qxp-iomuxc"; 139 }; 140 141 pd: imx8qx-pd { 142 compatible = "fsl,imx8qxp-scu-pd"; 143 #power-domain-cells = <1>; 144 }; 145 146 rtc: rtc { 147 compatible = "fsl,imx8qxp-sc-rtc"; 148 }; 149 }; 150 151 timer { 152 compatible = "arm,armv8-timer"; 153 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 154 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 155 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 156 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 157 }; 158 159 xtal32k: clock-xtal32k { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 clock-frequency = <32768>; 163 clock-output-names = "xtal_32KHz"; 164 }; 165 166 xtal24m: clock-xtal24m { 167 compatible = "fixed-clock"; 168 #clock-cells = <0>; 169 clock-frequency = <24000000>; 170 clock-output-names = "xtal_24MHz"; 171 }; 172 173 adma_subsys: bus@59000000 { 174 compatible = "simple-bus"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 178 179 adma_lpcg: clock-controller@59000000 { 180 compatible = "fsl,imx8qxp-lpcg-adma"; 181 reg = <0x59000000 0x2000000>; 182 #clock-cells = <1>; 183 }; 184 185 adma_lpuart0: serial@5a060000 { 186 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 187 reg = <0x5a060000 0x1000>; 188 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-parent = <&gic>; 190 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 191 clock-names = "ipg"; 192 power-domains = <&pd IMX_SC_R_UART_0>; 193 status = "disabled"; 194 }; 195 196 adma_lpuart1: serial@5a070000 { 197 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 198 reg = <0x5a070000 0x1000>; 199 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-parent = <&gic>; 201 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 202 clock-names = "ipg"; 203 power-domains = <&pd IMX_SC_R_UART_1>; 204 status = "disabled"; 205 }; 206 207 adma_lpuart2: serial@5a080000 { 208 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 209 reg = <0x5a080000 0x1000>; 210 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-parent = <&gic>; 212 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 213 clock-names = "ipg"; 214 power-domains = <&pd IMX_SC_R_UART_2>; 215 status = "disabled"; 216 }; 217 218 adma_lpuart3: serial@5a090000 { 219 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 220 reg = <0x5a090000 0x1000>; 221 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 222 interrupt-parent = <&gic>; 223 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 224 clock-names = "ipg"; 225 power-domains = <&pd IMX_SC_R_UART_3>; 226 status = "disabled"; 227 }; 228 229 adma_i2c0: i2c@5a800000 { 230 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 231 reg = <0x5a800000 0x4000>; 232 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-parent = <&gic>; 234 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 235 clock-names = "per"; 236 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 237 assigned-clock-rates = <24000000>; 238 power-domains = <&pd IMX_SC_R_I2C_0>; 239 status = "disabled"; 240 }; 241 242 adma_i2c1: i2c@5a810000 { 243 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 244 reg = <0x5a810000 0x4000>; 245 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 246 interrupt-parent = <&gic>; 247 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 248 clock-names = "per"; 249 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 250 assigned-clock-rates = <24000000>; 251 power-domains = <&pd IMX_SC_R_I2C_1>; 252 status = "disabled"; 253 }; 254 255 adma_i2c2: i2c@5a820000 { 256 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 257 reg = <0x5a820000 0x4000>; 258 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 259 interrupt-parent = <&gic>; 260 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 261 clock-names = "per"; 262 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 263 assigned-clock-rates = <24000000>; 264 power-domains = <&pd IMX_SC_R_I2C_2>; 265 status = "disabled"; 266 }; 267 268 adma_i2c3: i2c@5a830000 { 269 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 270 reg = <0x5a830000 0x4000>; 271 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-parent = <&gic>; 273 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 274 clock-names = "per"; 275 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 276 assigned-clock-rates = <24000000>; 277 power-domains = <&pd IMX_SC_R_I2C_3>; 278 status = "disabled"; 279 }; 280 }; 281 282 conn_subsys: bus@5b000000 { 283 compatible = "simple-bus"; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 287 288 conn_lpcg: clock-controller@5b200000 { 289 compatible = "fsl,imx8qxp-lpcg-conn"; 290 reg = <0x5b200000 0xb0000>; 291 #clock-cells = <1>; 292 }; 293 294 usdhc1: mmc@5b010000 { 295 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 296 interrupt-parent = <&gic>; 297 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 298 reg = <0x5b010000 0x10000>; 299 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 300 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 301 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 302 clock-names = "ipg", "per", "ahb"; 303 assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 304 assigned-clock-rates = <200000000>; 305 power-domains = <&pd IMX_SC_R_SDHC_0>; 306 status = "disabled"; 307 }; 308 309 usdhc2: mmc@5b020000 { 310 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 311 interrupt-parent = <&gic>; 312 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 313 reg = <0x5b020000 0x10000>; 314 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 315 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 316 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 317 clock-names = "ipg", "per", "ahb"; 318 assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 319 assigned-clock-rates = <200000000>; 320 power-domains = <&pd IMX_SC_R_SDHC_1>; 321 fsl,tuning-start-tap = <20>; 322 fsl,tuning-step= <2>; 323 status = "disabled"; 324 }; 325 326 usdhc3: mmc@5b030000 { 327 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 328 interrupt-parent = <&gic>; 329 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 330 reg = <0x5b030000 0x10000>; 331 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 332 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 333 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 334 clock-names = "ipg", "per", "ahb"; 335 assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; 336 assigned-clock-rates = <200000000>; 337 power-domains = <&pd IMX_SC_R_SDHC_2>; 338 status = "disabled"; 339 }; 340 341 fec1: ethernet@5b040000 { 342 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 343 reg = <0x5b040000 0x10000>; 344 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 349 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 350 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 351 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 352 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 353 fsl,num-tx-queues=<3>; 354 fsl,num-rx-queues=<3>; 355 power-domains = <&pd IMX_SC_R_ENET_0>; 356 status = "disabled"; 357 }; 358 359 fec2: ethernet@5b050000 { 360 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 361 reg = <0x5b050000 0x10000>; 362 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 367 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 368 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 369 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 370 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 371 fsl,num-tx-queues=<3>; 372 fsl,num-rx-queues=<3>; 373 power-domains = <&pd IMX_SC_R_ENET_1>; 374 status = "disabled"; 375 }; 376 }; 377 378 lsio_subsys: bus@5d000000 { 379 compatible = "simple-bus"; 380 #address-cells = <1>; 381 #size-cells = <1>; 382 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 383 384 lsio_lpcg: clock-controller@5d400000 { 385 compatible = "fsl,imx8qxp-lpcg-lsio"; 386 reg = <0x5d400000 0x400000>; 387 #clock-cells = <1>; 388 }; 389 390 lsio_mu0: mailbox@5d1b0000 { 391 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 392 reg = <0x5d1b0000 0x10000>; 393 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 394 #mbox-cells = <2>; 395 status = "disabled"; 396 }; 397 398 lsio_mu1: mailbox@5d1c0000 { 399 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 400 reg = <0x5d1c0000 0x10000>; 401 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 402 #mbox-cells = <2>; 403 }; 404 405 lsio_mu2: mailbox@5d1d0000 { 406 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 407 reg = <0x5d1d0000 0x10000>; 408 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 409 #mbox-cells = <2>; 410 status = "disabled"; 411 }; 412 413 lsio_mu3: mailbox@5d1e0000 { 414 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 415 reg = <0x5d1e0000 0x10000>; 416 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 417 #mbox-cells = <2>; 418 status = "disabled"; 419 }; 420 421 lsio_mu4: mailbox@5d1f0000 { 422 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 423 reg = <0x5d1f0000 0x10000>; 424 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 425 #mbox-cells = <2>; 426 status = "disabled"; 427 }; 428 429 lsio_gpio0: gpio@5d080000 { 430 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 431 reg = <0x5d080000 0x10000>; 432 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 power-domains = <&pd IMX_SC_R_GPIO_0>; 438 }; 439 440 lsio_gpio1: gpio@5d090000 { 441 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 442 reg = <0x5d090000 0x10000>; 443 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 444 gpio-controller; 445 #gpio-cells = <2>; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 power-domains = <&pd IMX_SC_R_GPIO_1>; 449 }; 450 451 lsio_gpio2: gpio@5d0a0000 { 452 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 453 reg = <0x5d0a0000 0x10000>; 454 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 455 gpio-controller; 456 #gpio-cells = <2>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 power-domains = <&pd IMX_SC_R_GPIO_2>; 460 }; 461 462 lsio_gpio3: gpio@5d0b0000 { 463 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 464 reg = <0x5d0b0000 0x10000>; 465 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 power-domains = <&pd IMX_SC_R_GPIO_3>; 471 }; 472 473 lsio_gpio4: gpio@5d0c0000 { 474 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 475 reg = <0x5d0c0000 0x10000>; 476 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 power-domains = <&pd IMX_SC_R_GPIO_4>; 482 }; 483 484 lsio_gpio5: gpio@5d0d0000 { 485 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 486 reg = <0x5d0d0000 0x10000>; 487 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 488 gpio-controller; 489 #gpio-cells = <2>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 power-domains = <&pd IMX_SC_R_GPIO_5>; 493 }; 494 495 lsio_gpio6: gpio@5d0e0000 { 496 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 497 reg = <0x5d0e0000 0x10000>; 498 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 power-domains = <&pd IMX_SC_R_GPIO_6>; 504 }; 505 506 lsio_gpio7: gpio@5d0f0000 { 507 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 508 reg = <0x5d0f0000 0x10000>; 509 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 510 gpio-controller; 511 #gpio-cells = <2>; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 power-domains = <&pd IMX_SC_R_GPIO_7>; 515 }; 516 }; 517 518 watchdog { 519 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 520 timeout-sec = <60>; 521 }; 522}; 523