xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-tqma8mpql.dtsi (revision 840d9a813c8eaa5c55d86525e374a97ca5023b53) 
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8#include "imx8mp.dtsi"
9
10/ {
11	model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
12	compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
13
14	memory@40000000 {
15		device_type = "memory";
16		reg = <0x0 0x40000000 0 0x80000000>;
17	};
18
19	/* identical to buck4_reg, but should never change */
20	reg_vcc3v3: regulator-vcc3v3 {
21		compatible = "regulator-fixed";
22		regulator-name = "VCC3V3";
23		regulator-min-microvolt = <3300000>;
24		regulator-max-microvolt = <3300000>;
25		regulator-always-on;
26	};
27};
28
29&A53_0 {
30	cpu-supply = <&buck2_reg>;
31};
32
33&flexspi {
34	pinctrl-names = "default";
35	pinctrl-0 = <&pinctrl_flexspi0>;
36	status = "okay";
37
38	flash0: flash@0 {
39		reg = <0>;
40		#address-cells = <1>;
41		#size-cells = <1>;
42		compatible = "jedec,spi-nor";
43		spi-max-frequency = <80000000>;
44		spi-tx-bus-width = <1>;
45		spi-rx-bus-width = <4>;
46	};
47};
48
49&i2c1 {
50	clock-frequency = <384000>;
51	pinctrl-names = "default", "gpio";
52	pinctrl-0 = <&pinctrl_i2c1>;
53	pinctrl-1 = <&pinctrl_i2c1_gpio>;
54	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
56	status = "okay";
57
58	se97: temperature-sensor@1b {
59		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
60		reg = <0x1b>;
61	};
62
63	pmic: pmic@25 {
64		reg = <0x25>;
65		compatible = "nxp,pca9450c";
66
67		/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
68		pinctrl-0 = <&pinctrl_pmic>;
69		pinctrl-names = "default";
70		interrupt-parent = <&gpio1>;
71		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
72
73		regulators {
74			/* V_0V85_SOC: 0.85 .. 0.95 */
75			buck1_reg: BUCK1 {
76				regulator-name = "BUCK1";
77				regulator-min-microvolt = <850000>;
78				regulator-max-microvolt = <950000>;
79				regulator-boot-on;
80				regulator-always-on;
81				regulator-ramp-delay = <3125>;
82			};
83
84			/* VDD_ARM */
85			buck2_reg: BUCK2 {
86				regulator-name = "BUCK2";
87				regulator-min-microvolt = <850000>;
88				regulator-max-microvolt = <1000000>;
89				regulator-boot-on;
90				regulator-always-on;
91				nxp,dvs-run-voltage = <950000>;
92				nxp,dvs-standby-voltage = <850000>;
93				regulator-ramp-delay = <3125>;
94			};
95
96			/* VCC3V3 -> VMMC, ... must not be changed */
97			buck4_reg: BUCK4 {
98				regulator-name = "BUCK4";
99				regulator-min-microvolt = <3300000>;
100				regulator-max-microvolt = <3300000>;
101				regulator-boot-on;
102				regulator-always-on;
103			};
104
105			/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
106			buck5_reg: BUCK5 {
107				regulator-name = "BUCK5";
108				regulator-min-microvolt = <1800000>;
109				regulator-max-microvolt = <1800000>;
110				regulator-boot-on;
111				regulator-always-on;
112			};
113
114			/* V_1V1 -> RAM, ... must not be changed */
115			buck6_reg: BUCK6 {
116				regulator-name = "BUCK6";
117				regulator-min-microvolt = <1100000>;
118				regulator-max-microvolt = <1100000>;
119				regulator-boot-on;
120				regulator-always-on;
121			};
122
123			/* V_1V8_SNVS */
124			ldo1_reg: LDO1 {
125				regulator-name = "LDO1";
126				regulator-min-microvolt = <1800000>;
127				regulator-max-microvolt = <1800000>;
128				regulator-boot-on;
129				regulator-always-on;
130			};
131
132			/* V_1V8_ANA */
133			ldo3_reg: LDO3 {
134				regulator-name = "LDO3";
135				regulator-min-microvolt = <1800000>;
136				regulator-max-microvolt = <1800000>;
137				regulator-boot-on;
138				regulator-always-on;
139			};
140
141			/* unused */
142			ldo4_reg: LDO4 {
143				regulator-name = "LDO4";
144				regulator-min-microvolt = <800000>;
145				regulator-max-microvolt = <3300000>;
146			};
147
148			/* VCC SD IO - switched using SD2 VSELECT */
149			ldo5_reg: LDO5 {
150				regulator-name = "LDO5";
151				regulator-min-microvolt = <1800000>;
152				regulator-max-microvolt = <3300000>;
153			};
154		};
155	};
156
157	pcf85063: rtc@51 {
158		compatible = "nxp,pcf85063a";
159		reg = <0x51>;
160	};
161
162	at24c02: eeprom@53 {
163		compatible = "nxp,se97b", "atmel,24c02";
164		read-only;
165		reg = <0x53>;
166		pagesize = <16>;
167		vcc-supply = <&reg_vcc3v3>;
168	};
169
170	m24c64: eeprom@57 {
171		compatible = "atmel,24c64";
172		reg = <0x57>;
173		pagesize = <32>;
174		vcc-supply = <&reg_vcc3v3>;
175	};
176};
177
178&usdhc3 {
179	pinctrl-names = "default", "state_100mhz", "state_200mhz";
180	pinctrl-0 = <&pinctrl_usdhc3>;
181	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
182	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
183	bus-width = <8>;
184	non-removable;
185	no-sd;
186	no-sdio;
187	vmmc-supply = <&reg_vcc3v3>;
188	vqmmc-supply = <&buck5_reg>;
189	status = "okay";
190};
191
192&wdog1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_wdog>;
195	fsl,ext-reset-output;
196	status = "okay";
197};
198
199&iomuxc {
200	pinctrl_flexspi0: flexspi0grp {
201		fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK	0x142>,
202			   <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,
203			   <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,
204			   <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,
205			   <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,
206			   <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>;
207	};
208
209	pinctrl_i2c1: i2c1grp {
210		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001e2>,
211			   <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001e2>;
212	};
213
214	pinctrl_i2c1_gpio: i2c1-gpiogrp {
215		fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001e2>,
216			   <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001e2>;
217	};
218
219	pinctrl_pmic: pmicirqgrp {
220		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x1c0>;
221	};
222
223	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
224		fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x10>;
225	};
226
227	pinctrl_usdhc3: usdhc3grp {
228		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
229			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
230			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
231			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
232			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
233			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
234			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
235			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
236			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
237			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
238			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
239			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
240	};
241
242	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
243		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
244			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
245			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
246			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
247			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
248			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
249			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
250			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
251			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
252			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
253			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
254			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
255	};
256
257	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
258		fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
259			   <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>,
260			   <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0	0x1d4>,
261			   <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1	0x1d4>,
262			   <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2	0x1d4>,
263			   <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3	0x1d4>,
264			   <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4	0x1d4>,
265			   <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5	0x1d4>,
266			   <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6	0x1d4>,
267			   <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
268			   <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE	0x84>,
269			   <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x84>;
270	};
271
272	pinctrl_wdog: wdoggrp {
273		fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x1c4>;
274	};
275};
276