1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk40m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <40000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 hdmi_connector: hdmi-connector { 57 compatible = "hdmi-connector"; 58 ddc-i2c-bus = <&i2c2>; 59 /* Verdin PWM_3_DSI (SODIMM 19) */ 60 hpd-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 61 label = "hdmi"; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>; 64 type = "a"; 65 status = "disabled"; 66 }; 67 68 panel_lvds: panel-lvds { 69 compatible = "panel-lvds"; 70 backlight = <&backlight>; 71 data-mapping = "vesa-24"; 72 status = "disabled"; 73 }; 74 75 /* Carrier Board Supplies */ 76 reg_1p8v: regulator-1p8v { 77 compatible = "regulator-fixed"; 78 regulator-max-microvolt = <1800000>; 79 regulator-min-microvolt = <1800000>; 80 regulator-name = "+V1.8_SW"; 81 }; 82 83 reg_3p3v: regulator-3p3v { 84 compatible = "regulator-fixed"; 85 regulator-max-microvolt = <3300000>; 86 regulator-min-microvolt = <3300000>; 87 regulator-name = "+V3.3_SW"; 88 }; 89 90 reg_5p0v: regulator-5p0v { 91 compatible = "regulator-fixed"; 92 regulator-max-microvolt = <5000000>; 93 regulator-min-microvolt = <5000000>; 94 regulator-name = "+V5_SW"; 95 }; 96 97 /* Non PMIC On-module Supplies */ 98 reg_ethphy: regulator-ethphy { 99 compatible = "regulator-fixed"; 100 enable-active-high; 101 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 102 off-on-delay-us = <500000>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_reg_eth>; 105 regulator-always-on; 106 regulator-boot-on; 107 regulator-max-microvolt = <3300000>; 108 regulator-min-microvolt = <3300000>; 109 regulator-name = "On-module +V3.3_ETH"; 110 startup-delay-us = <200000>; 111 }; 112 113 reg_usb_otg1_vbus: regulator-usb-otg1 { 114 compatible = "regulator-fixed"; 115 enable-active-high; 116 /* Verdin USB_1_EN (SODIMM 155) */ 117 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_reg_usb1_en>; 120 regulator-max-microvolt = <5000000>; 121 regulator-min-microvolt = <5000000>; 122 regulator-name = "USB_1_EN"; 123 }; 124 125 reg_usb_otg2_vbus: regulator-usb-otg2 { 126 compatible = "regulator-fixed"; 127 enable-active-high; 128 /* Verdin USB_2_EN (SODIMM 185) */ 129 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_reg_usb2_en>; 132 regulator-max-microvolt = <5000000>; 133 regulator-min-microvolt = <5000000>; 134 regulator-name = "USB_2_EN"; 135 }; 136 137 reg_usdhc2_vmmc: regulator-usdhc2 { 138 compatible = "regulator-fixed"; 139 enable-active-high; 140 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 141 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 142 off-on-delay-us = <100000>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 145 regulator-max-microvolt = <3300000>; 146 regulator-min-microvolt = <3300000>; 147 regulator-name = "+V3.3_SD"; 148 startup-delay-us = <20000>; 149 }; 150 151 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 152 compatible = "regulator-gpio"; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 155 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 156 regulator-max-microvolt = <3300000>; 157 regulator-min-microvolt = <1800000>; 158 states = <1800000 0x1>, 159 <3300000 0x0>; 160 regulator-name = "PMIC_USDHC_VSELECT"; 161 vin-supply = <®_nvcc_sd>; 162 }; 163 164 reserved-memory { 165 #address-cells = <2>; 166 #size-cells = <2>; 167 ranges; 168 169 /* Use the kernel configuration settings instead */ 170 /delete-node/ linux,cma; 171 }; 172}; 173 174&A53_0 { 175 cpu-supply = <®_vdd_arm>; 176}; 177 178&A53_1 { 179 cpu-supply = <®_vdd_arm>; 180}; 181 182&A53_2 { 183 cpu-supply = <®_vdd_arm>; 184}; 185 186&A53_3 { 187 cpu-supply = <®_vdd_arm>; 188}; 189 190&cpu_alert0 { 191 temperature = <95000>; 192}; 193 194&cpu_crit0 { 195 temperature = <105000>; 196}; 197 198&ddrc { 199 operating-points-v2 = <&ddrc_opp_table>; 200 201 ddrc_opp_table: opp-table { 202 compatible = "operating-points-v2"; 203 204 opp-25000000 { 205 opp-hz = /bits/ 64 <25000000>; 206 }; 207 208 opp-100000000 { 209 opp-hz = /bits/ 64 <100000000>; 210 }; 211 212 opp-750000000 { 213 opp-hz = /bits/ 64 <750000000>; 214 }; 215 }; 216}; 217 218/* Verdin SPI_1 */ 219&ecspi2 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_ecspi2>; 225}; 226 227/* Verdin CAN_1 (On-module) */ 228&ecspi3 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_ecspi3>; 234 status = "okay"; 235 236 can1: can@0 { 237 compatible = "microchip,mcp251xfd"; 238 clocks = <&clk40m>; 239 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_can1_int>; 242 reg = <0>; 243 spi-max-frequency = <8500000>; 244 }; 245}; 246 247/* Verdin ETH_1 (On-module PHY) */ 248&fec1 { 249 fsl,magic-packet; 250 phy-handle = <ðphy0>; 251 phy-mode = "rgmii-id"; 252 phy-supply = <®_ethphy>; 253 pinctrl-names = "default", "sleep"; 254 pinctrl-0 = <&pinctrl_fec1>; 255 pinctrl-1 = <&pinctrl_fec1_sleep>; 256 257 mdio { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 261 ethphy0: ethernet-phy@7 { 262 compatible = "ethernet-phy-ieee802.3-c22"; 263 interrupt-parent = <&gpio1>; 264 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 265 micrel,led-mode = <0>; 266 reg = <7>; 267 }; 268 }; 269}; 270 271/* Verdin QSPI_1 */ 272&flexspi { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_flexspi0>; 275}; 276 277&gpio1 { 278 gpio-line-names = "SODIMM_216", 279 "SODIMM_19", 280 "", 281 "", 282 "PMIC_USDHC_VSELECT", 283 "", 284 "", 285 "", 286 "SODIMM_220", 287 "SODIMM_222", 288 "", 289 "SODIMM_218", 290 "SODIMM_155", 291 "SODIMM_157", 292 "SODIMM_185", 293 "SODIMM_187"; 294}; 295 296&gpio2 { 297 gpio-line-names = "", 298 "", 299 "", 300 "", 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "SODIMM_84", 310 "SODIMM_78", 311 "SODIMM_74", 312 "SODIMM_80", 313 "SODIMM_82", 314 "SODIMM_70", 315 "SODIMM_72"; 316}; 317 318&gpio5 { 319 gpio-line-names = "SODIMM_131", 320 "", 321 "SODIMM_91", 322 "SODIMM_16", 323 "SODIMM_15", 324 "SODIMM_208", 325 "SODIMM_137", 326 "SODIMM_139", 327 "SODIMM_141", 328 "SODIMM_143", 329 "SODIMM_196", 330 "SODIMM_200", 331 "SODIMM_198", 332 "SODIMM_202", 333 "", 334 "", 335 "SODIMM_55", 336 "SODIMM_53", 337 "SODIMM_95", 338 "SODIMM_93", 339 "SODIMM_14", 340 "SODIMM_12", 341 "", 342 "", 343 "", 344 "", 345 "SODIMM_210", 346 "SODIMM_212", 347 "SODIMM_151", 348 "SODIMM_153"; 349 350 ctrl-sleep-moci-hog { 351 gpio-hog; 352 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 353 gpios = <1 GPIO_ACTIVE_HIGH>; 354 line-name = "CTRL_SLEEP_MOCI#"; 355 output-high; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 358 }; 359}; 360 361/* On-module I2C */ 362&i2c1 { 363 clock-frequency = <400000>; 364 pinctrl-names = "default", "gpio"; 365 pinctrl-0 = <&pinctrl_i2c1>; 366 pinctrl-1 = <&pinctrl_i2c1_gpio>; 367 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 368 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 369 status = "okay"; 370 371 pca9450: pmic@25 { 372 compatible = "nxp,pca9450a"; 373 interrupt-parent = <&gpio1>; 374 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 375 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_pmic>; 378 reg = <0x25>; 379 380 /* 381 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 382 * behind this PMIC. 383 */ 384 385 regulators { 386 reg_vdd_soc: BUCK1 { 387 nxp,dvs-run-voltage = <850000>; 388 nxp,dvs-standby-voltage = <800000>; 389 regulator-always-on; 390 regulator-boot-on; 391 regulator-max-microvolt = <850000>; 392 regulator-min-microvolt = <800000>; 393 regulator-name = "On-module +VDD_SOC (BUCK1)"; 394 regulator-ramp-delay = <3125>; 395 }; 396 397 reg_vdd_arm: BUCK2 { 398 nxp,dvs-run-voltage = <950000>; 399 nxp,dvs-standby-voltage = <850000>; 400 regulator-always-on; 401 regulator-boot-on; 402 regulator-max-microvolt = <1050000>; 403 regulator-min-microvolt = <805000>; 404 regulator-name = "On-module +VDD_ARM (BUCK2)"; 405 regulator-ramp-delay = <3125>; 406 }; 407 408 reg_vdd_dram: BUCK3 { 409 regulator-always-on; 410 regulator-boot-on; 411 regulator-max-microvolt = <1000000>; 412 regulator-min-microvolt = <805000>; 413 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 414 }; 415 416 reg_vdd_3v3: BUCK4 { 417 regulator-always-on; 418 regulator-boot-on; 419 regulator-max-microvolt = <3300000>; 420 regulator-min-microvolt = <3300000>; 421 regulator-name = "On-module +V3.3 (BUCK4)"; 422 }; 423 424 reg_vdd_1v8: BUCK5 { 425 regulator-always-on; 426 regulator-boot-on; 427 regulator-max-microvolt = <1800000>; 428 regulator-min-microvolt = <1800000>; 429 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 430 }; 431 432 reg_nvcc_dram: BUCK6 { 433 regulator-always-on; 434 regulator-boot-on; 435 regulator-max-microvolt = <1100000>; 436 regulator-min-microvolt = <1100000>; 437 regulator-name = "On-module +VDD_DDR (BUCK6)"; 438 }; 439 440 reg_nvcc_snvs: LDO1 { 441 regulator-always-on; 442 regulator-boot-on; 443 regulator-max-microvolt = <1800000>; 444 regulator-min-microvolt = <1800000>; 445 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 446 }; 447 448 reg_vdd_snvs: LDO2 { 449 regulator-always-on; 450 regulator-boot-on; 451 regulator-max-microvolt = <800000>; 452 regulator-min-microvolt = <800000>; 453 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 454 }; 455 456 reg_vdda: LDO3 { 457 regulator-always-on; 458 regulator-boot-on; 459 regulator-max-microvolt = <1800000>; 460 regulator-min-microvolt = <1800000>; 461 regulator-name = "On-module +V1.8A (LDO3)"; 462 }; 463 464 reg_vdd_phy: LDO4 { 465 regulator-always-on; 466 regulator-boot-on; 467 regulator-max-microvolt = <900000>; 468 regulator-min-microvolt = <900000>; 469 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 470 }; 471 472 reg_nvcc_sd: LDO5 { 473 regulator-max-microvolt = <3300000>; 474 regulator-min-microvolt = <1800000>; 475 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 476 }; 477 }; 478 }; 479 480 rtc_i2c: rtc@32 { 481 compatible = "epson,rx8130"; 482 reg = <0x32>; 483 }; 484 485 adc@49 { 486 compatible = "ti,ads1015"; 487 reg = <0x49>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 491 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 492 channel@0 { 493 reg = <0>; 494 ti,datarate = <4>; 495 ti,gain = <2>; 496 }; 497 498 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 499 channel@1 { 500 reg = <1>; 501 ti,datarate = <4>; 502 ti,gain = <2>; 503 }; 504 505 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 506 channel@2 { 507 reg = <2>; 508 ti,datarate = <4>; 509 ti,gain = <2>; 510 }; 511 512 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 513 channel@3 { 514 reg = <3>; 515 ti,datarate = <4>; 516 ti,gain = <2>; 517 }; 518 519 /* Verdin I2C_1 ADC_4 */ 520 channel@4 { 521 reg = <4>; 522 ti,datarate = <4>; 523 ti,gain = <2>; 524 }; 525 526 /* Verdin I2C_1 ADC_3 */ 527 channel@5 { 528 reg = <5>; 529 ti,datarate = <4>; 530 ti,gain = <2>; 531 }; 532 533 /* Verdin I2C_1 ADC_2 */ 534 channel@6 { 535 reg = <6>; 536 ti,datarate = <4>; 537 ti,gain = <2>; 538 }; 539 540 /* Verdin I2C_1 ADC_1 */ 541 channel@7 { 542 reg = <7>; 543 ti,datarate = <4>; 544 ti,gain = <2>; 545 }; 546 }; 547 548 eeprom@50 { 549 compatible = "st,24c02"; 550 pagesize = <16>; 551 reg = <0x50>; 552 }; 553}; 554 555/* Verdin I2C_2_DSI */ 556&i2c2 { 557 clock-frequency = <10000>; 558 pinctrl-names = "default", "gpio"; 559 pinctrl-0 = <&pinctrl_i2c2>; 560 pinctrl-1 = <&pinctrl_i2c2_gpio>; 561 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 562 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 563 status = "disabled"; 564}; 565 566/* Verdin I2C_3_HDMI N/A */ 567 568/* Verdin I2C_4_CSI */ 569&i2c3 { 570 clock-frequency = <400000>; 571 pinctrl-names = "default", "gpio"; 572 pinctrl-0 = <&pinctrl_i2c3>; 573 pinctrl-1 = <&pinctrl_i2c3_gpio>; 574 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 575 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 576}; 577 578/* Verdin I2C_1 */ 579&i2c4 { 580 clock-frequency = <400000>; 581 pinctrl-names = "default", "gpio"; 582 pinctrl-0 = <&pinctrl_i2c4>; 583 pinctrl-1 = <&pinctrl_i2c4_gpio>; 584 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 585 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 586 587 gpio_expander_21: gpio-expander@21 { 588 compatible = "nxp,pcal6416"; 589 #gpio-cells = <2>; 590 gpio-controller; 591 reg = <0x21>; 592 vcc-supply = <®_3p3v>; 593 status = "disabled"; 594 }; 595 596 lvds_ti_sn65dsi84: bridge@2c { 597 compatible = "ti,sn65dsi84"; 598 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 599 /* Verdin GPIO_10_DSI (SODIMM 21) */ 600 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 603 reg = <0x2c>; 604 status = "disabled"; 605 }; 606 607 /* Current measurement into module VCC */ 608 hwmon: hwmon@40 { 609 compatible = "ti,ina219"; 610 reg = <0x40>; 611 shunt-resistor = <10000>; 612 status = "disabled"; 613 }; 614 615 hdmi_lontium_lt8912: hdmi@48 { 616 compatible = "lontium,lt8912b"; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 619 reg = <0x48>; 620 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 621 /* Verdin GPIO_10_DSI (SODIMM 21) */ 622 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 623 status = "disabled"; 624 }; 625 626 atmel_mxt_ts: touch@4a { 627 compatible = "atmel,maxtouch"; 628 /* 629 * Verdin GPIO_9_DSI 630 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 631 */ 632 interrupt-parent = <&gpio3>; 633 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 636 reg = <0x4a>; 637 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 638 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 639 status = "disabled"; 640 }; 641 642 /* Temperature sensor on carrier board */ 643 hwmon_temp: sensor@4f { 644 compatible = "ti,tmp75c"; 645 reg = <0x4f>; 646 status = "disabled"; 647 }; 648 649 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 650 eeprom_display_adapter: eeprom@50 { 651 compatible = "st,24c02"; 652 pagesize = <16>; 653 reg = <0x50>; 654 status = "disabled"; 655 }; 656 657 /* EEPROM on carrier board */ 658 eeprom_carrier_board: eeprom@57 { 659 compatible = "st,24c02"; 660 pagesize = <16>; 661 reg = <0x57>; 662 status = "disabled"; 663 }; 664}; 665 666/* Verdin PCIE_1 */ 667&pcie0 { 668 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 669 <&clk IMX8MM_CLK_PCIE1_CTRL>; 670 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 671 <&clk IMX8MM_SYS_PLL2_250M>; 672 assigned-clock-rates = <10000000>, <250000000>; 673 pinctrl-names = "default"; 674 pinctrl-0 = <&pinctrl_pcie0>; 675 /* PCIE_1_RESET# (SODIMM 244) */ 676 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 677}; 678 679&pcie_phy { 680 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 681 clock-names = "ref"; 682 fsl,clkreq-unsupported; 683 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 684 fsl,tx-deemph-gen1 = <0x2d>; 685 fsl,tx-deemph-gen2 = <0xf>; 686}; 687 688/* Verdin PWM_3_DSI */ 689&pwm1 { 690 pinctrl-names = "default"; 691 pinctrl-0 = <&pinctrl_pwm_1>; 692 #pwm-cells = <3>; 693}; 694 695/* Verdin PWM_1 */ 696&pwm2 { 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pinctrl_pwm_2>; 699 #pwm-cells = <3>; 700}; 701 702/* Verdin PWM_2 */ 703&pwm3 { 704 pinctrl-names = "default"; 705 pinctrl-0 = <&pinctrl_pwm_3>; 706 #pwm-cells = <3>; 707}; 708 709/* Verdin I2S_1 */ 710&sai2 { 711 #sound-dai-cells = <0>; 712 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 713 assigned-clock-rates = <24576000>; 714 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_sai2>; 717}; 718 719&snvs_pwrkey { 720 status = "okay"; 721}; 722 723/* Verdin UART_3, used as the Linux console */ 724&uart1 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&pinctrl_uart1>; 727}; 728 729/* Verdin UART_1 */ 730&uart2 { 731 pinctrl-names = "default"; 732 pinctrl-0 = <&pinctrl_uart2>; 733 uart-has-rtscts; 734}; 735 736/* Verdin UART_2 */ 737&uart3 { 738 pinctrl-names = "default"; 739 pinctrl-0 = <&pinctrl_uart3>; 740 uart-has-rtscts; 741}; 742 743/* 744 * Verdin UART_4 745 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 746 */ 747&uart4 { 748 pinctrl-names = "default"; 749 pinctrl-0 = <&pinctrl_uart4>; 750}; 751 752/* Verdin USB_1 */ 753&usbotg1 { 754 adp-disable; 755 dr_mode = "otg"; 756 hnp-disable; 757 samsung,picophy-dc-vol-level-adjust = <7>; 758 samsung,picophy-pre-emp-curr-control = <3>; 759 srp-disable; 760 vbus-supply = <®_usb_otg1_vbus>; 761}; 762 763/* Verdin USB_2 */ 764&usbotg2 { 765 dr_mode = "host"; 766 samsung,picophy-dc-vol-level-adjust = <7>; 767 samsung,picophy-pre-emp-curr-control = <3>; 768 vbus-supply = <®_usb_otg2_vbus>; 769}; 770 771&usbphynop1 { 772 vcc-supply = <®_vdd_3v3>; 773}; 774 775&usbphynop2 { 776 power-domains = <&pgc_otg2>; 777 vcc-supply = <®_vdd_3v3>; 778}; 779 780/* On-module eMMC */ 781&usdhc1 { 782 bus-width = <8>; 783 keep-power-in-suspend; 784 non-removable; 785 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 786 pinctrl-0 = <&pinctrl_usdhc1>; 787 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 788 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 789 status = "okay"; 790}; 791 792/* Verdin SD_1 */ 793&usdhc2 { 794 bus-width = <4>; 795 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 796 disable-wp; 797 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 798 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 799 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 800 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 801 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 802 vmmc-supply = <®_usdhc2_vmmc>; 803 vqmmc-supply = <®_usdhc2_vqmmc>; 804}; 805 806&wdog1 { 807 fsl,ext-reset-output; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&pinctrl_wdog>; 810 status = "okay"; 811}; 812 813&iomuxc { 814 pinctrl-names = "default"; 815 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 816 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 817 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 818 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 819 <&pinctrl_pmic_tpm_ena>; 820 821 pinctrl_can1_int: can1intgrp { 822 fsl,pins = 823 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 824 }; 825 826 pinctrl_can2_int: can2intgrp { 827 fsl,pins = 828 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 829 }; 830 831 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 832 fsl,pins = 833 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 834 }; 835 836 pinctrl_ecspi2: ecspi2grp { 837 fsl,pins = 838 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 839 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 840 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 841 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 842 }; 843 844 pinctrl_ecspi3: ecspi3grp { 845 fsl,pins = 846 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 847 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 848 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 849 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 850 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 851 }; 852 853 pinctrl_fec1: fec1grp { 854 fsl,pins = 855 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 856 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 857 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 858 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 859 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 860 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 861 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 862 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 863 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 864 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 865 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 866 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 867 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 868 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 869 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 870 }; 871 872 pinctrl_fec1_sleep: fec1-sleepgrp { 873 fsl,pins = 874 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 875 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 876 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 877 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 878 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 879 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 880 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 881 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 882 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 883 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 884 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 885 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 886 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 887 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 888 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 889 }; 890 891 pinctrl_flexspi0: flexspi0grp { 892 fsl,pins = 893 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 894 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 895 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 896 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 897 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 898 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 899 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 900 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 901 }; 902 903 pinctrl_gpio1: gpio1grp { 904 fsl,pins = 905 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 906 }; 907 908 pinctrl_gpio2: gpio2grp { 909 fsl,pins = 910 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 911 }; 912 913 pinctrl_gpio3: gpio3grp { 914 fsl,pins = 915 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 916 }; 917 918 pinctrl_gpio4: gpio4grp { 919 fsl,pins = 920 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 921 }; 922 923 pinctrl_gpio5: gpio5grp { 924 fsl,pins = 925 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 926 }; 927 928 pinctrl_gpio6: gpio6grp { 929 fsl,pins = 930 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 931 }; 932 933 pinctrl_gpio7: gpio7grp { 934 fsl,pins = 935 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 936 }; 937 938 pinctrl_gpio8: gpio8grp { 939 fsl,pins = 940 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 941 }; 942 943 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 944 pinctrl_gpio_9_dsi: gpio9dsigrp { 945 fsl,pins = 946 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c6>; /* SODIMM 17 */ 947 }; 948 949 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 950 pinctrl_gpio_10_dsi: gpio10dsigrp { 951 fsl,pins = 952 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 953 }; 954 955 pinctrl_gpio_hog1: gpiohog1grp { 956 fsl,pins = 957 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 958 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 959 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 960 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 961 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 962 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 963 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 964 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 965 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 966 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 967 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 968 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 969 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 970 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 971 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 972 }; 973 974 pinctrl_gpio_hog2: gpiohog2grp { 975 fsl,pins = 976 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 977 }; 978 979 pinctrl_gpio_hog3: gpiohog3grp { 980 fsl,pins = 981 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 982 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 983 }; 984 985 pinctrl_gpio_keys: gpiokeysgrp { 986 fsl,pins = 987 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 988 }; 989 990 /* On-module I2C */ 991 pinctrl_i2c1: i2c1grp { 992 fsl,pins = 993 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 994 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 995 }; 996 997 pinctrl_i2c1_gpio: i2c1gpiogrp { 998 fsl,pins = 999 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 1000 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 1001 }; 1002 1003 /* Verdin I2C_4_CSI */ 1004 pinctrl_i2c2: i2c2grp { 1005 fsl,pins = 1006 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 1007 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 1008 }; 1009 1010 pinctrl_i2c2_gpio: i2c2gpiogrp { 1011 fsl,pins = 1012 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 1013 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1014 }; 1015 1016 /* Verdin I2C_2_DSI */ 1017 pinctrl_i2c3: i2c3grp { 1018 fsl,pins = 1019 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1020 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1021 }; 1022 1023 pinctrl_i2c3_gpio: i2c3gpiogrp { 1024 fsl,pins = 1025 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1026 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1027 }; 1028 1029 /* Verdin I2C_1 */ 1030 pinctrl_i2c4: i2c4grp { 1031 fsl,pins = 1032 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1033 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1034 }; 1035 1036 pinctrl_i2c4_gpio: i2c4gpiogrp { 1037 fsl,pins = 1038 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1039 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1040 }; 1041 1042 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1043 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1044 fsl,pins = 1045 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1046 }; 1047 1048 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1049 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1050 fsl,pins = 1051 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1052 }; 1053 1054 pinctrl_pcie0: pcie0grp { 1055 fsl,pins = 1056 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1057 /* PMIC_EN_PCIe_CLK, unused */ 1058 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1059 }; 1060 1061 pinctrl_pmic: pmicirqgrp { 1062 fsl,pins = 1063 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1064 }; 1065 1066 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1067 pinctrl_pwm_1: pwm1grp { 1068 fsl,pins = 1069 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1070 }; 1071 1072 pinctrl_pwm_2: pwm2grp { 1073 fsl,pins = 1074 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1075 }; 1076 1077 pinctrl_pwm_3: pwm3grp { 1078 fsl,pins = 1079 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1080 }; 1081 1082 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1083 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1084 fsl,pins = 1085 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1086 }; 1087 1088 pinctrl_reg_eth: regethgrp { 1089 fsl,pins = 1090 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1091 }; 1092 1093 pinctrl_reg_usb1_en: regusb1engrp { 1094 fsl,pins = 1095 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1096 }; 1097 1098 pinctrl_reg_usb2_en: regusb2engrp { 1099 fsl,pins = 1100 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1101 }; 1102 1103 pinctrl_sai2: sai2grp { 1104 fsl,pins = 1105 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1106 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1107 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1108 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1109 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1110 }; 1111 1112 pinctrl_sai5: sai5grp { 1113 fsl,pins = 1114 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1115 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1116 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1117 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1118 }; 1119 1120 /* control signal for optional ATTPM20P or SE050 */ 1121 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1122 fsl,pins = 1123 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1124 }; 1125 1126 pinctrl_tsp: tspgrp { 1127 fsl,pins = 1128 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1129 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1130 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1131 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1132 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1133 }; 1134 1135 pinctrl_uart1: uart1grp { 1136 fsl,pins = 1137 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1138 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1139 }; 1140 1141 pinctrl_uart2: uart2grp { 1142 fsl,pins = 1143 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1144 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1145 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1146 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1147 }; 1148 1149 pinctrl_uart3: uart3grp { 1150 fsl,pins = 1151 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1152 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1153 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1154 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1155 }; 1156 1157 pinctrl_uart4: uart4grp { 1158 fsl,pins = 1159 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1160 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1161 }; 1162 1163 pinctrl_usdhc1: usdhc1grp { 1164 fsl,pins = 1165 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1166 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1167 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1168 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1169 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1170 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1171 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1172 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1173 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1174 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1175 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1176 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1177 }; 1178 1179 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1180 fsl,pins = 1181 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1182 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1183 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1184 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1185 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1186 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1187 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1188 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1189 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1190 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1191 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1192 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1193 }; 1194 1195 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1196 fsl,pins = 1197 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1198 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1199 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1200 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1201 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1202 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1203 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1204 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1205 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1206 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1207 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1208 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1209 }; 1210 1211 pinctrl_usdhc2_cd: usdhc2cdgrp { 1212 fsl,pins = 1213 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1214 }; 1215 1216 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1217 fsl,pins = 1218 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1219 }; 1220 1221 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1222 fsl,pins = 1223 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1224 }; 1225 1226 pinctrl_usdhc2_vsel: usdhc2vselgrp { 1227 fsl,pins = 1228 <MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x10>; /* PMIC_USDHC_VSELECT */ 1229 }; 1230 1231 /* 1232 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1233 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1234 */ 1235 pinctrl_usdhc2: usdhc2grp { 1236 fsl,pins = 1237 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1238 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1239 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1240 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1241 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1242 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1243 }; 1244 1245 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1246 fsl,pins = 1247 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1248 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1249 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1250 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1251 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1252 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1253 }; 1254 1255 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1256 fsl,pins = 1257 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1258 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1259 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1260 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1261 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1262 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1263 }; 1264 1265 /* Avoid backfeeding with removed card power */ 1266 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1267 fsl,pins = 1268 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1269 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1270 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1271 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1272 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1273 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1274 }; 1275 1276 /* 1277 * On-module Wi-Fi/BT or type specific SDHC interface 1278 * (e.g. on X52 extension slot of Verdin Development Board) 1279 */ 1280 pinctrl_usdhc3: usdhc3grp { 1281 fsl,pins = 1282 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1283 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1284 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1285 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1286 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1287 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1288 }; 1289 1290 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1291 fsl,pins = 1292 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1293 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1294 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1295 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1296 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1297 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1298 }; 1299 1300 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1301 fsl,pins = 1302 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1303 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1304 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1305 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1306 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1307 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1308 }; 1309 1310 pinctrl_wdog: wdoggrp { 1311 fsl,pins = 1312 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1313 }; 1314 1315 pinctrl_wifi_ctrl: wifictrlgrp { 1316 fsl,pins = 1317 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1318 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1319 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1320 }; 1321 1322 pinctrl_wifi_i2s: bti2sgrp { 1323 fsl,pins = 1324 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1325 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1326 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1327 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1328 }; 1329 1330 pinctrl_wifi_pwr_en: wifipwrengrp { 1331 fsl,pins = 1332 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1333 }; 1334}; 1335