1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/stm32mp1-clks.h> 8#include <dt-bindings/reset/stm32mp1-resets.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 clock-frequency = <650000000>; 21 device_type = "cpu"; 22 reg = <0>; 23 }; 24 }; 25 26 arm-pmu { 27 compatible = "arm,cortex-a7-pmu"; 28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-affinity = <&cpu0>; 30 interrupt-parent = <&intc>; 31 }; 32 33 psci { 34 compatible = "arm,psci-1.0"; 35 method = "smc"; 36 }; 37 38 intc: interrupt-controller@a0021000 { 39 compatible = "arm,cortex-a7-gic"; 40 #interrupt-cells = <3>; 41 interrupt-controller; 42 reg = <0xa0021000 0x1000>, 43 <0xa0022000 0x2000>; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&intc>; 53 arm,no-tick-in-suspend; 54 }; 55 56 clocks { 57 clk_hse: clk-hse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 63 clk_hsi: clk-hsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <64000000>; 67 }; 68 69 clk_lse: clk-lse { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <32768>; 73 }; 74 75 clk_lsi: clk-lsi { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <32000>; 79 }; 80 81 clk_csi: clk-csi { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <4000000>; 85 }; 86 }; 87 88 thermal-zones { 89 cpu_thermal: cpu-thermal { 90 polling-delay-passive = <0>; 91 polling-delay = <0>; 92 thermal-sensors = <&dts>; 93 94 trips { 95 cpu_alert1: cpu-alert1 { 96 temperature = <85000>; 97 hysteresis = <0>; 98 type = "passive"; 99 }; 100 101 cpu-crit { 102 temperature = <120000>; 103 hysteresis = <0>; 104 type = "critical"; 105 }; 106 }; 107 108 cooling-maps { 109 }; 110 }; 111 }; 112 113 booster: regulator-booster { 114 compatible = "st,stm32mp1-booster"; 115 st,syscfg = <&syscfg>; 116 status = "disabled"; 117 }; 118 119 soc { 120 compatible = "simple-bus"; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 interrupt-parent = <&intc>; 124 ranges; 125 126 timers2: timer@40000000 { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 compatible = "st,stm32-timers"; 130 reg = <0x40000000 0x400>; 131 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 132 interrupt-names = "global"; 133 clocks = <&rcc TIM2_K>; 134 clock-names = "int"; 135 dmas = <&dmamux1 18 0x400 0x1>, 136 <&dmamux1 19 0x400 0x1>, 137 <&dmamux1 20 0x400 0x1>, 138 <&dmamux1 21 0x400 0x1>, 139 <&dmamux1 22 0x400 0x1>; 140 dma-names = "ch1", "ch2", "ch3", "ch4", "up"; 141 status = "disabled"; 142 143 pwm { 144 compatible = "st,stm32-pwm"; 145 #pwm-cells = <3>; 146 status = "disabled"; 147 }; 148 149 timer@1 { 150 compatible = "st,stm32h7-timer-trigger"; 151 reg = <1>; 152 status = "disabled"; 153 }; 154 155 counter { 156 compatible = "st,stm32-timer-counter"; 157 status = "disabled"; 158 }; 159 }; 160 161 timers3: timer@40001000 { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 compatible = "st,stm32-timers"; 165 reg = <0x40001000 0x400>; 166 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-names = "global"; 168 clocks = <&rcc TIM3_K>; 169 clock-names = "int"; 170 dmas = <&dmamux1 23 0x400 0x1>, 171 <&dmamux1 24 0x400 0x1>, 172 <&dmamux1 25 0x400 0x1>, 173 <&dmamux1 26 0x400 0x1>, 174 <&dmamux1 27 0x400 0x1>, 175 <&dmamux1 28 0x400 0x1>; 176 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 177 status = "disabled"; 178 179 pwm { 180 compatible = "st,stm32-pwm"; 181 #pwm-cells = <3>; 182 status = "disabled"; 183 }; 184 185 timer@2 { 186 compatible = "st,stm32h7-timer-trigger"; 187 reg = <2>; 188 status = "disabled"; 189 }; 190 191 counter { 192 compatible = "st,stm32-timer-counter"; 193 status = "disabled"; 194 }; 195 }; 196 197 timers4: timer@40002000 { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 compatible = "st,stm32-timers"; 201 reg = <0x40002000 0x400>; 202 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 203 interrupt-names = "global"; 204 clocks = <&rcc TIM4_K>; 205 clock-names = "int"; 206 dmas = <&dmamux1 29 0x400 0x1>, 207 <&dmamux1 30 0x400 0x1>, 208 <&dmamux1 31 0x400 0x1>, 209 <&dmamux1 32 0x400 0x1>; 210 dma-names = "ch1", "ch2", "ch3", "ch4"; 211 status = "disabled"; 212 213 pwm { 214 compatible = "st,stm32-pwm"; 215 #pwm-cells = <3>; 216 status = "disabled"; 217 }; 218 219 timer@3 { 220 compatible = "st,stm32h7-timer-trigger"; 221 reg = <3>; 222 status = "disabled"; 223 }; 224 225 counter { 226 compatible = "st,stm32-timer-counter"; 227 status = "disabled"; 228 }; 229 }; 230 231 timers5: timer@40003000 { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 compatible = "st,stm32-timers"; 235 reg = <0x40003000 0x400>; 236 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "global"; 238 clocks = <&rcc TIM5_K>; 239 clock-names = "int"; 240 dmas = <&dmamux1 55 0x400 0x1>, 241 <&dmamux1 56 0x400 0x1>, 242 <&dmamux1 57 0x400 0x1>, 243 <&dmamux1 58 0x400 0x1>, 244 <&dmamux1 59 0x400 0x1>, 245 <&dmamux1 60 0x400 0x1>; 246 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; 247 status = "disabled"; 248 249 pwm { 250 compatible = "st,stm32-pwm"; 251 #pwm-cells = <3>; 252 status = "disabled"; 253 }; 254 255 timer@4 { 256 compatible = "st,stm32h7-timer-trigger"; 257 reg = <4>; 258 status = "disabled"; 259 }; 260 261 counter { 262 compatible = "st,stm32-timer-counter"; 263 status = "disabled"; 264 }; 265 }; 266 267 timers6: timer@40004000 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 compatible = "st,stm32-timers"; 271 reg = <0x40004000 0x400>; 272 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "global"; 274 clocks = <&rcc TIM6_K>; 275 clock-names = "int"; 276 dmas = <&dmamux1 69 0x400 0x1>; 277 dma-names = "up"; 278 status = "disabled"; 279 280 timer@5 { 281 compatible = "st,stm32h7-timer-trigger"; 282 reg = <5>; 283 status = "disabled"; 284 }; 285 }; 286 287 timers7: timer@40005000 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "st,stm32-timers"; 291 reg = <0x40005000 0x400>; 292 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 293 interrupt-names = "global"; 294 clocks = <&rcc TIM7_K>; 295 clock-names = "int"; 296 dmas = <&dmamux1 70 0x400 0x1>; 297 dma-names = "up"; 298 status = "disabled"; 299 300 timer@6 { 301 compatible = "st,stm32h7-timer-trigger"; 302 reg = <6>; 303 status = "disabled"; 304 }; 305 }; 306 307 timers12: timer@40006000 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 compatible = "st,stm32-timers"; 311 reg = <0x40006000 0x400>; 312 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-names = "global"; 314 clocks = <&rcc TIM12_K>; 315 clock-names = "int"; 316 status = "disabled"; 317 318 pwm { 319 compatible = "st,stm32-pwm"; 320 #pwm-cells = <3>; 321 status = "disabled"; 322 }; 323 324 timer@11 { 325 compatible = "st,stm32h7-timer-trigger"; 326 reg = <11>; 327 status = "disabled"; 328 }; 329 }; 330 331 timers13: timer@40007000 { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 compatible = "st,stm32-timers"; 335 reg = <0x40007000 0x400>; 336 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 337 interrupt-names = "global"; 338 clocks = <&rcc TIM13_K>; 339 clock-names = "int"; 340 status = "disabled"; 341 342 pwm { 343 compatible = "st,stm32-pwm"; 344 #pwm-cells = <3>; 345 status = "disabled"; 346 }; 347 348 timer@12 { 349 compatible = "st,stm32h7-timer-trigger"; 350 reg = <12>; 351 status = "disabled"; 352 }; 353 }; 354 355 timers14: timer@40008000 { 356 #address-cells = <1>; 357 #size-cells = <0>; 358 compatible = "st,stm32-timers"; 359 reg = <0x40008000 0x400>; 360 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 361 interrupt-names = "global"; 362 clocks = <&rcc TIM14_K>; 363 clock-names = "int"; 364 status = "disabled"; 365 366 pwm { 367 compatible = "st,stm32-pwm"; 368 #pwm-cells = <3>; 369 status = "disabled"; 370 }; 371 372 timer@13 { 373 compatible = "st,stm32h7-timer-trigger"; 374 reg = <13>; 375 status = "disabled"; 376 }; 377 }; 378 379 lptimer1: timer@40009000 { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 compatible = "st,stm32-lptimer"; 383 reg = <0x40009000 0x400>; 384 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&rcc LPTIM1_K>; 386 clock-names = "mux"; 387 wakeup-source; 388 status = "disabled"; 389 390 pwm { 391 compatible = "st,stm32-pwm-lp"; 392 #pwm-cells = <3>; 393 status = "disabled"; 394 }; 395 396 trigger@0 { 397 compatible = "st,stm32-lptimer-trigger"; 398 reg = <0>; 399 status = "disabled"; 400 }; 401 402 counter { 403 compatible = "st,stm32-lptimer-counter"; 404 status = "disabled"; 405 }; 406 }; 407 408 spi2: spi@4000b000 { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 compatible = "st,stm32h7-spi"; 412 reg = <0x4000b000 0x400>; 413 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&rcc SPI2_K>; 415 resets = <&rcc SPI2_R>; 416 dmas = <&dmamux1 39 0x400 0x05>, 417 <&dmamux1 40 0x400 0x05>; 418 dma-names = "rx", "tx"; 419 status = "disabled"; 420 }; 421 422 i2s2: audio-controller@4000b000 { 423 compatible = "st,stm32h7-i2s"; 424 #sound-dai-cells = <0>; 425 reg = <0x4000b000 0x400>; 426 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 427 dmas = <&dmamux1 39 0x400 0x01>, 428 <&dmamux1 40 0x400 0x01>; 429 dma-names = "rx", "tx"; 430 status = "disabled"; 431 }; 432 433 spi3: spi@4000c000 { 434 #address-cells = <1>; 435 #size-cells = <0>; 436 compatible = "st,stm32h7-spi"; 437 reg = <0x4000c000 0x400>; 438 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&rcc SPI3_K>; 440 resets = <&rcc SPI3_R>; 441 dmas = <&dmamux1 61 0x400 0x05>, 442 <&dmamux1 62 0x400 0x05>; 443 dma-names = "rx", "tx"; 444 status = "disabled"; 445 }; 446 447 i2s3: audio-controller@4000c000 { 448 compatible = "st,stm32h7-i2s"; 449 #sound-dai-cells = <0>; 450 reg = <0x4000c000 0x400>; 451 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 452 dmas = <&dmamux1 61 0x400 0x01>, 453 <&dmamux1 62 0x400 0x01>; 454 dma-names = "rx", "tx"; 455 status = "disabled"; 456 }; 457 458 spdifrx: audio-controller@4000d000 { 459 compatible = "st,stm32h7-spdifrx"; 460 #sound-dai-cells = <0>; 461 reg = <0x4000d000 0x400>; 462 clocks = <&rcc SPDIF_K>; 463 clock-names = "kclk"; 464 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 465 dmas = <&dmamux1 93 0x400 0x01>, 466 <&dmamux1 94 0x400 0x01>; 467 dma-names = "rx", "rx-ctrl"; 468 status = "disabled"; 469 }; 470 471 usart2: serial@4000e000 { 472 compatible = "st,stm32h7-uart"; 473 reg = <0x4000e000 0x400>; 474 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&rcc USART2_K>; 476 wakeup-source; 477 dmas = <&dmamux1 43 0x400 0x15>, 478 <&dmamux1 44 0x400 0x11>; 479 dma-names = "rx", "tx"; 480 status = "disabled"; 481 }; 482 483 usart3: serial@4000f000 { 484 compatible = "st,stm32h7-uart"; 485 reg = <0x4000f000 0x400>; 486 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&rcc USART3_K>; 488 wakeup-source; 489 dmas = <&dmamux1 45 0x400 0x15>, 490 <&dmamux1 46 0x400 0x11>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 uart4: serial@40010000 { 496 compatible = "st,stm32h7-uart"; 497 reg = <0x40010000 0x400>; 498 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&rcc UART4_K>; 500 wakeup-source; 501 dmas = <&dmamux1 63 0x400 0x15>, 502 <&dmamux1 64 0x400 0x11>; 503 dma-names = "rx", "tx"; 504 status = "disabled"; 505 }; 506 507 uart5: serial@40011000 { 508 compatible = "st,stm32h7-uart"; 509 reg = <0x40011000 0x400>; 510 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&rcc UART5_K>; 512 wakeup-source; 513 dmas = <&dmamux1 65 0x400 0x15>, 514 <&dmamux1 66 0x400 0x11>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 i2c1: i2c@40012000 { 520 compatible = "st,stm32mp15-i2c"; 521 reg = <0x40012000 0x400>; 522 interrupt-names = "event", "error"; 523 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&rcc I2C1_K>; 526 resets = <&rcc I2C1_R>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 st,syscfg-fmp = <&syscfg 0x4 0x1>; 530 wakeup-source; 531 i2c-analog-filter; 532 status = "disabled"; 533 }; 534 535 i2c2: i2c@40013000 { 536 compatible = "st,stm32mp15-i2c"; 537 reg = <0x40013000 0x400>; 538 interrupt-names = "event", "error"; 539 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&rcc I2C2_K>; 542 resets = <&rcc I2C2_R>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 st,syscfg-fmp = <&syscfg 0x4 0x2>; 546 wakeup-source; 547 i2c-analog-filter; 548 status = "disabled"; 549 }; 550 551 i2c3: i2c@40014000 { 552 compatible = "st,stm32mp15-i2c"; 553 reg = <0x40014000 0x400>; 554 interrupt-names = "event", "error"; 555 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&rcc I2C3_K>; 558 resets = <&rcc I2C3_R>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 st,syscfg-fmp = <&syscfg 0x4 0x4>; 562 wakeup-source; 563 i2c-analog-filter; 564 status = "disabled"; 565 }; 566 567 i2c5: i2c@40015000 { 568 compatible = "st,stm32mp15-i2c"; 569 reg = <0x40015000 0x400>; 570 interrupt-names = "event", "error"; 571 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&rcc I2C5_K>; 574 resets = <&rcc I2C5_R>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 st,syscfg-fmp = <&syscfg 0x4 0x10>; 578 wakeup-source; 579 i2c-analog-filter; 580 status = "disabled"; 581 }; 582 583 cec: cec@40016000 { 584 compatible = "st,stm32-cec"; 585 reg = <0x40016000 0x400>; 586 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&rcc CEC_K>, <&rcc CEC>; 588 clock-names = "cec", "hdmi-cec"; 589 status = "disabled"; 590 }; 591 592 dac: dac@40017000 { 593 compatible = "st,stm32h7-dac-core"; 594 reg = <0x40017000 0x400>; 595 clocks = <&rcc DAC12>; 596 clock-names = "pclk"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 601 dac1: dac@1 { 602 compatible = "st,stm32-dac"; 603 #io-channel-cells = <1>; 604 reg = <1>; 605 status = "disabled"; 606 }; 607 608 dac2: dac@2 { 609 compatible = "st,stm32-dac"; 610 #io-channel-cells = <1>; 611 reg = <2>; 612 status = "disabled"; 613 }; 614 }; 615 616 uart7: serial@40018000 { 617 compatible = "st,stm32h7-uart"; 618 reg = <0x40018000 0x400>; 619 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&rcc UART7_K>; 621 wakeup-source; 622 dmas = <&dmamux1 79 0x400 0x15>, 623 <&dmamux1 80 0x400 0x11>; 624 dma-names = "rx", "tx"; 625 status = "disabled"; 626 }; 627 628 uart8: serial@40019000 { 629 compatible = "st,stm32h7-uart"; 630 reg = <0x40019000 0x400>; 631 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&rcc UART8_K>; 633 wakeup-source; 634 dmas = <&dmamux1 81 0x400 0x15>, 635 <&dmamux1 82 0x400 0x11>; 636 dma-names = "rx", "tx"; 637 status = "disabled"; 638 }; 639 640 timers1: timer@44000000 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 compatible = "st,stm32-timers"; 644 reg = <0x44000000 0x400>; 645 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 649 interrupt-names = "brk", "up", "trg-com", "cc"; 650 clocks = <&rcc TIM1_K>; 651 clock-names = "int"; 652 dmas = <&dmamux1 11 0x400 0x1>, 653 <&dmamux1 12 0x400 0x1>, 654 <&dmamux1 13 0x400 0x1>, 655 <&dmamux1 14 0x400 0x1>, 656 <&dmamux1 15 0x400 0x1>, 657 <&dmamux1 16 0x400 0x1>, 658 <&dmamux1 17 0x400 0x1>; 659 dma-names = "ch1", "ch2", "ch3", "ch4", 660 "up", "trig", "com"; 661 status = "disabled"; 662 663 pwm { 664 compatible = "st,stm32-pwm"; 665 #pwm-cells = <3>; 666 status = "disabled"; 667 }; 668 669 timer@0 { 670 compatible = "st,stm32h7-timer-trigger"; 671 reg = <0>; 672 status = "disabled"; 673 }; 674 675 counter { 676 compatible = "st,stm32-timer-counter"; 677 status = "disabled"; 678 }; 679 }; 680 681 timers8: timer@44001000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "st,stm32-timers"; 685 reg = <0x44001000 0x400>; 686 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "brk", "up", "trg-com", "cc"; 691 clocks = <&rcc TIM8_K>; 692 clock-names = "int"; 693 dmas = <&dmamux1 47 0x400 0x1>, 694 <&dmamux1 48 0x400 0x1>, 695 <&dmamux1 49 0x400 0x1>, 696 <&dmamux1 50 0x400 0x1>, 697 <&dmamux1 51 0x400 0x1>, 698 <&dmamux1 52 0x400 0x1>, 699 <&dmamux1 53 0x400 0x1>; 700 dma-names = "ch1", "ch2", "ch3", "ch4", 701 "up", "trig", "com"; 702 status = "disabled"; 703 704 pwm { 705 compatible = "st,stm32-pwm"; 706 #pwm-cells = <3>; 707 status = "disabled"; 708 }; 709 710 timer@7 { 711 compatible = "st,stm32h7-timer-trigger"; 712 reg = <7>; 713 status = "disabled"; 714 }; 715 716 counter { 717 compatible = "st,stm32-timer-counter"; 718 status = "disabled"; 719 }; 720 }; 721 722 usart6: serial@44003000 { 723 compatible = "st,stm32h7-uart"; 724 reg = <0x44003000 0x400>; 725 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&rcc USART6_K>; 727 wakeup-source; 728 dmas = <&dmamux1 71 0x400 0x15>, 729 <&dmamux1 72 0x400 0x11>; 730 dma-names = "rx", "tx"; 731 status = "disabled"; 732 }; 733 734 spi1: spi@44004000 { 735 #address-cells = <1>; 736 #size-cells = <0>; 737 compatible = "st,stm32h7-spi"; 738 reg = <0x44004000 0x400>; 739 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&rcc SPI1_K>; 741 resets = <&rcc SPI1_R>; 742 dmas = <&dmamux1 37 0x400 0x05>, 743 <&dmamux1 38 0x400 0x05>; 744 dma-names = "rx", "tx"; 745 status = "disabled"; 746 }; 747 748 i2s1: audio-controller@44004000 { 749 compatible = "st,stm32h7-i2s"; 750 #sound-dai-cells = <0>; 751 reg = <0x44004000 0x400>; 752 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 753 dmas = <&dmamux1 37 0x400 0x01>, 754 <&dmamux1 38 0x400 0x01>; 755 dma-names = "rx", "tx"; 756 status = "disabled"; 757 }; 758 759 spi4: spi@44005000 { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 compatible = "st,stm32h7-spi"; 763 reg = <0x44005000 0x400>; 764 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&rcc SPI4_K>; 766 resets = <&rcc SPI4_R>; 767 dmas = <&dmamux1 83 0x400 0x05>, 768 <&dmamux1 84 0x400 0x05>; 769 dma-names = "rx", "tx"; 770 status = "disabled"; 771 }; 772 773 timers15: timer@44006000 { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 compatible = "st,stm32-timers"; 777 reg = <0x44006000 0x400>; 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 779 interrupt-names = "global"; 780 clocks = <&rcc TIM15_K>; 781 clock-names = "int"; 782 dmas = <&dmamux1 105 0x400 0x1>, 783 <&dmamux1 106 0x400 0x1>, 784 <&dmamux1 107 0x400 0x1>, 785 <&dmamux1 108 0x400 0x1>; 786 dma-names = "ch1", "up", "trig", "com"; 787 status = "disabled"; 788 789 pwm { 790 compatible = "st,stm32-pwm"; 791 #pwm-cells = <3>; 792 status = "disabled"; 793 }; 794 795 timer@14 { 796 compatible = "st,stm32h7-timer-trigger"; 797 reg = <14>; 798 status = "disabled"; 799 }; 800 }; 801 802 timers16: timer@44007000 { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 compatible = "st,stm32-timers"; 806 reg = <0x44007000 0x400>; 807 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-names = "global"; 809 clocks = <&rcc TIM16_K>; 810 clock-names = "int"; 811 dmas = <&dmamux1 109 0x400 0x1>, 812 <&dmamux1 110 0x400 0x1>; 813 dma-names = "ch1", "up"; 814 status = "disabled"; 815 816 pwm { 817 compatible = "st,stm32-pwm"; 818 #pwm-cells = <3>; 819 status = "disabled"; 820 }; 821 timer@15 { 822 compatible = "st,stm32h7-timer-trigger"; 823 reg = <15>; 824 status = "disabled"; 825 }; 826 }; 827 828 timers17: timer@44008000 { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 compatible = "st,stm32-timers"; 832 reg = <0x44008000 0x400>; 833 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "global"; 835 clocks = <&rcc TIM17_K>; 836 clock-names = "int"; 837 dmas = <&dmamux1 111 0x400 0x1>, 838 <&dmamux1 112 0x400 0x1>; 839 dma-names = "ch1", "up"; 840 status = "disabled"; 841 842 pwm { 843 compatible = "st,stm32-pwm"; 844 #pwm-cells = <3>; 845 status = "disabled"; 846 }; 847 848 timer@16 { 849 compatible = "st,stm32h7-timer-trigger"; 850 reg = <16>; 851 status = "disabled"; 852 }; 853 }; 854 855 spi5: spi@44009000 { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 compatible = "st,stm32h7-spi"; 859 reg = <0x44009000 0x400>; 860 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&rcc SPI5_K>; 862 resets = <&rcc SPI5_R>; 863 dmas = <&dmamux1 85 0x400 0x05>, 864 <&dmamux1 86 0x400 0x05>; 865 dma-names = "rx", "tx"; 866 status = "disabled"; 867 }; 868 869 sai1: sai@4400a000 { 870 compatible = "st,stm32h7-sai"; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 ranges = <0 0x4400a000 0x400>; 874 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; 875 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 876 resets = <&rcc SAI1_R>; 877 status = "disabled"; 878 879 sai1a: audio-controller@4400a004 { 880 #sound-dai-cells = <0>; 881 882 compatible = "st,stm32-sai-sub-a"; 883 reg = <0x4 0x20>; 884 clocks = <&rcc SAI1_K>; 885 clock-names = "sai_ck"; 886 dmas = <&dmamux1 87 0x400 0x01>; 887 status = "disabled"; 888 }; 889 890 sai1b: audio-controller@4400a024 { 891 #sound-dai-cells = <0>; 892 compatible = "st,stm32-sai-sub-b"; 893 reg = <0x24 0x20>; 894 clocks = <&rcc SAI1_K>; 895 clock-names = "sai_ck"; 896 dmas = <&dmamux1 88 0x400 0x01>; 897 status = "disabled"; 898 }; 899 }; 900 901 sai2: sai@4400b000 { 902 compatible = "st,stm32h7-sai"; 903 #address-cells = <1>; 904 #size-cells = <1>; 905 ranges = <0 0x4400b000 0x400>; 906 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; 907 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 908 resets = <&rcc SAI2_R>; 909 status = "disabled"; 910 911 sai2a: audio-controller@4400b004 { 912 #sound-dai-cells = <0>; 913 compatible = "st,stm32-sai-sub-a"; 914 reg = <0x4 0x20>; 915 clocks = <&rcc SAI2_K>; 916 clock-names = "sai_ck"; 917 dmas = <&dmamux1 89 0x400 0x01>; 918 status = "disabled"; 919 }; 920 921 sai2b: audio-controller@4400b024 { 922 #sound-dai-cells = <0>; 923 compatible = "st,stm32-sai-sub-b"; 924 reg = <0x24 0x20>; 925 clocks = <&rcc SAI2_K>; 926 clock-names = "sai_ck"; 927 dmas = <&dmamux1 90 0x400 0x01>; 928 status = "disabled"; 929 }; 930 }; 931 932 sai3: sai@4400c000 { 933 compatible = "st,stm32h7-sai"; 934 #address-cells = <1>; 935 #size-cells = <1>; 936 ranges = <0 0x4400c000 0x400>; 937 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; 938 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 939 resets = <&rcc SAI3_R>; 940 status = "disabled"; 941 942 sai3a: audio-controller@4400c004 { 943 #sound-dai-cells = <0>; 944 compatible = "st,stm32-sai-sub-a"; 945 reg = <0x04 0x20>; 946 clocks = <&rcc SAI3_K>; 947 clock-names = "sai_ck"; 948 dmas = <&dmamux1 113 0x400 0x01>; 949 status = "disabled"; 950 }; 951 952 sai3b: audio-controller@4400c024 { 953 #sound-dai-cells = <0>; 954 compatible = "st,stm32-sai-sub-b"; 955 reg = <0x24 0x20>; 956 clocks = <&rcc SAI3_K>; 957 clock-names = "sai_ck"; 958 dmas = <&dmamux1 114 0x400 0x01>; 959 status = "disabled"; 960 }; 961 }; 962 963 dfsdm: dfsdm@4400d000 { 964 compatible = "st,stm32mp1-dfsdm"; 965 reg = <0x4400d000 0x800>; 966 clocks = <&rcc DFSDM_K>; 967 clock-names = "dfsdm"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 972 dfsdm0: filter@0 { 973 compatible = "st,stm32-dfsdm-adc"; 974 #io-channel-cells = <1>; 975 reg = <0>; 976 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 977 dmas = <&dmamux1 101 0x400 0x01>; 978 dma-names = "rx"; 979 status = "disabled"; 980 }; 981 982 dfsdm1: filter@1 { 983 compatible = "st,stm32-dfsdm-adc"; 984 #io-channel-cells = <1>; 985 reg = <1>; 986 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 987 dmas = <&dmamux1 102 0x400 0x01>; 988 dma-names = "rx"; 989 status = "disabled"; 990 }; 991 992 dfsdm2: filter@2 { 993 compatible = "st,stm32-dfsdm-adc"; 994 #io-channel-cells = <1>; 995 reg = <2>; 996 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 997 dmas = <&dmamux1 103 0x400 0x01>; 998 dma-names = "rx"; 999 status = "disabled"; 1000 }; 1001 1002 dfsdm3: filter@3 { 1003 compatible = "st,stm32-dfsdm-adc"; 1004 #io-channel-cells = <1>; 1005 reg = <3>; 1006 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1007 dmas = <&dmamux1 104 0x400 0x01>; 1008 dma-names = "rx"; 1009 status = "disabled"; 1010 }; 1011 1012 dfsdm4: filter@4 { 1013 compatible = "st,stm32-dfsdm-adc"; 1014 #io-channel-cells = <1>; 1015 reg = <4>; 1016 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1017 dmas = <&dmamux1 91 0x400 0x01>; 1018 dma-names = "rx"; 1019 status = "disabled"; 1020 }; 1021 1022 dfsdm5: filter@5 { 1023 compatible = "st,stm32-dfsdm-adc"; 1024 #io-channel-cells = <1>; 1025 reg = <5>; 1026 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1027 dmas = <&dmamux1 92 0x400 0x01>; 1028 dma-names = "rx"; 1029 status = "disabled"; 1030 }; 1031 }; 1032 1033 dma1: dma-controller@48000000 { 1034 compatible = "st,stm32-dma"; 1035 reg = <0x48000000 0x400>; 1036 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&rcc DMA1>; 1045 resets = <&rcc DMA1_R>; 1046 #dma-cells = <4>; 1047 st,mem2mem; 1048 dma-requests = <8>; 1049 }; 1050 1051 dma2: dma-controller@48001000 { 1052 compatible = "st,stm32-dma"; 1053 reg = <0x48001000 0x400>; 1054 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&rcc DMA2>; 1063 resets = <&rcc DMA2_R>; 1064 #dma-cells = <4>; 1065 st,mem2mem; 1066 dma-requests = <8>; 1067 }; 1068 1069 dmamux1: dma-router@48002000 { 1070 compatible = "st,stm32h7-dmamux"; 1071 reg = <0x48002000 0x40>; 1072 #dma-cells = <3>; 1073 dma-requests = <128>; 1074 dma-masters = <&dma1 &dma2>; 1075 dma-channels = <16>; 1076 clocks = <&rcc DMAMUX>; 1077 resets = <&rcc DMAMUX_R>; 1078 }; 1079 1080 adc: adc@48003000 { 1081 compatible = "st,stm32mp1-adc-core"; 1082 reg = <0x48003000 0x400>; 1083 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&rcc ADC12>, <&rcc ADC12_K>; 1086 clock-names = "bus", "adc"; 1087 interrupt-controller; 1088 st,syscfg = <&syscfg>; 1089 #interrupt-cells = <1>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 1094 adc1: adc@0 { 1095 compatible = "st,stm32mp1-adc"; 1096 #io-channel-cells = <1>; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 reg = <0x0>; 1100 interrupt-parent = <&adc>; 1101 interrupts = <0>; 1102 dmas = <&dmamux1 9 0x400 0x01>; 1103 dma-names = "rx"; 1104 status = "disabled"; 1105 }; 1106 1107 adc2: adc@100 { 1108 compatible = "st,stm32mp1-adc"; 1109 #io-channel-cells = <1>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 reg = <0x100>; 1113 interrupt-parent = <&adc>; 1114 interrupts = <1>; 1115 dmas = <&dmamux1 10 0x400 0x01>; 1116 dma-names = "rx"; 1117 nvmem-cells = <&vrefint>; 1118 nvmem-cell-names = "vrefint"; 1119 status = "disabled"; 1120 channel@13 { 1121 reg = <13>; 1122 label = "vrefint"; 1123 }; 1124 channel@14 { 1125 reg = <14>; 1126 label = "vddcore"; 1127 }; 1128 }; 1129 }; 1130 1131 sdmmc3: mmc@48004000 { 1132 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1133 arm,primecell-periphid = <0x00253180>; 1134 reg = <0x48004000 0x400>; 1135 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&rcc SDMMC3_K>; 1137 clock-names = "apb_pclk"; 1138 resets = <&rcc SDMMC3_R>; 1139 cap-sd-highspeed; 1140 cap-mmc-highspeed; 1141 max-frequency = <120000000>; 1142 status = "disabled"; 1143 }; 1144 1145 usbotg_hs: usb-otg@49000000 { 1146 compatible = "st,stm32mp15-hsotg", "snps,dwc2"; 1147 reg = <0x49000000 0x10000>; 1148 clocks = <&rcc USBO_K>, <&usbphyc>; 1149 clock-names = "otg", "utmi"; 1150 resets = <&rcc USBO_R>; 1151 reset-names = "dwc2"; 1152 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1153 g-rx-fifo-size = <512>; 1154 g-np-tx-fifo-size = <32>; 1155 g-tx-fifo-size = <256 16 16 16 16 16 16 16>; 1156 dr_mode = "otg"; 1157 otg-rev = <0x200>; 1158 usb33d-supply = <&usb33>; 1159 status = "disabled"; 1160 }; 1161 1162 ipcc: mailbox@4c001000 { 1163 compatible = "st,stm32mp1-ipcc"; 1164 #mbox-cells = <1>; 1165 reg = <0x4c001000 0x400>; 1166 st,proc-id = <0>; 1167 interrupts-extended = 1168 <&exti 61 1>, 1169 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1170 interrupt-names = "rx", "tx"; 1171 clocks = <&rcc IPCC>; 1172 wakeup-source; 1173 status = "disabled"; 1174 }; 1175 1176 dcmi: dcmi@4c006000 { 1177 compatible = "st,stm32-dcmi"; 1178 reg = <0x4c006000 0x400>; 1179 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1180 resets = <&rcc CAMITF_R>; 1181 clocks = <&rcc DCMI>; 1182 clock-names = "mclk"; 1183 dmas = <&dmamux1 75 0x400 0x01>; 1184 dma-names = "tx"; 1185 status = "disabled"; 1186 }; 1187 1188 rcc: rcc@50000000 { 1189 compatible = "st,stm32mp1-rcc", "syscon"; 1190 reg = <0x50000000 0x1000>; 1191 #clock-cells = <1>; 1192 #reset-cells = <1>; 1193 }; 1194 1195 pwr_regulators: pwr@50001000 { 1196 compatible = "st,stm32mp1,pwr-reg"; 1197 reg = <0x50001000 0x10>; 1198 1199 reg11: reg11 { 1200 regulator-name = "reg11"; 1201 regulator-min-microvolt = <1100000>; 1202 regulator-max-microvolt = <1100000>; 1203 }; 1204 1205 reg18: reg18 { 1206 regulator-name = "reg18"; 1207 regulator-min-microvolt = <1800000>; 1208 regulator-max-microvolt = <1800000>; 1209 }; 1210 1211 usb33: usb33 { 1212 regulator-name = "usb33"; 1213 regulator-min-microvolt = <3300000>; 1214 regulator-max-microvolt = <3300000>; 1215 }; 1216 }; 1217 1218 pwr_mcu: pwr_mcu@50001014 { 1219 compatible = "st,stm32mp151-pwr-mcu", "syscon"; 1220 reg = <0x50001014 0x4>; 1221 }; 1222 1223 exti: interrupt-controller@5000d000 { 1224 compatible = "st,stm32mp1-exti", "syscon"; 1225 interrupt-controller; 1226 #interrupt-cells = <2>; 1227 reg = <0x5000d000 0x400>; 1228 }; 1229 1230 syscfg: syscon@50020000 { 1231 compatible = "st,stm32mp157-syscfg", "syscon"; 1232 reg = <0x50020000 0x400>; 1233 clocks = <&rcc SYSCFG>; 1234 }; 1235 1236 lptimer2: timer@50021000 { 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 compatible = "st,stm32-lptimer"; 1240 reg = <0x50021000 0x400>; 1241 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&rcc LPTIM2_K>; 1243 clock-names = "mux"; 1244 wakeup-source; 1245 status = "disabled"; 1246 1247 pwm { 1248 compatible = "st,stm32-pwm-lp"; 1249 #pwm-cells = <3>; 1250 status = "disabled"; 1251 }; 1252 1253 trigger@1 { 1254 compatible = "st,stm32-lptimer-trigger"; 1255 reg = <1>; 1256 status = "disabled"; 1257 }; 1258 1259 counter { 1260 compatible = "st,stm32-lptimer-counter"; 1261 status = "disabled"; 1262 }; 1263 }; 1264 1265 lptimer3: timer@50022000 { 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 compatible = "st,stm32-lptimer"; 1269 reg = <0x50022000 0x400>; 1270 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; 1271 clocks = <&rcc LPTIM3_K>; 1272 clock-names = "mux"; 1273 wakeup-source; 1274 status = "disabled"; 1275 1276 pwm { 1277 compatible = "st,stm32-pwm-lp"; 1278 #pwm-cells = <3>; 1279 status = "disabled"; 1280 }; 1281 1282 trigger@2 { 1283 compatible = "st,stm32-lptimer-trigger"; 1284 reg = <2>; 1285 status = "disabled"; 1286 }; 1287 }; 1288 1289 lptimer4: timer@50023000 { 1290 compatible = "st,stm32-lptimer"; 1291 reg = <0x50023000 0x400>; 1292 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&rcc LPTIM4_K>; 1294 clock-names = "mux"; 1295 wakeup-source; 1296 status = "disabled"; 1297 1298 pwm { 1299 compatible = "st,stm32-pwm-lp"; 1300 #pwm-cells = <3>; 1301 status = "disabled"; 1302 }; 1303 }; 1304 1305 lptimer5: timer@50024000 { 1306 compatible = "st,stm32-lptimer"; 1307 reg = <0x50024000 0x400>; 1308 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&rcc LPTIM5_K>; 1310 clock-names = "mux"; 1311 wakeup-source; 1312 status = "disabled"; 1313 1314 pwm { 1315 compatible = "st,stm32-pwm-lp"; 1316 #pwm-cells = <3>; 1317 status = "disabled"; 1318 }; 1319 }; 1320 1321 vrefbuf: vrefbuf@50025000 { 1322 compatible = "st,stm32-vrefbuf"; 1323 reg = <0x50025000 0x8>; 1324 regulator-min-microvolt = <1500000>; 1325 regulator-max-microvolt = <2500000>; 1326 clocks = <&rcc VREF>; 1327 status = "disabled"; 1328 }; 1329 1330 sai4: sai@50027000 { 1331 compatible = "st,stm32h7-sai"; 1332 #address-cells = <1>; 1333 #size-cells = <1>; 1334 ranges = <0 0x50027000 0x400>; 1335 reg = <0x50027000 0x4>, <0x500273f0 0x10>; 1336 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1337 resets = <&rcc SAI4_R>; 1338 status = "disabled"; 1339 1340 sai4a: audio-controller@50027004 { 1341 #sound-dai-cells = <0>; 1342 compatible = "st,stm32-sai-sub-a"; 1343 reg = <0x04 0x20>; 1344 clocks = <&rcc SAI4_K>; 1345 clock-names = "sai_ck"; 1346 dmas = <&dmamux1 99 0x400 0x01>; 1347 status = "disabled"; 1348 }; 1349 1350 sai4b: audio-controller@50027024 { 1351 #sound-dai-cells = <0>; 1352 compatible = "st,stm32-sai-sub-b"; 1353 reg = <0x24 0x20>; 1354 clocks = <&rcc SAI4_K>; 1355 clock-names = "sai_ck"; 1356 dmas = <&dmamux1 100 0x400 0x01>; 1357 status = "disabled"; 1358 }; 1359 }; 1360 1361 dts: thermal@50028000 { 1362 compatible = "st,stm32-thermal"; 1363 reg = <0x50028000 0x100>; 1364 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1365 clocks = <&rcc TMPSENS>; 1366 clock-names = "pclk"; 1367 #thermal-sensor-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 hash1: hash@54002000 { 1372 compatible = "st,stm32f756-hash"; 1373 reg = <0x54002000 0x400>; 1374 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&rcc HASH1>; 1376 resets = <&rcc HASH1_R>; 1377 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; 1378 dma-names = "in"; 1379 dma-maxburst = <2>; 1380 status = "disabled"; 1381 }; 1382 1383 rng1: rng@54003000 { 1384 compatible = "st,stm32-rng"; 1385 reg = <0x54003000 0x400>; 1386 clocks = <&rcc RNG1_K>; 1387 resets = <&rcc RNG1_R>; 1388 status = "disabled"; 1389 }; 1390 1391 mdma1: dma-controller@58000000 { 1392 compatible = "st,stm32h7-mdma"; 1393 reg = <0x58000000 0x1000>; 1394 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1395 clocks = <&rcc MDMA>; 1396 resets = <&rcc MDMA_R>; 1397 #dma-cells = <5>; 1398 dma-channels = <32>; 1399 dma-requests = <48>; 1400 }; 1401 1402 fmc: memory-controller@58002000 { 1403 #address-cells = <2>; 1404 #size-cells = <1>; 1405 compatible = "st,stm32mp1-fmc2-ebi"; 1406 reg = <0x58002000 0x1000>; 1407 clocks = <&rcc FMC_K>; 1408 resets = <&rcc FMC_R>; 1409 status = "disabled"; 1410 1411 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 1412 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 1413 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 1414 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 1415 <4 0 0x80000000 0x10000000>; /* NAND */ 1416 1417 nand-controller@4,0 { 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 compatible = "st,stm32mp1-fmc2-nfc"; 1421 reg = <4 0x00000000 0x1000>, 1422 <4 0x08010000 0x1000>, 1423 <4 0x08020000 0x1000>, 1424 <4 0x01000000 0x1000>, 1425 <4 0x09010000 0x1000>, 1426 <4 0x09020000 0x1000>; 1427 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1428 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, 1429 <&mdma1 20 0x2 0x12000a08 0x0 0x0>, 1430 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; 1431 dma-names = "tx", "rx", "ecc"; 1432 status = "disabled"; 1433 }; 1434 }; 1435 1436 qspi: spi@58003000 { 1437 compatible = "st,stm32f469-qspi"; 1438 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 1439 reg-names = "qspi", "qspi_mm"; 1440 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, 1442 <&mdma1 22 0x2 0x10100008 0x0 0x0>; 1443 dma-names = "tx", "rx"; 1444 clocks = <&rcc QSPI_K>; 1445 resets = <&rcc QSPI_R>; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 1451 sdmmc1: mmc@58005000 { 1452 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1453 arm,primecell-periphid = <0x00253180>; 1454 reg = <0x58005000 0x1000>; 1455 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1456 clocks = <&rcc SDMMC1_K>; 1457 clock-names = "apb_pclk"; 1458 resets = <&rcc SDMMC1_R>; 1459 cap-sd-highspeed; 1460 cap-mmc-highspeed; 1461 max-frequency = <120000000>; 1462 status = "disabled"; 1463 }; 1464 1465 sdmmc2: mmc@58007000 { 1466 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 1467 arm,primecell-periphid = <0x00253180>; 1468 reg = <0x58007000 0x1000>; 1469 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&rcc SDMMC2_K>; 1471 clock-names = "apb_pclk"; 1472 resets = <&rcc SDMMC2_R>; 1473 cap-sd-highspeed; 1474 cap-mmc-highspeed; 1475 max-frequency = <120000000>; 1476 status = "disabled"; 1477 }; 1478 1479 crc1: crc@58009000 { 1480 compatible = "st,stm32f7-crc"; 1481 reg = <0x58009000 0x400>; 1482 clocks = <&rcc CRC1>; 1483 status = "disabled"; 1484 }; 1485 1486 ethernet0: ethernet@5800a000 { 1487 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; 1488 reg = <0x5800a000 0x2000>; 1489 reg-names = "stmmaceth"; 1490 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1491 interrupt-names = "macirq"; 1492 clock-names = "stmmaceth", 1493 "mac-clk-tx", 1494 "mac-clk-rx", 1495 "eth-ck", 1496 "ptp_ref", 1497 "ethstp"; 1498 clocks = <&rcc ETHMAC>, 1499 <&rcc ETHTX>, 1500 <&rcc ETHRX>, 1501 <&rcc ETHCK_K>, 1502 <&rcc ETHPTP_K>, 1503 <&rcc ETHSTP>; 1504 st,syscon = <&syscfg 0x4>; 1505 snps,mixed-burst; 1506 snps,pbl = <2>; 1507 snps,en-tx-lpi-clockgating; 1508 snps,axi-config = <&stmmac_axi_config_0>; 1509 snps,tso; 1510 status = "disabled"; 1511 1512 stmmac_axi_config_0: stmmac-axi-config { 1513 snps,wr_osr_lmt = <0x7>; 1514 snps,rd_osr_lmt = <0x7>; 1515 snps,blen = <0 0 0 0 16 8 4>; 1516 }; 1517 }; 1518 1519 usbh_ohci: usb@5800c000 { 1520 compatible = "generic-ohci"; 1521 reg = <0x5800c000 0x1000>; 1522 clocks = <&usbphyc>, <&rcc USBH>; 1523 resets = <&rcc USBH_R>; 1524 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1525 status = "disabled"; 1526 }; 1527 1528 usbh_ehci: usb@5800d000 { 1529 compatible = "generic-ehci"; 1530 reg = <0x5800d000 0x1000>; 1531 clocks = <&usbphyc>, <&rcc USBH>; 1532 resets = <&rcc USBH_R>; 1533 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1534 companion = <&usbh_ohci>; 1535 status = "disabled"; 1536 }; 1537 1538 ltdc: display-controller@5a001000 { 1539 compatible = "st,stm32-ltdc"; 1540 reg = <0x5a001000 0x400>; 1541 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&rcc LTDC_PX>; 1544 clock-names = "lcd"; 1545 resets = <&rcc LTDC_R>; 1546 status = "disabled"; 1547 }; 1548 1549 iwdg2: watchdog@5a002000 { 1550 compatible = "st,stm32mp1-iwdg"; 1551 reg = <0x5a002000 0x400>; 1552 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 1553 clock-names = "pclk", "lsi"; 1554 status = "disabled"; 1555 }; 1556 1557 usbphyc: usbphyc@5a006000 { 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 #clock-cells = <0>; 1561 compatible = "st,stm32mp1-usbphyc"; 1562 reg = <0x5a006000 0x1000>; 1563 clocks = <&rcc USBPHY_K>; 1564 resets = <&rcc USBPHY_R>; 1565 vdda1v1-supply = <®11>; 1566 vdda1v8-supply = <®18>; 1567 status = "disabled"; 1568 1569 usbphyc_port0: usb-phy@0 { 1570 #phy-cells = <0>; 1571 reg = <0>; 1572 }; 1573 1574 usbphyc_port1: usb-phy@1 { 1575 #phy-cells = <1>; 1576 reg = <1>; 1577 }; 1578 }; 1579 1580 usart1: serial@5c000000 { 1581 compatible = "st,stm32h7-uart"; 1582 reg = <0x5c000000 0x400>; 1583 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; 1584 clocks = <&rcc USART1_K>; 1585 wakeup-source; 1586 status = "disabled"; 1587 }; 1588 1589 spi6: spi@5c001000 { 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 compatible = "st,stm32h7-spi"; 1593 reg = <0x5c001000 0x400>; 1594 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&rcc SPI6_K>; 1596 resets = <&rcc SPI6_R>; 1597 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, 1598 <&mdma1 35 0x0 0x40002 0x0 0x0>; 1599 dma-names = "rx", "tx"; 1600 status = "disabled"; 1601 }; 1602 1603 i2c4: i2c@5c002000 { 1604 compatible = "st,stm32mp15-i2c"; 1605 reg = <0x5c002000 0x400>; 1606 interrupt-names = "event", "error"; 1607 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1609 clocks = <&rcc I2C4_K>; 1610 resets = <&rcc I2C4_R>; 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 st,syscfg-fmp = <&syscfg 0x4 0x8>; 1614 wakeup-source; 1615 i2c-analog-filter; 1616 status = "disabled"; 1617 }; 1618 1619 rtc: rtc@5c004000 { 1620 compatible = "st,stm32mp1-rtc"; 1621 reg = <0x5c004000 0x400>; 1622 clocks = <&rcc RTCAPB>, <&rcc RTC>; 1623 clock-names = "pclk", "rtc_ck"; 1624 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 1625 status = "disabled"; 1626 }; 1627 1628 bsec: efuse@5c005000 { 1629 compatible = "st,stm32mp15-bsec"; 1630 reg = <0x5c005000 0x400>; 1631 #address-cells = <1>; 1632 #size-cells = <1>; 1633 part_number_otp: part-number-otp@4 { 1634 reg = <0x4 0x1>; 1635 }; 1636 vrefint: vrefin-cal@52 { 1637 reg = <0x52 0x2>; 1638 }; 1639 ts_cal1: calib@5c { 1640 reg = <0x5c 0x2>; 1641 }; 1642 ts_cal2: calib@5e { 1643 reg = <0x5e 0x2>; 1644 }; 1645 }; 1646 1647 i2c6: i2c@5c009000 { 1648 compatible = "st,stm32mp15-i2c"; 1649 reg = <0x5c009000 0x400>; 1650 interrupt-names = "event", "error"; 1651 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1653 clocks = <&rcc I2C6_K>; 1654 resets = <&rcc I2C6_R>; 1655 #address-cells = <1>; 1656 #size-cells = <0>; 1657 st,syscfg-fmp = <&syscfg 0x4 0x20>; 1658 wakeup-source; 1659 i2c-analog-filter; 1660 status = "disabled"; 1661 }; 1662 1663 tamp: tamp@5c00a000 { 1664 compatible = "st,stm32-tamp", "syscon", "simple-mfd"; 1665 reg = <0x5c00a000 0x400>; 1666 }; 1667 1668 /* 1669 * Break node order to solve dependency probe issue between 1670 * pinctrl and exti. 1671 */ 1672 pinctrl: pinctrl@50002000 { 1673 #address-cells = <1>; 1674 #size-cells = <1>; 1675 compatible = "st,stm32mp157-pinctrl"; 1676 ranges = <0 0x50002000 0xa400>; 1677 interrupt-parent = <&exti>; 1678 st,syscfg = <&exti 0x60 0xff>; 1679 1680 gpioa: gpio@50002000 { 1681 gpio-controller; 1682 #gpio-cells = <2>; 1683 interrupt-controller; 1684 #interrupt-cells = <2>; 1685 reg = <0x0 0x400>; 1686 clocks = <&rcc GPIOA>; 1687 st,bank-name = "GPIOA"; 1688 status = "disabled"; 1689 }; 1690 1691 gpiob: gpio@50003000 { 1692 gpio-controller; 1693 #gpio-cells = <2>; 1694 interrupt-controller; 1695 #interrupt-cells = <2>; 1696 reg = <0x1000 0x400>; 1697 clocks = <&rcc GPIOB>; 1698 st,bank-name = "GPIOB"; 1699 status = "disabled"; 1700 }; 1701 1702 gpioc: gpio@50004000 { 1703 gpio-controller; 1704 #gpio-cells = <2>; 1705 interrupt-controller; 1706 #interrupt-cells = <2>; 1707 reg = <0x2000 0x400>; 1708 clocks = <&rcc GPIOC>; 1709 st,bank-name = "GPIOC"; 1710 status = "disabled"; 1711 }; 1712 1713 gpiod: gpio@50005000 { 1714 gpio-controller; 1715 #gpio-cells = <2>; 1716 interrupt-controller; 1717 #interrupt-cells = <2>; 1718 reg = <0x3000 0x400>; 1719 clocks = <&rcc GPIOD>; 1720 st,bank-name = "GPIOD"; 1721 status = "disabled"; 1722 }; 1723 1724 gpioe: gpio@50006000 { 1725 gpio-controller; 1726 #gpio-cells = <2>; 1727 interrupt-controller; 1728 #interrupt-cells = <2>; 1729 reg = <0x4000 0x400>; 1730 clocks = <&rcc GPIOE>; 1731 st,bank-name = "GPIOE"; 1732 status = "disabled"; 1733 }; 1734 1735 gpiof: gpio@50007000 { 1736 gpio-controller; 1737 #gpio-cells = <2>; 1738 interrupt-controller; 1739 #interrupt-cells = <2>; 1740 reg = <0x5000 0x400>; 1741 clocks = <&rcc GPIOF>; 1742 st,bank-name = "GPIOF"; 1743 status = "disabled"; 1744 }; 1745 1746 gpiog: gpio@50008000 { 1747 gpio-controller; 1748 #gpio-cells = <2>; 1749 interrupt-controller; 1750 #interrupt-cells = <2>; 1751 reg = <0x6000 0x400>; 1752 clocks = <&rcc GPIOG>; 1753 st,bank-name = "GPIOG"; 1754 status = "disabled"; 1755 }; 1756 1757 gpioh: gpio@50009000 { 1758 gpio-controller; 1759 #gpio-cells = <2>; 1760 interrupt-controller; 1761 #interrupt-cells = <2>; 1762 reg = <0x7000 0x400>; 1763 clocks = <&rcc GPIOH>; 1764 st,bank-name = "GPIOH"; 1765 status = "disabled"; 1766 }; 1767 1768 gpioi: gpio@5000a000 { 1769 gpio-controller; 1770 #gpio-cells = <2>; 1771 interrupt-controller; 1772 #interrupt-cells = <2>; 1773 reg = <0x8000 0x400>; 1774 clocks = <&rcc GPIOI>; 1775 st,bank-name = "GPIOI"; 1776 status = "disabled"; 1777 }; 1778 1779 gpioj: gpio@5000b000 { 1780 gpio-controller; 1781 #gpio-cells = <2>; 1782 interrupt-controller; 1783 #interrupt-cells = <2>; 1784 reg = <0x9000 0x400>; 1785 clocks = <&rcc GPIOJ>; 1786 st,bank-name = "GPIOJ"; 1787 status = "disabled"; 1788 }; 1789 1790 gpiok: gpio@5000c000 { 1791 gpio-controller; 1792 #gpio-cells = <2>; 1793 interrupt-controller; 1794 #interrupt-cells = <2>; 1795 reg = <0xa000 0x400>; 1796 clocks = <&rcc GPIOK>; 1797 st,bank-name = "GPIOK"; 1798 status = "disabled"; 1799 }; 1800 }; 1801 1802 pinctrl_z: pinctrl@54004000 { 1803 #address-cells = <1>; 1804 #size-cells = <1>; 1805 compatible = "st,stm32mp157-z-pinctrl"; 1806 ranges = <0 0x54004000 0x400>; 1807 interrupt-parent = <&exti>; 1808 st,syscfg = <&exti 0x60 0xff>; 1809 1810 gpioz: gpio@54004000 { 1811 gpio-controller; 1812 #gpio-cells = <2>; 1813 interrupt-controller; 1814 #interrupt-cells = <2>; 1815 reg = <0 0x400>; 1816 clocks = <&rcc GPIOZ>; 1817 st,bank-name = "GPIOZ"; 1818 st,bank-ioport = <11>; 1819 status = "disabled"; 1820 }; 1821 }; 1822 }; 1823 1824 mlahb: ahb { 1825 compatible = "st,mlahb", "simple-bus"; 1826 #address-cells = <1>; 1827 #size-cells = <1>; 1828 ranges; 1829 dma-ranges = <0x00000000 0x38000000 0x10000>, 1830 <0x10000000 0x10000000 0x60000>, 1831 <0x30000000 0x30000000 0x60000>; 1832 1833 m4_rproc: m4@10000000 { 1834 compatible = "st,stm32mp1-m4"; 1835 reg = <0x10000000 0x40000>, 1836 <0x30000000 0x40000>, 1837 <0x38000000 0x10000>; 1838 resets = <&rcc MCU_R>; 1839 reset-names = "mcu_rst"; 1840 st,syscfg-holdboot = <&rcc 0x10C 0x1>; 1841 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; 1842 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; 1843 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; 1844 status = "disabled"; 1845 }; 1846 }; 1847}; 1848