1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rv1126-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1126"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@f00 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a7"; 33 reg = <0xf00>; 34 enable-method = "psci"; 35 clocks = <&cru ARMCLK>; 36 }; 37 38 cpu1: cpu@f01 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0xf01>; 42 enable-method = "psci"; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu2: cpu@f02 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf02>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 }; 53 54 cpu3: cpu@f03 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0xf03>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a7-pmu"; 65 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 psci { 73 compatible = "arm,psci-1.0"; 74 method = "smc"; 75 }; 76 77 timer { 78 compatible = "arm,armv7-timer"; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 83 clock-frequency = <24000000>; 84 }; 85 86 xin24m: oscillator { 87 compatible = "fixed-clock"; 88 clock-frequency = <24000000>; 89 clock-output-names = "xin24m"; 90 #clock-cells = <0>; 91 }; 92 93 grf: syscon@fe000000 { 94 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 95 reg = <0xfe000000 0x20000>; 96 }; 97 98 pmugrf: syscon@fe020000 { 99 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 100 reg = <0xfe020000 0x1000>; 101 102 pmu_io_domains: io-domains { 103 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 104 status = "disabled"; 105 }; 106 }; 107 108 qos_emmc: qos@fe860000 { 109 compatible = "rockchip,rv1126-qos", "syscon"; 110 reg = <0xfe860000 0x20>; 111 }; 112 113 qos_nandc: qos@fe860080 { 114 compatible = "rockchip,rv1126-qos", "syscon"; 115 reg = <0xfe860080 0x20>; 116 }; 117 118 qos_sfc: qos@fe860200 { 119 compatible = "rockchip,rv1126-qos", "syscon"; 120 reg = <0xfe860200 0x20>; 121 }; 122 123 qos_sdio: qos@fe86c000 { 124 compatible = "rockchip,rv1126-qos", "syscon"; 125 reg = <0xfe86c000 0x20>; 126 }; 127 128 gic: interrupt-controller@feff0000 { 129 compatible = "arm,gic-400"; 130 interrupt-controller; 131 #interrupt-cells = <3>; 132 #address-cells = <0>; 133 134 reg = <0xfeff1000 0x1000>, 135 <0xfeff2000 0x2000>, 136 <0xfeff4000 0x2000>, 137 <0xfeff6000 0x2000>; 138 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 }; 140 141 pmu: power-management@ff3e0000 { 142 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 143 reg = <0xff3e0000 0x1000>; 144 145 power: power-controller { 146 compatible = "rockchip,rv1126-power-controller"; 147 #power-domain-cells = <1>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 power-domain@RV1126_PD_NVM { 152 reg = <RV1126_PD_NVM>; 153 clocks = <&cru HCLK_EMMC>, 154 <&cru CLK_EMMC>, 155 <&cru HCLK_NANDC>, 156 <&cru CLK_NANDC>, 157 <&cru HCLK_SFC>, 158 <&cru HCLK_SFCXIP>, 159 <&cru SCLK_SFC>; 160 pm_qos = <&qos_emmc>, 161 <&qos_nandc>, 162 <&qos_sfc>; 163 #power-domain-cells = <0>; 164 }; 165 166 power-domain@RV1126_PD_SDIO { 167 reg = <RV1126_PD_SDIO>; 168 clocks = <&cru HCLK_SDIO>, 169 <&cru CLK_SDIO>; 170 pm_qos = <&qos_sdio>; 171 #power-domain-cells = <0>; 172 }; 173 }; 174 }; 175 176 i2c0: i2c@ff3f0000 { 177 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 178 reg = <0xff3f0000 0x1000>; 179 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 180 rockchip,grf = <&pmugrf>; 181 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 182 clock-names = "i2c", "pclk"; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&i2c0_xfer>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 status = "disabled"; 188 }; 189 190 uart1: serial@ff410000 { 191 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 192 reg = <0xff410000 0x100>; 193 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 194 clock-frequency = <24000000>; 195 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 196 clock-names = "baudclk", "apb_pclk"; 197 dmas = <&dmac 7>, <&dmac 6>; 198 dma-names = "tx", "rx"; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&uart1m0_xfer>; 201 reg-shift = <2>; 202 reg-io-width = <4>; 203 status = "disabled"; 204 }; 205 206 pmucru: clock-controller@ff480000 { 207 compatible = "rockchip,rv1126-pmucru"; 208 reg = <0xff480000 0x1000>; 209 rockchip,grf = <&grf>; 210 #clock-cells = <1>; 211 #reset-cells = <1>; 212 }; 213 214 cru: clock-controller@ff490000 { 215 compatible = "rockchip,rv1126-cru"; 216 reg = <0xff490000 0x1000>; 217 clocks = <&xin24m>; 218 clock-names = "xin24m"; 219 rockchip,grf = <&grf>; 220 #clock-cells = <1>; 221 #reset-cells = <1>; 222 }; 223 224 dmac: dma-controller@ff4e0000 { 225 compatible = "arm,pl330", "arm,primecell"; 226 reg = <0xff4e0000 0x4000>; 227 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 229 #dma-cells = <1>; 230 arm,pl330-periph-burst; 231 clocks = <&cru ACLK_DMAC>; 232 clock-names = "apb_pclk"; 233 }; 234 235 uart0: serial@ff560000 { 236 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 237 reg = <0xff560000 0x100>; 238 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 239 clock-frequency = <24000000>; 240 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 241 clock-names = "baudclk", "apb_pclk"; 242 dmas = <&dmac 5>, <&dmac 4>; 243 dma-names = "tx", "rx"; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&uart0_xfer>; 246 reg-shift = <2>; 247 reg-io-width = <4>; 248 status = "disabled"; 249 }; 250 251 uart2: serial@ff570000 { 252 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 253 reg = <0xff570000 0x100>; 254 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 255 clock-frequency = <24000000>; 256 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 257 clock-names = "baudclk", "apb_pclk"; 258 dmas = <&dmac 9>, <&dmac 8>; 259 dma-names = "tx", "rx"; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&uart2m1_xfer>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 status = "disabled"; 265 }; 266 267 uart3: serial@ff580000 { 268 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 269 reg = <0xff580000 0x100>; 270 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 271 clock-frequency = <24000000>; 272 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 273 clock-names = "baudclk", "apb_pclk"; 274 dmas = <&dmac 11>, <&dmac 10>; 275 dma-names = "tx", "rx"; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&uart3m0_xfer>; 278 reg-shift = <2>; 279 reg-io-width = <4>; 280 status = "disabled"; 281 }; 282 283 uart4: serial@ff590000 { 284 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 285 reg = <0xff590000 0x100>; 286 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 287 clock-frequency = <24000000>; 288 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 289 clock-names = "baudclk", "apb_pclk"; 290 dmas = <&dmac 13>, <&dmac 12>; 291 dma-names = "tx", "rx"; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&uart4m0_xfer>; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 status = "disabled"; 297 }; 298 299 uart5: serial@ff5a0000 { 300 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 301 reg = <0xff5a0000 0x100>; 302 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 303 clock-frequency = <24000000>; 304 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 305 clock-names = "baudclk", "apb_pclk"; 306 dmas = <&dmac 15>, <&dmac 14>; 307 dma-names = "tx", "rx"; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&uart5m0_xfer>; 310 reg-shift = <2>; 311 reg-io-width = <4>; 312 status = "disabled"; 313 }; 314 315 saradc: adc@ff5e0000 { 316 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; 317 reg = <0xff5e0000 0x100>; 318 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 319 #io-channel-cells = <1>; 320 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 321 clock-names = "saradc", "apb_pclk"; 322 resets = <&cru SRST_SARADC_P>; 323 reset-names = "saradc-apb"; 324 status = "disabled"; 325 }; 326 327 timer0: timer@ff660000 { 328 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; 329 reg = <0xff660000 0x20>; 330 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 332 clock-names = "pclk", "timer"; 333 }; 334 335 gmac: ethernet@ffc40000 { 336 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 337 reg = <0xffc40000 0x4000>; 338 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "macirq", "eth_wake_irq"; 341 rockchip,grf = <&grf>; 342 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 343 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 344 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 345 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 346 clock-names = "stmmaceth", "mac_clk_rx", 347 "mac_clk_tx", "clk_mac_ref", 348 "aclk_mac", "pclk_mac", 349 "clk_mac_speed", "ptp_ref"; 350 resets = <&cru SRST_GMAC_A>; 351 reset-names = "stmmaceth"; 352 353 snps,mixed-burst; 354 snps,tso; 355 356 snps,axi-config = <&stmmac_axi_setup>; 357 snps,mtl-rx-config = <&mtl_rx_setup>; 358 snps,mtl-tx-config = <&mtl_tx_setup>; 359 status = "disabled"; 360 361 mdio: mdio { 362 compatible = "snps,dwmac-mdio"; 363 #address-cells = <0x1>; 364 #size-cells = <0x0>; 365 }; 366 367 stmmac_axi_setup: stmmac-axi-config { 368 snps,wr_osr_lmt = <4>; 369 snps,rd_osr_lmt = <8>; 370 snps,blen = <0 0 0 0 16 8 4>; 371 }; 372 373 mtl_rx_setup: rx-queues-config { 374 snps,rx-queues-to-use = <1>; 375 queue0 {}; 376 }; 377 378 mtl_tx_setup: tx-queues-config { 379 snps,tx-queues-to-use = <1>; 380 queue0 {}; 381 }; 382 }; 383 384 emmc: mmc@ffc50000 { 385 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 386 reg = <0xffc50000 0x4000>; 387 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 389 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 390 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 391 fifo-depth = <0x100>; 392 max-frequency = <200000000>; 393 power-domains = <&power RV1126_PD_NVM>; 394 status = "disabled"; 395 }; 396 397 sdmmc: mmc@ffc60000 { 398 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 399 reg = <0xffc60000 0x4000>; 400 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 402 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 403 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 404 fifo-depth = <0x100>; 405 max-frequency = <200000000>; 406 status = "disabled"; 407 }; 408 409 sdio: mmc@ffc70000 { 410 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 411 reg = <0xffc70000 0x4000>; 412 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 414 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 415 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 416 fifo-depth = <0x100>; 417 max-frequency = <200000000>; 418 power-domains = <&power RV1126_PD_SDIO>; 419 status = "disabled"; 420 }; 421 422 sfc: spi@ffc90000 { 423 compatible = "rockchip,sfc"; 424 reg = <0xffc90000 0x4000>; 425 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 426 assigned-clocks = <&cru SCLK_SFC>; 427 assigned-clock-rates = <80000000>; 428 clock-names = "clk_sfc", "hclk_sfc"; 429 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 430 power-domains = <&power RV1126_PD_NVM>; 431 status = "disabled"; 432 }; 433 434 pinctrl: pinctrl { 435 compatible = "rockchip,rv1126-pinctrl"; 436 rockchip,grf = <&grf>; 437 rockchip,pmu = <&pmugrf>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 ranges; 441 442 gpio0: gpio@ff460000 { 443 compatible = "rockchip,gpio-bank"; 444 reg = <0xff460000 0x100>; 445 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 }; 452 453 gpio1: gpio@ff620000 { 454 compatible = "rockchip,gpio-bank"; 455 reg = <0xff620000 0x100>; 456 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 }; 463 464 gpio2: gpio@ff630000 { 465 compatible = "rockchip,gpio-bank"; 466 reg = <0xff630000 0x100>; 467 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 }; 474 475 gpio3: gpio@ff640000 { 476 compatible = "rockchip,gpio-bank"; 477 reg = <0xff640000 0x100>; 478 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 }; 485 486 gpio4: gpio@ff650000 { 487 compatible = "rockchip,gpio-bank"; 488 reg = <0xff650000 0x100>; 489 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 }; 496 }; 497}; 498 499#include "rv1126-pinctrl.dtsi" 500