1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rv1126-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1126"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@f00 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a7"; 33 reg = <0xf00>; 34 enable-method = "psci"; 35 clocks = <&cru ARMCLK>; 36 }; 37 38 cpu1: cpu@f01 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0xf01>; 42 enable-method = "psci"; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu2: cpu@f02 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf02>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 }; 53 54 cpu3: cpu@f03 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0xf03>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a7-pmu"; 65 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 psci { 73 compatible = "arm,psci-1.0"; 74 method = "smc"; 75 }; 76 77 timer { 78 compatible = "arm,armv7-timer"; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 83 clock-frequency = <24000000>; 84 }; 85 86 display_subsystem { 87 compatible = "rockchip,display-subsystem"; 88 ports = <&vop_out>; 89 }; 90 91 xin24m: oscillator { 92 compatible = "fixed-clock"; 93 clock-frequency = <24000000>; 94 clock-output-names = "xin24m"; 95 #clock-cells = <0>; 96 }; 97 98 grf: syscon@fe000000 { 99 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 100 reg = <0xfe000000 0x20000>; 101 }; 102 103 pmugrf: syscon@fe020000 { 104 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 105 reg = <0xfe020000 0x1000>; 106 107 pmu_io_domains: io-domains { 108 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 109 status = "disabled"; 110 }; 111 }; 112 113 qos_emmc: qos@fe860000 { 114 compatible = "rockchip,rv1126-qos", "syscon"; 115 reg = <0xfe860000 0x20>; 116 }; 117 118 qos_nandc: qos@fe860080 { 119 compatible = "rockchip,rv1126-qos", "syscon"; 120 reg = <0xfe860080 0x20>; 121 }; 122 123 qos_sfc: qos@fe860200 { 124 compatible = "rockchip,rv1126-qos", "syscon"; 125 reg = <0xfe860200 0x20>; 126 }; 127 128 qos_sdio: qos@fe86c000 { 129 compatible = "rockchip,rv1126-qos", "syscon"; 130 reg = <0xfe86c000 0x20>; 131 }; 132 133 qos_iep: qos@fe8a0000 { 134 compatible = "rockchip,rv1126-qos", "syscon"; 135 reg = <0xfe8a0000 0x20>; 136 }; 137 138 qos_rga_rd: qos@fe8a0080 { 139 compatible = "rockchip,rv1126-qos", "syscon"; 140 reg = <0xfe8a0080 0x20>; 141 }; 142 143 qos_rga_wr: qos@fe8a0100 { 144 compatible = "rockchip,rv1126-qos", "syscon"; 145 reg = <0xfe8a0100 0x20>; 146 }; 147 148 qos_vop: qos@fe8a0180 { 149 compatible = "rockchip,rv1126-qos", "syscon"; 150 reg = <0xfe8a0180 0x20>; 151 }; 152 153 gic: interrupt-controller@feff0000 { 154 compatible = "arm,gic-400"; 155 interrupt-controller; 156 #interrupt-cells = <3>; 157 #address-cells = <0>; 158 159 reg = <0xfeff1000 0x1000>, 160 <0xfeff2000 0x2000>, 161 <0xfeff4000 0x2000>, 162 <0xfeff6000 0x2000>; 163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 164 }; 165 166 pmu: power-management@ff3e0000 { 167 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 168 reg = <0xff3e0000 0x1000>; 169 170 power: power-controller { 171 compatible = "rockchip,rv1126-power-controller"; 172 #power-domain-cells = <1>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 power-domain@RV1126_PD_NVM { 177 reg = <RV1126_PD_NVM>; 178 clocks = <&cru HCLK_EMMC>, 179 <&cru CLK_EMMC>, 180 <&cru HCLK_NANDC>, 181 <&cru CLK_NANDC>, 182 <&cru HCLK_SFC>, 183 <&cru HCLK_SFCXIP>, 184 <&cru SCLK_SFC>; 185 pm_qos = <&qos_emmc>, 186 <&qos_nandc>, 187 <&qos_sfc>; 188 #power-domain-cells = <0>; 189 }; 190 191 power-domain@RV1126_PD_SDIO { 192 reg = <RV1126_PD_SDIO>; 193 clocks = <&cru HCLK_SDIO>, 194 <&cru CLK_SDIO>; 195 pm_qos = <&qos_sdio>; 196 #power-domain-cells = <0>; 197 }; 198 199 power-domain@RV1126_PD_VO { 200 reg = <RV1126_PD_VO>; 201 clocks = <&cru ACLK_RGA>, 202 <&cru HCLK_RGA>, 203 <&cru CLK_RGA_CORE>, 204 <&cru ACLK_VOP>, 205 <&cru HCLK_VOP>, 206 <&cru DCLK_VOP>, 207 <&cru PCLK_DSIHOST>, 208 <&cru ACLK_IEP>, 209 <&cru HCLK_IEP>, 210 <&cru CLK_IEP_CORE>; 211 pm_qos = <&qos_rga_rd>, 212 <&qos_rga_wr>, 213 <&qos_vop>, 214 <&qos_iep>; 215 #power-domain-cells = <0>; 216 }; 217 }; 218 }; 219 220 i2c0: i2c@ff3f0000 { 221 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 222 reg = <0xff3f0000 0x1000>; 223 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 224 rockchip,grf = <&pmugrf>; 225 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 226 clock-names = "i2c", "pclk"; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&i2c0_xfer>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 uart1: serial@ff410000 { 235 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 236 reg = <0xff410000 0x100>; 237 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 238 clock-frequency = <24000000>; 239 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 240 clock-names = "baudclk", "apb_pclk"; 241 dmas = <&dmac 7>, <&dmac 6>; 242 dma-names = "tx", "rx"; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart1m0_xfer>; 245 reg-shift = <2>; 246 reg-io-width = <4>; 247 status = "disabled"; 248 }; 249 250 pmucru: clock-controller@ff480000 { 251 compatible = "rockchip,rv1126-pmucru"; 252 reg = <0xff480000 0x1000>; 253 rockchip,grf = <&grf>; 254 #clock-cells = <1>; 255 #reset-cells = <1>; 256 }; 257 258 cru: clock-controller@ff490000 { 259 compatible = "rockchip,rv1126-cru"; 260 reg = <0xff490000 0x1000>; 261 clocks = <&xin24m>; 262 clock-names = "xin24m"; 263 rockchip,grf = <&grf>; 264 #clock-cells = <1>; 265 #reset-cells = <1>; 266 }; 267 268 dmac: dma-controller@ff4e0000 { 269 compatible = "arm,pl330", "arm,primecell"; 270 reg = <0xff4e0000 0x4000>; 271 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 273 #dma-cells = <1>; 274 arm,pl330-periph-burst; 275 clocks = <&cru ACLK_DMAC>; 276 clock-names = "apb_pclk"; 277 }; 278 279 uart0: serial@ff560000 { 280 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 281 reg = <0xff560000 0x100>; 282 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 283 clock-frequency = <24000000>; 284 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 285 clock-names = "baudclk", "apb_pclk"; 286 dmas = <&dmac 5>, <&dmac 4>; 287 dma-names = "tx", "rx"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&uart0_xfer>; 290 reg-shift = <2>; 291 reg-io-width = <4>; 292 status = "disabled"; 293 }; 294 295 uart2: serial@ff570000 { 296 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 297 reg = <0xff570000 0x100>; 298 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 299 clock-frequency = <24000000>; 300 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 301 clock-names = "baudclk", "apb_pclk"; 302 dmas = <&dmac 9>, <&dmac 8>; 303 dma-names = "tx", "rx"; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&uart2m1_xfer>; 306 reg-shift = <2>; 307 reg-io-width = <4>; 308 status = "disabled"; 309 }; 310 311 uart3: serial@ff580000 { 312 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 313 reg = <0xff580000 0x100>; 314 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 315 clock-frequency = <24000000>; 316 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 317 clock-names = "baudclk", "apb_pclk"; 318 dmas = <&dmac 11>, <&dmac 10>; 319 dma-names = "tx", "rx"; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&uart3m0_xfer>; 322 reg-shift = <2>; 323 reg-io-width = <4>; 324 status = "disabled"; 325 }; 326 327 uart4: serial@ff590000 { 328 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 329 reg = <0xff590000 0x100>; 330 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 331 clock-frequency = <24000000>; 332 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 333 clock-names = "baudclk", "apb_pclk"; 334 dmas = <&dmac 13>, <&dmac 12>; 335 dma-names = "tx", "rx"; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&uart4m0_xfer>; 338 reg-shift = <2>; 339 reg-io-width = <4>; 340 status = "disabled"; 341 }; 342 343 uart5: serial@ff5a0000 { 344 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 345 reg = <0xff5a0000 0x100>; 346 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 347 clock-frequency = <24000000>; 348 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 349 clock-names = "baudclk", "apb_pclk"; 350 dmas = <&dmac 15>, <&dmac 14>; 351 dma-names = "tx", "rx"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&uart5m0_xfer>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 status = "disabled"; 357 }; 358 359 saradc: adc@ff5e0000 { 360 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; 361 reg = <0xff5e0000 0x100>; 362 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 363 #io-channel-cells = <1>; 364 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 365 clock-names = "saradc", "apb_pclk"; 366 resets = <&cru SRST_SARADC_P>; 367 reset-names = "saradc-apb"; 368 status = "disabled"; 369 }; 370 371 timer0: timer@ff660000 { 372 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; 373 reg = <0xff660000 0x20>; 374 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 376 clock-names = "pclk", "timer"; 377 }; 378 379 vop: vop@ffb00000 { 380 compatible = "rockchip,rv1126-vop"; 381 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 382 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 383 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 384 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 385 reset-names = "axi", "ahb", "dclk"; 386 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 387 iommus = <&vop_mmu>; 388 power-domains = <&power RV1126_PD_VO>; 389 status = "disabled"; 390 391 vop_out: port { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 395 vop_out_rgb: endpoint@0 { 396 reg = <0>; 397 }; 398 399 vop_out_dsi: endpoint@1 { 400 reg = <1>; 401 }; 402 }; 403 }; 404 405 vop_mmu: iommu@ffb00f00 { 406 compatible = "rockchip,iommu"; 407 reg = <0xffb00f00 0x100>; 408 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 409 clock-names = "aclk", "iface"; 410 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 411 #iommu-cells = <0>; 412 power-domains = <&power RV1126_PD_VO>; 413 status = "disabled"; 414 }; 415 416 gmac: ethernet@ffc40000 { 417 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 418 reg = <0xffc40000 0x4000>; 419 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "macirq", "eth_wake_irq"; 422 rockchip,grf = <&grf>; 423 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 424 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 425 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 426 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 427 clock-names = "stmmaceth", "mac_clk_rx", 428 "mac_clk_tx", "clk_mac_ref", 429 "aclk_mac", "pclk_mac", 430 "clk_mac_speed", "ptp_ref"; 431 resets = <&cru SRST_GMAC_A>; 432 reset-names = "stmmaceth"; 433 434 snps,mixed-burst; 435 snps,tso; 436 437 snps,axi-config = <&stmmac_axi_setup>; 438 snps,mtl-rx-config = <&mtl_rx_setup>; 439 snps,mtl-tx-config = <&mtl_tx_setup>; 440 status = "disabled"; 441 442 mdio: mdio { 443 compatible = "snps,dwmac-mdio"; 444 #address-cells = <0x1>; 445 #size-cells = <0x0>; 446 }; 447 448 stmmac_axi_setup: stmmac-axi-config { 449 snps,wr_osr_lmt = <4>; 450 snps,rd_osr_lmt = <8>; 451 snps,blen = <0 0 0 0 16 8 4>; 452 }; 453 454 mtl_rx_setup: rx-queues-config { 455 snps,rx-queues-to-use = <1>; 456 queue0 {}; 457 }; 458 459 mtl_tx_setup: tx-queues-config { 460 snps,tx-queues-to-use = <1>; 461 queue0 {}; 462 }; 463 }; 464 465 emmc: mmc@ffc50000 { 466 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 467 reg = <0xffc50000 0x4000>; 468 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 470 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 471 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 472 fifo-depth = <0x100>; 473 max-frequency = <200000000>; 474 power-domains = <&power RV1126_PD_NVM>; 475 status = "disabled"; 476 }; 477 478 sdmmc: mmc@ffc60000 { 479 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 480 reg = <0xffc60000 0x4000>; 481 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 483 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 484 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 485 fifo-depth = <0x100>; 486 max-frequency = <200000000>; 487 status = "disabled"; 488 }; 489 490 sdio: mmc@ffc70000 { 491 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 492 reg = <0xffc70000 0x4000>; 493 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 495 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 496 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 497 fifo-depth = <0x100>; 498 max-frequency = <200000000>; 499 power-domains = <&power RV1126_PD_SDIO>; 500 status = "disabled"; 501 }; 502 503 sfc: spi@ffc90000 { 504 compatible = "rockchip,sfc"; 505 reg = <0xffc90000 0x4000>; 506 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 507 assigned-clocks = <&cru SCLK_SFC>; 508 assigned-clock-rates = <80000000>; 509 clock-names = "clk_sfc", "hclk_sfc"; 510 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 511 power-domains = <&power RV1126_PD_NVM>; 512 status = "disabled"; 513 }; 514 515 pinctrl: pinctrl { 516 compatible = "rockchip,rv1126-pinctrl"; 517 rockchip,grf = <&grf>; 518 rockchip,pmu = <&pmugrf>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 ranges; 522 523 gpio0: gpio@ff460000 { 524 compatible = "rockchip,gpio-bank"; 525 reg = <0xff460000 0x100>; 526 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 }; 533 534 gpio1: gpio@ff620000 { 535 compatible = "rockchip,gpio-bank"; 536 reg = <0xff620000 0x100>; 537 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 539 gpio-controller; 540 #gpio-cells = <2>; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 }; 544 545 gpio2: gpio@ff630000 { 546 compatible = "rockchip,gpio-bank"; 547 reg = <0xff630000 0x100>; 548 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 550 gpio-controller; 551 #gpio-cells = <2>; 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 556 gpio3: gpio@ff640000 { 557 compatible = "rockchip,gpio-bank"; 558 reg = <0xff640000 0x100>; 559 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 561 gpio-controller; 562 #gpio-cells = <2>; 563 interrupt-controller; 564 #interrupt-cells = <2>; 565 }; 566 567 gpio4: gpio@ff650000 { 568 compatible = "rockchip,gpio-bank"; 569 reg = <0xff650000 0x100>; 570 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 }; 578}; 579 580#include "rv1126-pinctrl.dtsi" 581