1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rv1126-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1126"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu0: cpu@f00 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a7"; 33 reg = <0xf00>; 34 enable-method = "psci"; 35 clocks = <&cru ARMCLK>; 36 }; 37 38 cpu1: cpu@f01 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0xf01>; 42 enable-method = "psci"; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu2: cpu@f02 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf02>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 }; 53 54 cpu3: cpu@f03 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0xf03>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 }; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a7-pmu"; 65 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 psci { 73 compatible = "arm,psci-1.0"; 74 method = "smc"; 75 }; 76 77 timer { 78 compatible = "arm,armv7-timer"; 79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 80 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 81 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 83 clock-frequency = <24000000>; 84 }; 85 86 xin24m: oscillator { 87 compatible = "fixed-clock"; 88 clock-frequency = <24000000>; 89 clock-output-names = "xin24m"; 90 #clock-cells = <0>; 91 }; 92 93 grf: syscon@fe000000 { 94 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 95 reg = <0xfe000000 0x20000>; 96 }; 97 98 pmugrf: syscon@fe020000 { 99 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 100 reg = <0xfe020000 0x1000>; 101 102 pmu_io_domains: io-domains { 103 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 104 status = "disabled"; 105 }; 106 }; 107 108 qos_emmc: qos@fe860000 { 109 compatible = "rockchip,rv1126-qos", "syscon"; 110 reg = <0xfe860000 0x20>; 111 }; 112 113 qos_nandc: qos@fe860080 { 114 compatible = "rockchip,rv1126-qos", "syscon"; 115 reg = <0xfe860080 0x20>; 116 }; 117 118 qos_sfc: qos@fe860200 { 119 compatible = "rockchip,rv1126-qos", "syscon"; 120 reg = <0xfe860200 0x20>; 121 }; 122 123 qos_sdio: qos@fe86c000 { 124 compatible = "rockchip,rv1126-qos", "syscon"; 125 reg = <0xfe86c000 0x20>; 126 }; 127 128 qos_iep: qos@fe8a0000 { 129 compatible = "rockchip,rv1126-qos", "syscon"; 130 reg = <0xfe8a0000 0x20>; 131 }; 132 133 qos_rga_rd: qos@fe8a0080 { 134 compatible = "rockchip,rv1126-qos", "syscon"; 135 reg = <0xfe8a0080 0x20>; 136 }; 137 138 qos_rga_wr: qos@fe8a0100 { 139 compatible = "rockchip,rv1126-qos", "syscon"; 140 reg = <0xfe8a0100 0x20>; 141 }; 142 143 qos_vop: qos@fe8a0180 { 144 compatible = "rockchip,rv1126-qos", "syscon"; 145 reg = <0xfe8a0180 0x20>; 146 }; 147 148 gic: interrupt-controller@feff0000 { 149 compatible = "arm,gic-400"; 150 interrupt-controller; 151 #interrupt-cells = <3>; 152 #address-cells = <0>; 153 154 reg = <0xfeff1000 0x1000>, 155 <0xfeff2000 0x2000>, 156 <0xfeff4000 0x2000>, 157 <0xfeff6000 0x2000>; 158 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 159 }; 160 161 pmu: power-management@ff3e0000 { 162 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 163 reg = <0xff3e0000 0x1000>; 164 165 power: power-controller { 166 compatible = "rockchip,rv1126-power-controller"; 167 #power-domain-cells = <1>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 power-domain@RV1126_PD_NVM { 172 reg = <RV1126_PD_NVM>; 173 clocks = <&cru HCLK_EMMC>, 174 <&cru CLK_EMMC>, 175 <&cru HCLK_NANDC>, 176 <&cru CLK_NANDC>, 177 <&cru HCLK_SFC>, 178 <&cru HCLK_SFCXIP>, 179 <&cru SCLK_SFC>; 180 pm_qos = <&qos_emmc>, 181 <&qos_nandc>, 182 <&qos_sfc>; 183 #power-domain-cells = <0>; 184 }; 185 186 power-domain@RV1126_PD_SDIO { 187 reg = <RV1126_PD_SDIO>; 188 clocks = <&cru HCLK_SDIO>, 189 <&cru CLK_SDIO>; 190 pm_qos = <&qos_sdio>; 191 #power-domain-cells = <0>; 192 }; 193 194 power-domain@RV1126_PD_VO { 195 reg = <RV1126_PD_VO>; 196 clocks = <&cru ACLK_RGA>, 197 <&cru HCLK_RGA>, 198 <&cru CLK_RGA_CORE>, 199 <&cru ACLK_VOP>, 200 <&cru HCLK_VOP>, 201 <&cru DCLK_VOP>, 202 <&cru PCLK_DSIHOST>, 203 <&cru ACLK_IEP>, 204 <&cru HCLK_IEP>, 205 <&cru CLK_IEP_CORE>; 206 pm_qos = <&qos_rga_rd>, 207 <&qos_rga_wr>, 208 <&qos_vop>, 209 <&qos_iep>; 210 #power-domain-cells = <0>; 211 }; 212 }; 213 }; 214 215 i2c0: i2c@ff3f0000 { 216 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 217 reg = <0xff3f0000 0x1000>; 218 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 219 rockchip,grf = <&pmugrf>; 220 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 221 clock-names = "i2c", "pclk"; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&i2c0_xfer>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 status = "disabled"; 227 }; 228 229 uart1: serial@ff410000 { 230 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 231 reg = <0xff410000 0x100>; 232 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 233 clock-frequency = <24000000>; 234 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 235 clock-names = "baudclk", "apb_pclk"; 236 dmas = <&dmac 7>, <&dmac 6>; 237 dma-names = "tx", "rx"; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&uart1m0_xfer>; 240 reg-shift = <2>; 241 reg-io-width = <4>; 242 status = "disabled"; 243 }; 244 245 pmucru: clock-controller@ff480000 { 246 compatible = "rockchip,rv1126-pmucru"; 247 reg = <0xff480000 0x1000>; 248 rockchip,grf = <&grf>; 249 #clock-cells = <1>; 250 #reset-cells = <1>; 251 }; 252 253 cru: clock-controller@ff490000 { 254 compatible = "rockchip,rv1126-cru"; 255 reg = <0xff490000 0x1000>; 256 clocks = <&xin24m>; 257 clock-names = "xin24m"; 258 rockchip,grf = <&grf>; 259 #clock-cells = <1>; 260 #reset-cells = <1>; 261 }; 262 263 dmac: dma-controller@ff4e0000 { 264 compatible = "arm,pl330", "arm,primecell"; 265 reg = <0xff4e0000 0x4000>; 266 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 268 #dma-cells = <1>; 269 arm,pl330-periph-burst; 270 clocks = <&cru ACLK_DMAC>; 271 clock-names = "apb_pclk"; 272 }; 273 274 uart0: serial@ff560000 { 275 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 276 reg = <0xff560000 0x100>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 278 clock-frequency = <24000000>; 279 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 280 clock-names = "baudclk", "apb_pclk"; 281 dmas = <&dmac 5>, <&dmac 4>; 282 dma-names = "tx", "rx"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&uart0_xfer>; 285 reg-shift = <2>; 286 reg-io-width = <4>; 287 status = "disabled"; 288 }; 289 290 uart2: serial@ff570000 { 291 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 292 reg = <0xff570000 0x100>; 293 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 294 clock-frequency = <24000000>; 295 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 296 clock-names = "baudclk", "apb_pclk"; 297 dmas = <&dmac 9>, <&dmac 8>; 298 dma-names = "tx", "rx"; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&uart2m1_xfer>; 301 reg-shift = <2>; 302 reg-io-width = <4>; 303 status = "disabled"; 304 }; 305 306 uart3: serial@ff580000 { 307 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 308 reg = <0xff580000 0x100>; 309 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 310 clock-frequency = <24000000>; 311 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 312 clock-names = "baudclk", "apb_pclk"; 313 dmas = <&dmac 11>, <&dmac 10>; 314 dma-names = "tx", "rx"; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&uart3m0_xfer>; 317 reg-shift = <2>; 318 reg-io-width = <4>; 319 status = "disabled"; 320 }; 321 322 uart4: serial@ff590000 { 323 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 324 reg = <0xff590000 0x100>; 325 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 326 clock-frequency = <24000000>; 327 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 328 clock-names = "baudclk", "apb_pclk"; 329 dmas = <&dmac 13>, <&dmac 12>; 330 dma-names = "tx", "rx"; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&uart4m0_xfer>; 333 reg-shift = <2>; 334 reg-io-width = <4>; 335 status = "disabled"; 336 }; 337 338 uart5: serial@ff5a0000 { 339 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 340 reg = <0xff5a0000 0x100>; 341 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 342 clock-frequency = <24000000>; 343 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 344 clock-names = "baudclk", "apb_pclk"; 345 dmas = <&dmac 15>, <&dmac 14>; 346 dma-names = "tx", "rx"; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&uart5m0_xfer>; 349 reg-shift = <2>; 350 reg-io-width = <4>; 351 status = "disabled"; 352 }; 353 354 saradc: adc@ff5e0000 { 355 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; 356 reg = <0xff5e0000 0x100>; 357 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 358 #io-channel-cells = <1>; 359 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 360 clock-names = "saradc", "apb_pclk"; 361 resets = <&cru SRST_SARADC_P>; 362 reset-names = "saradc-apb"; 363 status = "disabled"; 364 }; 365 366 timer0: timer@ff660000 { 367 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; 368 reg = <0xff660000 0x20>; 369 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 371 clock-names = "pclk", "timer"; 372 }; 373 374 gmac: ethernet@ffc40000 { 375 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 376 reg = <0xffc40000 0x4000>; 377 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 379 interrupt-names = "macirq", "eth_wake_irq"; 380 rockchip,grf = <&grf>; 381 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 382 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 383 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 384 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 385 clock-names = "stmmaceth", "mac_clk_rx", 386 "mac_clk_tx", "clk_mac_ref", 387 "aclk_mac", "pclk_mac", 388 "clk_mac_speed", "ptp_ref"; 389 resets = <&cru SRST_GMAC_A>; 390 reset-names = "stmmaceth"; 391 392 snps,mixed-burst; 393 snps,tso; 394 395 snps,axi-config = <&stmmac_axi_setup>; 396 snps,mtl-rx-config = <&mtl_rx_setup>; 397 snps,mtl-tx-config = <&mtl_tx_setup>; 398 status = "disabled"; 399 400 mdio: mdio { 401 compatible = "snps,dwmac-mdio"; 402 #address-cells = <0x1>; 403 #size-cells = <0x0>; 404 }; 405 406 stmmac_axi_setup: stmmac-axi-config { 407 snps,wr_osr_lmt = <4>; 408 snps,rd_osr_lmt = <8>; 409 snps,blen = <0 0 0 0 16 8 4>; 410 }; 411 412 mtl_rx_setup: rx-queues-config { 413 snps,rx-queues-to-use = <1>; 414 queue0 {}; 415 }; 416 417 mtl_tx_setup: tx-queues-config { 418 snps,tx-queues-to-use = <1>; 419 queue0 {}; 420 }; 421 }; 422 423 emmc: mmc@ffc50000 { 424 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 425 reg = <0xffc50000 0x4000>; 426 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 428 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 429 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 430 fifo-depth = <0x100>; 431 max-frequency = <200000000>; 432 power-domains = <&power RV1126_PD_NVM>; 433 status = "disabled"; 434 }; 435 436 sdmmc: mmc@ffc60000 { 437 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 438 reg = <0xffc60000 0x4000>; 439 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 441 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 442 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 443 fifo-depth = <0x100>; 444 max-frequency = <200000000>; 445 status = "disabled"; 446 }; 447 448 sdio: mmc@ffc70000 { 449 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 450 reg = <0xffc70000 0x4000>; 451 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 453 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 454 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 455 fifo-depth = <0x100>; 456 max-frequency = <200000000>; 457 power-domains = <&power RV1126_PD_SDIO>; 458 status = "disabled"; 459 }; 460 461 sfc: spi@ffc90000 { 462 compatible = "rockchip,sfc"; 463 reg = <0xffc90000 0x4000>; 464 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 465 assigned-clocks = <&cru SCLK_SFC>; 466 assigned-clock-rates = <80000000>; 467 clock-names = "clk_sfc", "hclk_sfc"; 468 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 469 power-domains = <&power RV1126_PD_NVM>; 470 status = "disabled"; 471 }; 472 473 pinctrl: pinctrl { 474 compatible = "rockchip,rv1126-pinctrl"; 475 rockchip,grf = <&grf>; 476 rockchip,pmu = <&pmugrf>; 477 #address-cells = <1>; 478 #size-cells = <1>; 479 ranges; 480 481 gpio0: gpio@ff460000 { 482 compatible = "rockchip,gpio-bank"; 483 reg = <0xff460000 0x100>; 484 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 486 gpio-controller; 487 #gpio-cells = <2>; 488 interrupt-controller; 489 #interrupt-cells = <2>; 490 }; 491 492 gpio1: gpio@ff620000 { 493 compatible = "rockchip,gpio-bank"; 494 reg = <0xff620000 0x100>; 495 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 }; 502 503 gpio2: gpio@ff630000 { 504 compatible = "rockchip,gpio-bank"; 505 reg = <0xff630000 0x100>; 506 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 interrupt-controller; 511 #interrupt-cells = <2>; 512 }; 513 514 gpio3: gpio@ff640000 { 515 compatible = "rockchip,gpio-bank"; 516 reg = <0xff640000 0x100>; 517 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 525 gpio4: gpio@ff650000 { 526 compatible = "rockchip,gpio-bank"; 527 reg = <0xff650000 0x100>; 528 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 530 gpio-controller; 531 #gpio-cells = <2>; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 }; 536}; 537 538#include "rv1126-pinctrl.dtsi" 539