1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for Marvell Armada 382 reference board
4 * (RD-AC3X-48G4X2XL)
5 *
6 * Copyright (C) 2020 Allied Telesis Labs
7 */
8
9/dts-v1/;
10#include "armada-385.dtsi"
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	model = "Marvell Armada 382 RD-AC3X";
16	compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x",
17			 "marvell,armada385", "marvell,armada380";
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	aliases {
24		ethernet0 = &eth1;
25	};
26
27	memory {
28		device_type = "memory";
29		reg = <0x00000000 0x20000000>; /* 512MB */
30	};
31
32	soc {
33		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
34			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
35	};
36};
37
38&i2c0 {
39	pinctrl-names = "default";
40	pinctrl-0 = <&i2c0_pins>;
41	status = "okay";
42
43	eeprom@53 {
44		compatible = "atmel,24c64";
45		reg = <0x53>;
46	};
47
48	/* CPLD device present at 0x3c. Function unknown */
49};
50
51&uart0 {
52	pinctrl-names = "default";
53	pinctrl-0 = <&uart0_pins>;
54	status = "okay";
55};
56
57&eth1 {
58	status = "okay";
59	phy = <&phy0>;
60	phy-mode = "rgmii-id";
61};
62
63&mdio {
64	pinctrl-names = "default";
65	pinctrl-0 = <&mdio_pins>;
66
67	phy0: ethernet-phy@0 {
68		reg = <0>;
69	};
70};
71
72&pciec {
73	status = "okay";
74};
75
76&pcie1 {
77	/* Port 0, Lane 0 */
78	status = "okay";
79};
80
81&nand_controller {
82	status = "okay";
83
84	nand@0 {
85		reg = <0>;
86		label = "pxa3xx_nand-0";
87		nand-rb = <0>;
88		nand-on-flash-bbt;
89
90		partitions {
91			compatible = "fixed-partitions";
92			#address-cells = <1>;
93			#size-cells = <1>;
94			partition@0 {
95				reg = <0x00000000 0x00500000>;
96				label = "u-boot";
97			};
98			partition@500000 {
99				reg = <0x00500000 0x00400000>;
100				label = "u-boot env";
101			};
102			partition@900000 {
103				reg = <0x00900000 0x3F700000>;
104				label = "user";
105			};
106		};
107	};
108};
109
110&refclk {
111	clock-frequency = <200000000>;
112};
113