1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2014 Broadcom Corporation
3
4#include <dt-bindings/clock/bcm21664.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	model = "BCM21664 SoC";
12	compatible = "brcm,bcm21664";
13	interrupt-parent = <&gic>;
14
15	chosen {
16		bootargs = "console=ttyS0,115200n8";
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a9";
26			reg = <0>;
27		};
28
29		cpu1: cpu@1 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a9";
32			enable-method = "brcm,bcm11351-cpu-method";
33			secondary-boot-reg = <0x35004178>;
34			reg = <1>;
35		};
36	};
37
38	gic: interrupt-controller@3ff00100 {
39		compatible = "arm,cortex-a9-gic";
40		#interrupt-cells = <3>;
41		#address-cells = <0>;
42		interrupt-controller;
43		reg = <0x3ff01000 0x1000>,
44		      <0x3ff00100 0x100>;
45	};
46
47	smc@3404e000 {
48		compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
49		reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
50	};
51
52	uartb: serial@3e000000 {
53		compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
54		reg = <0x3e000000 0x118>;
55		clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
56		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
57		reg-shift = <2>;
58		reg-io-width = <4>;
59		status = "disabled";
60	};
61
62	uartb2: serial@3e001000 {
63		compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
64		reg = <0x3e001000 0x118>;
65		clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
66		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
67		reg-shift = <2>;
68		reg-io-width = <4>;
69		status = "disabled";
70	};
71
72	uartb3: serial@3e002000 {
73		compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
74		reg = <0x3e002000 0x118>;
75		clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
76		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
77		reg-shift = <2>;
78		reg-io-width = <4>;
79		status = "disabled";
80	};
81
82	L2: cache-controller@3ff20000 {
83		compatible = "arm,pl310-cache";
84		reg = <0x3ff20000 0x1000>;
85		cache-unified;
86		cache-level = <2>;
87	};
88
89	brcm,resetmgr@35001f00 {
90		compatible = "brcm,bcm21664-resetmgr";
91		reg = <0x35001f00 0x24>;
92	};
93
94	timer@35006000 {
95		compatible = "brcm,kona-timer";
96		reg = <0x35006000 0x1c>;
97		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
98		clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
99	};
100
101	gpio: gpio@35003000 {
102		compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
103		reg = <0x35003000 0x524>;
104		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
105			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
106			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
107			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
108		#gpio-cells = <2>;
109		#interrupt-cells = <2>;
110		gpio-controller;
111		interrupt-controller;
112	};
113
114	sdio1: mmc@3f180000 {
115		compatible = "brcm,kona-sdhci";
116		reg = <0x3f180000 0x801c>;
117		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
118		clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
119		status = "disabled";
120	};
121
122	sdio2: mmc@3f190000 {
123		compatible = "brcm,kona-sdhci";
124		reg = <0x3f190000 0x801c>;
125		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
126		clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
127		status = "disabled";
128	};
129
130	sdio3: mmc@3f1a0000 {
131		compatible = "brcm,kona-sdhci";
132		reg = <0x3f1a0000 0x801c>;
133		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
134		clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
135		status = "disabled";
136	};
137
138	sdio4: mmc@3f1b0000 {
139		compatible = "brcm,kona-sdhci";
140		reg = <0x3f1b0000 0x801c>;
141		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
142		clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
143		status = "disabled";
144	};
145
146	bsc1: i2c@3e016000 {
147		compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
148		reg = <0x3e016000 0x70>;
149		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150		#address-cells = <1>;
151		#size-cells = <0>;
152		clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
153		status = "disabled";
154	};
155
156	bsc2: i2c@3e017000 {
157		compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
158		reg = <0x3e017000 0x70>;
159		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
160		#address-cells = <1>;
161		#size-cells = <0>;
162		clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
163		status = "disabled";
164	};
165
166	bsc3: i2c@3e018000 {
167		compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
168		reg = <0x3e018000 0x70>;
169		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
170		#address-cells = <1>;
171		#size-cells = <0>;
172		clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
173		status = "disabled";
174	};
175
176	bsc4: i2c@3e01c000 {
177		compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
178		reg = <0x3e01c000 0x70>;
179		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
180		#address-cells = <1>;
181		#size-cells = <0>;
182		clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
183		status = "disabled";
184	};
185
186	clocks {
187		#address-cells = <1>;
188		#size-cells = <1>;
189		ranges;
190
191		/*
192		 * Fixed clocks are defined before CCUs whose
193		 * clocks may depend on them.
194		 */
195
196		ref_32k_clk: ref_32k {
197			#clock-cells = <0>;
198			compatible = "fixed-clock";
199			clock-frequency = <32768>;
200		};
201
202		bbl_32k_clk: bbl_32k {
203			#clock-cells = <0>;
204			compatible = "fixed-clock";
205			clock-frequency = <32768>;
206		};
207
208		ref_13m_clk: ref_13m {
209			#clock-cells = <0>;
210			compatible = "fixed-clock";
211			clock-frequency = <13000000>;
212		};
213
214		var_13m_clk: var_13m {
215			#clock-cells = <0>;
216			compatible = "fixed-clock";
217			clock-frequency = <13000000>;
218		};
219
220		dft_19_5m_clk: dft_19_5m {
221			#clock-cells = <0>;
222			compatible = "fixed-clock";
223			clock-frequency = <19500000>;
224		};
225
226		ref_crystal_clk: ref_crystal {
227			#clock-cells = <0>;
228			compatible = "fixed-clock";
229			clock-frequency = <26000000>;
230		};
231
232		ref_52m_clk: ref_52m {
233			#clock-cells = <0>;
234			compatible = "fixed-clock";
235			clock-frequency = <52000000>;
236		};
237
238		var_52m_clk: var_52m {
239			#clock-cells = <0>;
240			compatible = "fixed-clock";
241			clock-frequency = <52000000>;
242		};
243
244		usb_otg_ahb_clk: usb_otg_ahb {
245			#clock-cells = <0>;
246			compatible = "fixed-clock";
247			clock-frequency = <52000000>;
248		};
249
250		ref_96m_clk: ref_96m {
251			#clock-cells = <0>;
252			compatible = "fixed-clock";
253			clock-frequency = <96000000>;
254		};
255
256		var_96m_clk: var_96m {
257			#clock-cells = <0>;
258			compatible = "fixed-clock";
259			clock-frequency = <96000000>;
260		};
261
262		ref_104m_clk: ref_104m {
263			#clock-cells = <0>;
264			compatible = "fixed-clock";
265			clock-frequency = <104000000>;
266		};
267
268		var_104m_clk: var_104m {
269			#clock-cells = <0>;
270			compatible = "fixed-clock";
271			clock-frequency = <104000000>;
272		};
273
274		ref_156m_clk: ref_156m {
275			#clock-cells = <0>;
276			compatible = "fixed-clock";
277			clock-frequency = <156000000>;
278		};
279
280		var_156m_clk: var_156m {
281			#clock-cells = <0>;
282			compatible = "fixed-clock";
283			clock-frequency = <156000000>;
284		};
285
286		root_ccu: root_ccu@35001000 {
287			compatible = "brcm,bcm21664-root-ccu";
288			reg = <0x35001000 0x0f00>;
289			#clock-cells = <1>;
290			clock-output-names = "frac_1m";
291		};
292
293		aon_ccu: aon_ccu@35002000 {
294			compatible = "brcm,bcm21664-aon-ccu";
295			reg = <0x35002000 0x0f00>;
296			#clock-cells = <1>;
297			clock-output-names = "hub_timer";
298		};
299
300		master_ccu: master_ccu@3f001000 {
301			compatible = "brcm,bcm21664-master-ccu";
302			reg = <0x3f001000 0x0f00>;
303			#clock-cells = <1>;
304			clock-output-names = "sdio1",
305					     "sdio2",
306					     "sdio3",
307					     "sdio4",
308					     "sdio1_sleep",
309					     "sdio2_sleep",
310					     "sdio3_sleep",
311					     "sdio4_sleep";
312		};
313
314		slave_ccu: slave_ccu@3e011000 {
315			compatible = "brcm,bcm21664-slave-ccu";
316			reg = <0x3e011000 0x0f00>;
317			#clock-cells = <1>;
318			clock-output-names = "uartb",
319					     "uartb2",
320					     "uartb3",
321					     "bsc1",
322					     "bsc2",
323					     "bsc3",
324					     "bsc4";
325		};
326	};
327
328	usbotg: usb@3f120000 {
329		compatible = "snps,dwc2";
330		reg = <0x3f120000 0x10000>;
331		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
332		clocks = <&usb_otg_ahb_clk>;
333		clock-names = "otg";
334		phys = <&usbphy>;
335		phy-names = "usb2-phy";
336		status = "disabled";
337	};
338
339	usbphy: usb-phy@3f130000 {
340		compatible = "brcm,kona-usb2-phy";
341		reg = <0x3f130000 0x28>;
342		#phy-cells = <0>;
343		status = "disabled";
344	};
345};
346