1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
4 */
5
6#include <dt-bindings/clock/bcm-nsp.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13	interrupt-parent = <&gic>;
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	chipcommon-a-bus@18000000 {
18		compatible = "simple-bus";
19		ranges = <0x00000000 0x18000000 0x00001000>;
20		#address-cells = <1>;
21		#size-cells = <1>;
22
23		uart0: serial@300 {
24			compatible = "ns16550";
25			reg = <0x0300 0x100>;
26			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
27			clocks = <&iprocslow>;
28			status = "disabled";
29		};
30
31		uart1: serial@400 {
32			compatible = "ns16550";
33			reg = <0x0400 0x100>;
34			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
35			clocks = <&iprocslow>;
36			pinctrl-names = "default";
37			pinctrl-0 = <&pinmux_uart1>;
38			status = "disabled";
39		};
40	};
41
42	mpcore-bus@19000000 {
43		compatible = "simple-bus";
44		ranges = <0x00000000 0x19000000 0x00023000>;
45		#address-cells = <1>;
46		#size-cells = <1>;
47
48		scu@20000 {
49			compatible = "arm,cortex-a9-scu";
50			reg = <0x20000 0x100>;
51		};
52
53		timer@20200 {
54			compatible = "arm,cortex-a9-global-timer";
55			reg = <0x20200 0x100>;
56			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
57			clocks = <&periph_clk>;
58		};
59
60		timer@20600 {
61			compatible = "arm,cortex-a9-twd-timer";
62			reg = <0x20600 0x20>;
63			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
64						  IRQ_TYPE_EDGE_RISING)>;
65			clocks = <&periph_clk>;
66		};
67
68		gic: interrupt-controller@21000 {
69			compatible = "arm,cortex-a9-gic";
70			#interrupt-cells = <3>;
71			#address-cells = <0>;
72			interrupt-controller;
73			reg = <0x21000 0x1000>,
74			      <0x20100 0x100>;
75		};
76
77		L2: cache-controller@22000 {
78			compatible = "arm,pl310-cache";
79			reg = <0x22000 0x1000>;
80			cache-unified;
81			arm,shared-override;
82			prefetch-data = <1>;
83			prefetch-instr = <1>;
84			cache-level = <2>;
85		};
86	};
87
88	axi@18000000 {
89		compatible = "brcm,bus-axi";
90		reg = <0x18000000 0x1000>;
91		ranges = <0x00000000 0x18000000 0x00100000>;
92		#address-cells = <1>;
93		#size-cells = <1>;
94
95		#interrupt-cells = <1>;
96		interrupt-map-mask = <0x000fffff 0xffff>;
97		interrupt-map =
98			/* ChipCommon */
99			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
100
101			/* Switch Register Access Block */
102			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
103			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
104			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
105			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
106			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
107			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
108			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
109			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
110			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
111			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
112			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
113			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
114			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
115
116			/* PCIe Controller 0 */
117			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
118			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
119			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
120			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
121			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
122			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
123
124			/* PCIe Controller 1 */
125			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
126			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
127			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
128			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
129			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
130			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
131
132			/* PCIe Controller 2 */
133			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
134			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
135			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
136			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
137			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
138			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
139
140			/* USB 2.0 Controller */
141			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
142
143			/* USB 3.0 Controller */
144			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
145
146			/* Ethernet Controller 0 */
147			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
148
149			/* Ethernet Controller 1 */
150			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
151
152			/* Ethernet Controller 2 */
153			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
154
155			/* Ethernet Controller 3 */
156			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
157
158			/* NAND Controller */
159			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
160			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
161			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
162			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
163			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
164			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
165			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
166			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
167
168		chipcommon: chipcommon@0 {
169			reg = <0x00000000 0x1000>;
170
171			gpio-controller;
172			#gpio-cells = <2>;
173			interrupt-controller;
174			#interrupt-cells = <2>;
175		};
176
177		pcie0: pcie@12000 {
178			reg = <0x00012000 0x1000>;
179
180			#address-cells = <3>;
181			#size-cells = <2>;
182		};
183
184		pcie1: pcie@13000 {
185			reg = <0x00013000 0x1000>;
186
187			#address-cells = <3>;
188			#size-cells = <2>;
189		};
190
191		pcie2: pcie@14000 {
192			reg = <0x00014000 0x1000>;
193
194			#address-cells = <3>;
195			#size-cells = <2>;
196		};
197
198		usb2: usb2@21000 {
199			reg = <0x00021000 0x1000>;
200
201			#address-cells = <1>;
202			#size-cells = <1>;
203			ranges;
204
205			interrupt-parent = <&gic>;
206
207			ehci: usb@21000 {
208				compatible = "generic-ehci";
209				reg = <0x00021000 0x1000>;
210				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
211				phys = <&usb2_phy>;
212
213				#address-cells = <1>;
214				#size-cells = <0>;
215
216				ehci_port1: port@1 {
217					reg = <1>;
218					#trigger-source-cells = <0>;
219				};
220
221				ehci_port2: port@2 {
222					reg = <2>;
223					#trigger-source-cells = <0>;
224				};
225			};
226
227			ohci: usb@22000 {
228				compatible = "generic-ohci";
229				reg = <0x00022000 0x1000>;
230				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
231
232				#address-cells = <1>;
233				#size-cells = <0>;
234
235				ohci_port1: port@1 {
236					reg = <1>;
237					#trigger-source-cells = <0>;
238				};
239
240				ohci_port2: port@2 {
241					reg = <2>;
242					#trigger-source-cells = <0>;
243				};
244			};
245		};
246
247		usb3: usb3@23000 {
248			reg = <0x00023000 0x1000>;
249
250			#address-cells = <1>;
251			#size-cells = <1>;
252			ranges;
253
254			interrupt-parent = <&gic>;
255
256			xhci: usb@23000 {
257				compatible = "generic-xhci";
258				reg = <0x00023000 0x1000>;
259				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
260				phys = <&usb3_phy>;
261				phy-names = "usb";
262
263				#address-cells = <1>;
264				#size-cells = <0>;
265
266				xhci_port1: port@1 {
267					reg = <1>;
268					#trigger-source-cells = <0>;
269				};
270			};
271		};
272
273		gmac0: ethernet@24000 {
274			reg = <0x24000 0x800>;
275			phy-mode = "internal";
276
277			fixed-link {
278				speed = <1000>;
279				full-duplex;
280			};
281		};
282
283		gmac1: ethernet@25000 {
284			reg = <0x25000 0x800>;
285			phy-mode = "internal";
286
287			fixed-link {
288				speed = <1000>;
289				full-duplex;
290			};
291		};
292
293		gmac2: ethernet@26000 {
294			reg = <0x26000 0x800>;
295			phy-mode = "internal";
296
297			fixed-link {
298				speed = <1000>;
299				full-duplex;
300			};
301		};
302
303		gmac3: ethernet@27000 {
304			reg = <0x27000 0x800>;
305		};
306	};
307
308	pwm: pwm@18002000 {
309		compatible = "brcm,iproc-pwm";
310		reg = <0x18002000 0x28>;
311		clocks = <&osc>;
312		#pwm-cells = <3>;
313		status = "disabled";
314	};
315
316	mdio: mdio@18003000 {
317		compatible = "brcm,iproc-mdio";
318		reg = <0x18003000 0x8>;
319		#size-cells = <0>;
320		#address-cells = <1>;
321	};
322
323	rng: rng@18004000 {
324		compatible = "brcm,bcm5301x-rng";
325		reg = <0x18004000 0x14>;
326	};
327
328	srab: ethernet-switch@18007000 {
329		compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
330		reg = <0x18007000 0x1000>;
331
332		status = "disabled";
333
334		ports {
335			#address-cells = <1>;
336			#size-cells = <0>;
337
338			port@0 {
339				reg = <0>;
340			};
341
342			port@1 {
343				reg = <1>;
344			};
345
346			port@2 {
347				reg = <2>;
348			};
349
350			port@3 {
351				reg = <3>;
352			};
353
354			port@4 {
355				reg = <4>;
356			};
357
358			port@5 {
359				reg = <5>;
360				ethernet = <&gmac0>;
361			};
362
363			port@7 {
364				reg = <7>;
365				ethernet = <&gmac1>;
366			};
367
368			port@8 {
369				reg = <8>;
370				ethernet = <&gmac2>;
371
372				fixed-link {
373					speed = <1000>;
374					full-duplex;
375				};
376			};
377		};
378	};
379
380	uart2: serial@18008000 {
381		compatible = "ns16550a";
382		reg = <0x18008000 0x20>;
383		clocks = <&iprocslow>;
384		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
385		reg-shift = <2>;
386		status = "disabled";
387	};
388
389	dmu-bus@1800c000 {
390		compatible = "simple-bus";
391		ranges = <0 0x1800c000 0x1000>;
392		#address-cells = <1>;
393		#size-cells = <1>;
394
395		cru-bus@100 {
396			compatible = "brcm,ns-cru", "simple-mfd";
397			reg = <0x100 0x1a4>;
398			ranges;
399			#address-cells = <1>;
400			#size-cells = <1>;
401
402			usb2_phy: phy@164 {
403				compatible = "brcm,ns-usb2-phy";
404				reg = <0x164 0x4>;
405				brcm,syscon-clkset = <&cru_clkset>;
406				clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
407				clock-names = "phy-ref-clk";
408				#phy-cells = <0>;
409			};
410
411			cru_clkset: syscon@180 {
412				compatible = "brcm,cru-clkset", "syscon";
413				reg = <0x180 0x4>;
414			};
415
416			pinctrl: pinctrl@1c0 {
417				compatible = "brcm,bcm4708-pinmux";
418				reg = <0x1c0 0x24>;
419				reg-names = "cru_gpio_control";
420
421				spi-pins {
422					groups = "spi_grp";
423					function = "spi";
424				};
425
426				pinmux_i2c: i2c-pins {
427					groups = "i2c_grp";
428					function = "i2c";
429				};
430
431				pinmux_pwm: pwm-pins {
432					groups = "pwm0_grp", "pwm1_grp",
433						 "pwm2_grp", "pwm3_grp";
434					function = "pwm";
435				};
436
437				pinmux_uart1: uart1-pins {
438					groups = "uart1_grp";
439					function = "uart1";
440				};
441			};
442
443			thermal: thermal@2c0 {
444				compatible = "brcm,ns-thermal";
445				reg = <0x2c0 0x10>;
446				#thermal-sensor-cells = <0>;
447			};
448		};
449	};
450
451	nand_controller: nand-controller@18028000 {
452		compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
453		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
454		reg-names = "nand", "iproc-idm", "iproc-ext";
455		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
456
457		#address-cells = <1>;
458		#size-cells = <0>;
459
460		brcm,nand-has-wp;
461	};
462
463	thermal-zones {
464		cpu_thermal: cpu-thermal {
465			polling-delay-passive = <0>;
466			polling-delay = <1000>;
467			coefficients = <(-556) 418000>;
468			thermal-sensors = <&thermal>;
469
470			trips {
471				cpu-crit {
472					temperature = <125000>;
473					hysteresis = <0>;
474					type = "critical";
475				};
476			};
477
478			cooling-maps {
479			};
480		};
481	};
482};
483