1/*
2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device Tree for ARC HS Development Kit
11 */
12/dts-v1/;
13
14#include <dt-bindings/net/ti-dp83867.h>
15#include <dt-bindings/reset/snps,hsdk-reset.h>
16
17/ {
18	model = "snps,hsdk";
19	compatible = "snps,hsdk";
20
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	chosen {
25		bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
26	};
27
28	aliases {
29		ethernet = &gmac;
30	};
31
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		cpu@0 {
37			device_type = "cpu";
38			compatible = "snps,archs38";
39			reg = <0>;
40			clocks = <&core_clk>;
41		};
42
43		cpu@1 {
44			device_type = "cpu";
45			compatible = "snps,archs38";
46			reg = <1>;
47			clocks = <&core_clk>;
48		};
49
50		cpu@2 {
51			device_type = "cpu";
52			compatible = "snps,archs38";
53			reg = <2>;
54			clocks = <&core_clk>;
55		};
56
57		cpu@3 {
58			device_type = "cpu";
59			compatible = "snps,archs38";
60			reg = <3>;
61			clocks = <&core_clk>;
62		};
63	};
64
65	input_clk: input-clk {
66		#clock-cells = <0>;
67		compatible = "fixed-clock";
68		clock-frequency = <33333333>;
69	};
70
71	cpu_intc: cpu-interrupt-controller {
72		compatible = "snps,archs-intc";
73		interrupt-controller;
74		#interrupt-cells = <1>;
75	};
76
77	idu_intc: idu-interrupt-controller {
78		compatible = "snps,archs-idu-intc";
79		interrupt-controller;
80		#interrupt-cells = <1>;
81		interrupt-parent = <&cpu_intc>;
82	};
83
84	arcpct: pct {
85		compatible = "snps,archs-pct";
86	};
87
88	/* TIMER0 with interrupt for clockevent */
89	timer {
90		compatible = "snps,arc-timer";
91		interrupts = <16>;
92		interrupt-parent = <&cpu_intc>;
93		clocks = <&core_clk>;
94	};
95
96	/* 64-bit Global Free Running Counter */
97	gfrc {
98		compatible = "snps,archs-timer-gfrc";
99		clocks = <&core_clk>;
100	};
101
102	soc {
103		compatible = "simple-bus";
104		#address-cells = <1>;
105		#size-cells = <1>;
106		interrupt-parent = <&idu_intc>;
107
108		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
109
110		cgu_rst: reset-controller@8a0 {
111			compatible = "snps,hsdk-reset";
112			#reset-cells = <1>;
113			reg = <0x8a0 0x4>, <0xff0 0x4>;
114		};
115
116		core_clk: core-clk@0 {
117			compatible = "snps,hsdk-core-pll-clock";
118			reg = <0x00 0x10>, <0x14b8 0x4>;
119			#clock-cells = <0>;
120			clocks = <&input_clk>;
121
122			/*
123			 * Set initial core pll output frequency to 1GHz.
124			 * It will be applied at the core pll driver probing
125			 * on early boot.
126			 */
127			assigned-clocks = <&core_clk>;
128			assigned-clock-rates = <1000000000>;
129		};
130
131		serial: serial@5000 {
132			compatible = "snps,dw-apb-uart";
133			reg = <0x5000 0x100>;
134			clock-frequency = <33330000>;
135			interrupts = <6>;
136			baud = <115200>;
137			reg-shift = <2>;
138			reg-io-width = <4>;
139		};
140
141		gmacclk: gmacclk {
142			compatible = "fixed-clock";
143			clock-frequency = <400000000>;
144			#clock-cells = <0>;
145		};
146
147		mmcclk_ciu: mmcclk-ciu {
148			compatible = "fixed-clock";
149			/*
150			 * DW sdio controller has external ciu clock divider
151			 * controlled via register in SDIO IP. Due to its
152			 * unexpected default value (it should divide by 1
153			 * but it divides by 8) SDIO IP uses wrong clock and
154			 * works unstable (see STAR 9001204800)
155			 * We switched to the minimum possible value of the
156			 * divisor (div-by-2) in HSDK platform code.
157			 * So add temporary fix and change clock frequency
158			 * to 50000000 Hz until we fix dw sdio driver itself.
159			 */
160			clock-frequency = <50000000>;
161			#clock-cells = <0>;
162		};
163
164		mmcclk_biu: mmcclk-biu {
165			compatible = "fixed-clock";
166			clock-frequency = <400000000>;
167			#clock-cells = <0>;
168		};
169
170		gpu_core_clk: gpu-core-clk {
171			compatible = "fixed-clock";
172			clock-frequency = <400000000>;
173			#clock-cells = <0>;
174		};
175
176		gpu_dma_clk: gpu-dma-clk {
177			compatible = "fixed-clock";
178			clock-frequency = <400000000>;
179			#clock-cells = <0>;
180		};
181
182		gpu_cfg_clk: gpu-cfg-clk {
183			compatible = "fixed-clock";
184			clock-frequency = <200000000>;
185			#clock-cells = <0>;
186		};
187
188		dmac_core_clk: dmac-core-clk {
189			compatible = "fixed-clock";
190			clock-frequency = <400000000>;
191			#clock-cells = <0>;
192		};
193
194		dmac_cfg_clk: dmac-gpu-cfg-clk {
195			compatible = "fixed-clock";
196			clock-frequency = <200000000>;
197			#clock-cells = <0>;
198		};
199
200		gmac: ethernet@8000 {
201			#interrupt-cells = <1>;
202			compatible = "snps,dwmac";
203			reg = <0x8000 0x2000>;
204			interrupts = <10>;
205			interrupt-names = "macirq";
206			phy-mode = "rgmii";
207			snps,pbl = <32>;
208			snps,multicast-filter-bins = <256>;
209			clocks = <&gmacclk>;
210			clock-names = "stmmaceth";
211			phy-handle = <&phy0>;
212			resets = <&cgu_rst HSDK_ETH_RESET>;
213			reset-names = "stmmaceth";
214			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
215			dma-coherent;
216
217			tx-fifo-depth = <4096>;
218			rx-fifo-depth = <4096>;
219
220			mdio {
221				#address-cells = <1>;
222				#size-cells = <0>;
223				compatible = "snps,dwmac-mdio";
224				phy0: ethernet-phy@0 {
225					reg = <0>;
226					ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
227					ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
228					ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
229				};
230			};
231		};
232
233		ohci@60000 {
234			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
235			reg = <0x60000 0x100>;
236			interrupts = <15>;
237			resets = <&cgu_rst HSDK_USB_RESET>;
238			dma-coherent;
239		};
240
241		ehci@40000 {
242			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
243			reg = <0x40000 0x100>;
244			interrupts = <15>;
245			resets = <&cgu_rst HSDK_USB_RESET>;
246			dma-coherent;
247		};
248
249		mmc@a000 {
250			compatible = "altr,socfpga-dw-mshc";
251			reg = <0xa000 0x400>;
252			num-slots = <1>;
253			fifo-depth = <16>;
254			card-detect-delay = <200>;
255			clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
256			clock-names = "biu", "ciu";
257			interrupts = <12>;
258			bus-width = <4>;
259			dma-coherent;
260		};
261
262		creg_gpio: gpio@14b0 {
263			compatible = "snps,creg-gpio-hsdk";
264			reg = <0x14b0 0x4>;
265			gpio-controller;
266			#gpio-cells = <2>;
267			ngpios = <2>;
268		};
269
270		gpio: gpio@3000 {
271			compatible = "snps,dw-apb-gpio";
272			reg = <0x3000 0x20>;
273			#address-cells = <1>;
274			#size-cells = <0>;
275
276			gpio_port_a: gpio-controller@0 {
277				compatible = "snps,dw-apb-gpio-port";
278				gpio-controller;
279				#gpio-cells = <2>;
280				snps,nr-gpios = <24>;
281				reg = <0>;
282			};
283		};
284
285		gpu_3d: gpu@90000 {
286			compatible = "vivante,gc";
287			reg = <0x90000 0x4000>;
288			clocks = <&gpu_dma_clk>,
289				 <&gpu_cfg_clk>,
290				 <&gpu_core_clk>,
291				 <&gpu_core_clk>;
292			clock-names = "bus", "reg", "core", "shader";
293			interrupts = <28>;
294		};
295
296		dmac: dmac@80000 {
297			compatible = "snps,axi-dma-1.01a";
298			reg = <0x80000 0x400>;
299			interrupts = <27>;
300			clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
301			clock-names = "core-clk", "cfgr-clk";
302
303			dma-channels = <4>;
304			snps,dma-masters = <2>;
305			snps,data-width = <3>;
306			snps,block-size = <4096 4096 4096 4096>;
307			snps,priority = <0 1 2 3>;
308			snps,axi-max-burst-len = <16>;
309		};
310	};
311
312	memory@80000000 {
313		#address-cells = <2>;
314		#size-cells = <2>;
315		device_type = "memory";
316		reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
317		/*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */
318	};
319};
320