1a518d637SAlexey Brodkin/* 2a518d637SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 3a518d637SAlexey Brodkin * 4a518d637SAlexey Brodkin * This program is free software; you can redistribute it and/or modify 5a518d637SAlexey Brodkin * it under the terms of the GNU General Public License version 2 as 6a518d637SAlexey Brodkin * published by the Free Software Foundation. 7a518d637SAlexey Brodkin */ 8a518d637SAlexey Brodkin 9a518d637SAlexey Brodkin/* 10a518d637SAlexey Brodkin * Device Tree for ARC HS Development Kit 11a518d637SAlexey Brodkin */ 12a518d637SAlexey Brodkin/dts-v1/; 13a518d637SAlexey Brodkin 14a518d637SAlexey Brodkin#include <dt-bindings/net/ti-dp83867.h> 15a518d637SAlexey Brodkin 16a518d637SAlexey Brodkin/ { 17a518d637SAlexey Brodkin model = "snps,hsdk"; 18a518d637SAlexey Brodkin compatible = "snps,hsdk"; 19a518d637SAlexey Brodkin 20a518d637SAlexey Brodkin #address-cells = <1>; 21a518d637SAlexey Brodkin #size-cells = <1>; 22a518d637SAlexey Brodkin 23a518d637SAlexey Brodkin chosen { 24a518d637SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 25a518d637SAlexey Brodkin }; 26a518d637SAlexey Brodkin 27a518d637SAlexey Brodkin cpus { 28a518d637SAlexey Brodkin #address-cells = <1>; 29a518d637SAlexey Brodkin #size-cells = <0>; 30a518d637SAlexey Brodkin 31a518d637SAlexey Brodkin cpu@0 { 32a518d637SAlexey Brodkin device_type = "cpu"; 33a518d637SAlexey Brodkin compatible = "snps,archs38"; 34a518d637SAlexey Brodkin reg = <0>; 35a518d637SAlexey Brodkin clocks = <&core_clk>; 36a518d637SAlexey Brodkin }; 37a518d637SAlexey Brodkin 38a518d637SAlexey Brodkin cpu@1 { 39a518d637SAlexey Brodkin device_type = "cpu"; 40a518d637SAlexey Brodkin compatible = "snps,archs38"; 41a518d637SAlexey Brodkin reg = <1>; 42a518d637SAlexey Brodkin clocks = <&core_clk>; 43a518d637SAlexey Brodkin }; 44a518d637SAlexey Brodkin 45a518d637SAlexey Brodkin cpu@2 { 46a518d637SAlexey Brodkin device_type = "cpu"; 47a518d637SAlexey Brodkin compatible = "snps,archs38"; 48a518d637SAlexey Brodkin reg = <2>; 49a518d637SAlexey Brodkin clocks = <&core_clk>; 50a518d637SAlexey Brodkin }; 51a518d637SAlexey Brodkin 52a518d637SAlexey Brodkin cpu@3 { 53a518d637SAlexey Brodkin device_type = "cpu"; 54a518d637SAlexey Brodkin compatible = "snps,archs38"; 55a518d637SAlexey Brodkin reg = <3>; 56a518d637SAlexey Brodkin clocks = <&core_clk>; 57a518d637SAlexey Brodkin }; 58a518d637SAlexey Brodkin }; 59a518d637SAlexey Brodkin 60ef833eabSEugeniy Paltsev input_clk: input-clk { 61a518d637SAlexey Brodkin #clock-cells = <0>; 62a518d637SAlexey Brodkin compatible = "fixed-clock"; 63ef833eabSEugeniy Paltsev clock-frequency = <33333333>; 64a518d637SAlexey Brodkin }; 65a518d637SAlexey Brodkin 66a518d637SAlexey Brodkin cpu_intc: cpu-interrupt-controller { 67a518d637SAlexey Brodkin compatible = "snps,archs-intc"; 68a518d637SAlexey Brodkin interrupt-controller; 69a518d637SAlexey Brodkin #interrupt-cells = <1>; 70a518d637SAlexey Brodkin }; 71a518d637SAlexey Brodkin 72a518d637SAlexey Brodkin idu_intc: idu-interrupt-controller { 73a518d637SAlexey Brodkin compatible = "snps,archs-idu-intc"; 74a518d637SAlexey Brodkin interrupt-controller; 75a518d637SAlexey Brodkin #interrupt-cells = <1>; 76a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 77a518d637SAlexey Brodkin }; 78a518d637SAlexey Brodkin 79a518d637SAlexey Brodkin arcpct: pct { 80a518d637SAlexey Brodkin compatible = "snps,archs-pct"; 81a518d637SAlexey Brodkin }; 82a518d637SAlexey Brodkin 83a518d637SAlexey Brodkin /* TIMER0 with interrupt for clockevent */ 84a518d637SAlexey Brodkin timer { 85a518d637SAlexey Brodkin compatible = "snps,arc-timer"; 86a518d637SAlexey Brodkin interrupts = <16>; 87a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 88a518d637SAlexey Brodkin clocks = <&core_clk>; 89a518d637SAlexey Brodkin }; 90a518d637SAlexey Brodkin 91a518d637SAlexey Brodkin /* 64-bit Global Free Running Counter */ 92a518d637SAlexey Brodkin gfrc { 93a518d637SAlexey Brodkin compatible = "snps,archs-timer-gfrc"; 94a518d637SAlexey Brodkin clocks = <&core_clk>; 95a518d637SAlexey Brodkin }; 96a518d637SAlexey Brodkin 97a518d637SAlexey Brodkin soc { 98a518d637SAlexey Brodkin compatible = "simple-bus"; 99a518d637SAlexey Brodkin #address-cells = <1>; 100a518d637SAlexey Brodkin #size-cells = <1>; 101a518d637SAlexey Brodkin interrupt-parent = <&idu_intc>; 102a518d637SAlexey Brodkin 103a518d637SAlexey Brodkin ranges = <0x00000000 0xf0000000 0x10000000>; 104a518d637SAlexey Brodkin 105ef833eabSEugeniy Paltsev core_clk: core-clk@0 { 106ef833eabSEugeniy Paltsev compatible = "snps,hsdk-core-pll-clock"; 107ef833eabSEugeniy Paltsev reg = <0x00 0x10>, <0x14B8 0x4>; 108ef833eabSEugeniy Paltsev #clock-cells = <0>; 109ef833eabSEugeniy Paltsev clocks = <&input_clk>; 110ef833eabSEugeniy Paltsev }; 111ef833eabSEugeniy Paltsev 112a518d637SAlexey Brodkin serial: serial@5000 { 113a518d637SAlexey Brodkin compatible = "snps,dw-apb-uart"; 114a518d637SAlexey Brodkin reg = <0x5000 0x100>; 115a518d637SAlexey Brodkin clock-frequency = <33330000>; 116a518d637SAlexey Brodkin interrupts = <6>; 117a518d637SAlexey Brodkin baud = <115200>; 118a518d637SAlexey Brodkin reg-shift = <2>; 119a518d637SAlexey Brodkin reg-io-width = <4>; 120a518d637SAlexey Brodkin }; 121a518d637SAlexey Brodkin 122a518d637SAlexey Brodkin gmacclk: gmacclk { 123a518d637SAlexey Brodkin compatible = "fixed-clock"; 124a518d637SAlexey Brodkin clock-frequency = <400000000>; 125a518d637SAlexey Brodkin #clock-cells = <0>; 126a518d637SAlexey Brodkin }; 127a518d637SAlexey Brodkin 128a518d637SAlexey Brodkin mmcclk_ciu: mmcclk-ciu { 129a518d637SAlexey Brodkin compatible = "fixed-clock"; 1306afa3bcfSEugeniy Paltsev /* 1316afa3bcfSEugeniy Paltsev * DW sdio controller has external ciu clock divider 1326afa3bcfSEugeniy Paltsev * controlled via register in SDIO IP. Due to its 1336afa3bcfSEugeniy Paltsev * unexpected default value (it should devide by 1 1346afa3bcfSEugeniy Paltsev * but it devides by 8) SDIO IP uses wrong clock and 1356afa3bcfSEugeniy Paltsev * works unstable (see STAR 9001204800) 1366afa3bcfSEugeniy Paltsev * So add temporary fix and change clock frequency 1376afa3bcfSEugeniy Paltsev * from 100000000 to 12500000 Hz until we fix dw sdio 1386afa3bcfSEugeniy Paltsev * driver itself. 1396afa3bcfSEugeniy Paltsev */ 1406afa3bcfSEugeniy Paltsev clock-frequency = <12500000>; 141a518d637SAlexey Brodkin #clock-cells = <0>; 142a518d637SAlexey Brodkin }; 143a518d637SAlexey Brodkin 144a518d637SAlexey Brodkin mmcclk_biu: mmcclk-biu { 145a518d637SAlexey Brodkin compatible = "fixed-clock"; 146a518d637SAlexey Brodkin clock-frequency = <400000000>; 147a518d637SAlexey Brodkin #clock-cells = <0>; 148a518d637SAlexey Brodkin }; 149a518d637SAlexey Brodkin 150a518d637SAlexey Brodkin ethernet@8000 { 151a518d637SAlexey Brodkin #interrupt-cells = <1>; 152a518d637SAlexey Brodkin compatible = "snps,dwmac"; 153a518d637SAlexey Brodkin reg = <0x8000 0x2000>; 154a518d637SAlexey Brodkin interrupts = <10>; 155a518d637SAlexey Brodkin interrupt-names = "macirq"; 156a518d637SAlexey Brodkin phy-mode = "rgmii"; 157a518d637SAlexey Brodkin snps,pbl = <32>; 158a518d637SAlexey Brodkin clocks = <&gmacclk>; 159a518d637SAlexey Brodkin clock-names = "stmmaceth"; 160a518d637SAlexey Brodkin phy-handle = <&phy0>; 161a518d637SAlexey Brodkin 162a518d637SAlexey Brodkin mdio { 163a518d637SAlexey Brodkin #address-cells = <1>; 164a518d637SAlexey Brodkin #size-cells = <0>; 165a518d637SAlexey Brodkin compatible = "snps,dwmac-mdio"; 166a518d637SAlexey Brodkin phy0: ethernet-phy@0 { 167a518d637SAlexey Brodkin reg = <0>; 168a518d637SAlexey Brodkin ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 169a518d637SAlexey Brodkin ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 170a518d637SAlexey Brodkin ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 171a518d637SAlexey Brodkin }; 172a518d637SAlexey Brodkin }; 173a518d637SAlexey Brodkin }; 174a518d637SAlexey Brodkin 175a518d637SAlexey Brodkin ohci@60000 { 176a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 177a518d637SAlexey Brodkin reg = <0x60000 0x100>; 178a518d637SAlexey Brodkin interrupts = <15>; 179a518d637SAlexey Brodkin }; 180a518d637SAlexey Brodkin 181a518d637SAlexey Brodkin ehci@40000 { 182a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 183a518d637SAlexey Brodkin reg = <0x40000 0x100>; 184a518d637SAlexey Brodkin interrupts = <15>; 185a518d637SAlexey Brodkin }; 186a518d637SAlexey Brodkin 187a518d637SAlexey Brodkin mmc@a000 { 188a518d637SAlexey Brodkin compatible = "altr,socfpga-dw-mshc"; 189a518d637SAlexey Brodkin reg = <0xa000 0x400>; 190a518d637SAlexey Brodkin num-slots = <1>; 191a518d637SAlexey Brodkin fifo-depth = <16>; 192a518d637SAlexey Brodkin card-detect-delay = <200>; 193a518d637SAlexey Brodkin clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 194a518d637SAlexey Brodkin clock-names = "biu", "ciu"; 195a518d637SAlexey Brodkin interrupts = <12>; 196a518d637SAlexey Brodkin bus-width = <4>; 197a518d637SAlexey Brodkin }; 198a518d637SAlexey Brodkin }; 199a518d637SAlexey Brodkin 200a518d637SAlexey Brodkin memory@80000000 { 201a518d637SAlexey Brodkin #address-cells = <1>; 202a518d637SAlexey Brodkin #size-cells = <1>; 203a518d637SAlexey Brodkin device_type = "memory"; 204a518d637SAlexey Brodkin reg = <0x80000000 0x40000000>; /* 1 GiB */ 205a518d637SAlexey Brodkin }; 206a518d637SAlexey Brodkin}; 207