1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2a518d637SAlexey Brodkin/* 3a518d637SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 4a518d637SAlexey Brodkin */ 5a518d637SAlexey Brodkin 6a518d637SAlexey Brodkin/* 7a518d637SAlexey Brodkin * Device Tree for ARC HS Development Kit 8a518d637SAlexey Brodkin */ 9a518d637SAlexey Brodkin/dts-v1/; 10a518d637SAlexey Brodkin 11ab8eb7dbSEugeniy Paltsev#include <dt-bindings/reset/snps,hsdk-reset.h> 12a518d637SAlexey Brodkin 13a518d637SAlexey Brodkin/ { 14a518d637SAlexey Brodkin model = "snps,hsdk"; 15a518d637SAlexey Brodkin compatible = "snps,hsdk"; 16a518d637SAlexey Brodkin 1721cee1bdSVineet Gupta #address-cells = <2>; 1821cee1bdSVineet Gupta #size-cells = <2>; 19a518d637SAlexey Brodkin 20a518d637SAlexey Brodkin chosen { 21a518d637SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 22a518d637SAlexey Brodkin }; 23a518d637SAlexey Brodkin 245c092089SAlexey Brodkin aliases { 255c092089SAlexey Brodkin ethernet = &gmac; 265c092089SAlexey Brodkin }; 275c092089SAlexey Brodkin 28a518d637SAlexey Brodkin cpus { 29a518d637SAlexey Brodkin #address-cells = <1>; 30a518d637SAlexey Brodkin #size-cells = <0>; 31a518d637SAlexey Brodkin 32a518d637SAlexey Brodkin cpu@0 { 33a518d637SAlexey Brodkin device_type = "cpu"; 34a518d637SAlexey Brodkin compatible = "snps,archs38"; 35a518d637SAlexey Brodkin reg = <0>; 36a518d637SAlexey Brodkin clocks = <&core_clk>; 37a518d637SAlexey Brodkin }; 38a518d637SAlexey Brodkin 39a518d637SAlexey Brodkin cpu@1 { 40a518d637SAlexey Brodkin device_type = "cpu"; 41a518d637SAlexey Brodkin compatible = "snps,archs38"; 42a518d637SAlexey Brodkin reg = <1>; 43a518d637SAlexey Brodkin clocks = <&core_clk>; 44a518d637SAlexey Brodkin }; 45a518d637SAlexey Brodkin 46a518d637SAlexey Brodkin cpu@2 { 47a518d637SAlexey Brodkin device_type = "cpu"; 48a518d637SAlexey Brodkin compatible = "snps,archs38"; 49a518d637SAlexey Brodkin reg = <2>; 50a518d637SAlexey Brodkin clocks = <&core_clk>; 51a518d637SAlexey Brodkin }; 52a518d637SAlexey Brodkin 53a518d637SAlexey Brodkin cpu@3 { 54a518d637SAlexey Brodkin device_type = "cpu"; 55a518d637SAlexey Brodkin compatible = "snps,archs38"; 56a518d637SAlexey Brodkin reg = <3>; 57a518d637SAlexey Brodkin clocks = <&core_clk>; 58a518d637SAlexey Brodkin }; 59a518d637SAlexey Brodkin }; 60a518d637SAlexey Brodkin 61ef833eabSEugeniy Paltsev input_clk: input-clk { 62a518d637SAlexey Brodkin #clock-cells = <0>; 63a518d637SAlexey Brodkin compatible = "fixed-clock"; 64ef833eabSEugeniy Paltsev clock-frequency = <33333333>; 65a518d637SAlexey Brodkin }; 66a518d637SAlexey Brodkin 67a518d637SAlexey Brodkin cpu_intc: cpu-interrupt-controller { 68a518d637SAlexey Brodkin compatible = "snps,archs-intc"; 69a518d637SAlexey Brodkin interrupt-controller; 70a518d637SAlexey Brodkin #interrupt-cells = <1>; 71a518d637SAlexey Brodkin }; 72a518d637SAlexey Brodkin 73a518d637SAlexey Brodkin idu_intc: idu-interrupt-controller { 74a518d637SAlexey Brodkin compatible = "snps,archs-idu-intc"; 75a518d637SAlexey Brodkin interrupt-controller; 76a518d637SAlexey Brodkin #interrupt-cells = <1>; 77a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 78a518d637SAlexey Brodkin }; 79a518d637SAlexey Brodkin 80a518d637SAlexey Brodkin arcpct: pct { 81a518d637SAlexey Brodkin compatible = "snps,archs-pct"; 82a518d637SAlexey Brodkin }; 83a518d637SAlexey Brodkin 84a518d637SAlexey Brodkin /* TIMER0 with interrupt for clockevent */ 85a518d637SAlexey Brodkin timer { 86a518d637SAlexey Brodkin compatible = "snps,arc-timer"; 87a518d637SAlexey Brodkin interrupts = <16>; 88a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 89a518d637SAlexey Brodkin clocks = <&core_clk>; 90a518d637SAlexey Brodkin }; 91a518d637SAlexey Brodkin 92a518d637SAlexey Brodkin /* 64-bit Global Free Running Counter */ 93a518d637SAlexey Brodkin gfrc { 94a518d637SAlexey Brodkin compatible = "snps,archs-timer-gfrc"; 95a518d637SAlexey Brodkin clocks = <&core_clk>; 96a518d637SAlexey Brodkin }; 97a518d637SAlexey Brodkin 98a518d637SAlexey Brodkin soc { 99a518d637SAlexey Brodkin compatible = "simple-bus"; 100a518d637SAlexey Brodkin #address-cells = <1>; 101a518d637SAlexey Brodkin #size-cells = <1>; 102a518d637SAlexey Brodkin interrupt-parent = <&idu_intc>; 103a518d637SAlexey Brodkin 10421cee1bdSVineet Gupta ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 105a518d637SAlexey Brodkin 106ab8eb7dbSEugeniy Paltsev cgu_rst: reset-controller@8a0 { 107ab8eb7dbSEugeniy Paltsev compatible = "snps,hsdk-reset"; 108ab8eb7dbSEugeniy Paltsev #reset-cells = <1>; 109ef4c54c3SAlexey Brodkin reg = <0x8a0 0x4>, <0xff0 0x4>; 110ab8eb7dbSEugeniy Paltsev }; 111ab8eb7dbSEugeniy Paltsev 112ef833eabSEugeniy Paltsev core_clk: core-clk@0 { 113ef833eabSEugeniy Paltsev compatible = "snps,hsdk-core-pll-clock"; 114ef4c54c3SAlexey Brodkin reg = <0x00 0x10>, <0x14b8 0x4>; 115ef833eabSEugeniy Paltsev #clock-cells = <0>; 116ef833eabSEugeniy Paltsev clocks = <&input_clk>; 117a08c832fSEugeniy Paltsev 118a08c832fSEugeniy Paltsev /* 119a08c832fSEugeniy Paltsev * Set initial core pll output frequency to 1GHz. 120a08c832fSEugeniy Paltsev * It will be applied at the core pll driver probing 121a08c832fSEugeniy Paltsev * on early boot. 122a08c832fSEugeniy Paltsev */ 123a08c832fSEugeniy Paltsev assigned-clocks = <&core_clk>; 124a08c832fSEugeniy Paltsev assigned-clock-rates = <1000000000>; 125ef833eabSEugeniy Paltsev }; 126ef833eabSEugeniy Paltsev 127a518d637SAlexey Brodkin serial: serial@5000 { 128a518d637SAlexey Brodkin compatible = "snps,dw-apb-uart"; 129a518d637SAlexey Brodkin reg = <0x5000 0x100>; 130a518d637SAlexey Brodkin clock-frequency = <33330000>; 131a518d637SAlexey Brodkin interrupts = <6>; 132a518d637SAlexey Brodkin baud = <115200>; 133a518d637SAlexey Brodkin reg-shift = <2>; 134a518d637SAlexey Brodkin reg-io-width = <4>; 135a518d637SAlexey Brodkin }; 136a518d637SAlexey Brodkin 137a518d637SAlexey Brodkin gmacclk: gmacclk { 138a518d637SAlexey Brodkin compatible = "fixed-clock"; 139a518d637SAlexey Brodkin clock-frequency = <400000000>; 140a518d637SAlexey Brodkin #clock-cells = <0>; 141a518d637SAlexey Brodkin }; 142a518d637SAlexey Brodkin 143a518d637SAlexey Brodkin mmcclk_ciu: mmcclk-ciu { 144a518d637SAlexey Brodkin compatible = "fixed-clock"; 1456afa3bcfSEugeniy Paltsev /* 1466afa3bcfSEugeniy Paltsev * DW sdio controller has external ciu clock divider 1476afa3bcfSEugeniy Paltsev * controlled via register in SDIO IP. Due to its 148753affbaSEugeniy Paltsev * unexpected default value (it should divide by 1 149753affbaSEugeniy Paltsev * but it divides by 8) SDIO IP uses wrong clock and 1506afa3bcfSEugeniy Paltsev * works unstable (see STAR 9001204800) 151753affbaSEugeniy Paltsev * We switched to the minimum possible value of the 152753affbaSEugeniy Paltsev * divisor (div-by-2) in HSDK platform code. 1536afa3bcfSEugeniy Paltsev * So add temporary fix and change clock frequency 154753affbaSEugeniy Paltsev * to 50000000 Hz until we fix dw sdio driver itself. 1556afa3bcfSEugeniy Paltsev */ 156753affbaSEugeniy Paltsev clock-frequency = <50000000>; 157a518d637SAlexey Brodkin #clock-cells = <0>; 158a518d637SAlexey Brodkin }; 159a518d637SAlexey Brodkin 160a518d637SAlexey Brodkin mmcclk_biu: mmcclk-biu { 161a518d637SAlexey Brodkin compatible = "fixed-clock"; 162a518d637SAlexey Brodkin clock-frequency = <400000000>; 163a518d637SAlexey Brodkin #clock-cells = <0>; 164a518d637SAlexey Brodkin }; 165a518d637SAlexey Brodkin 166b0470064SEugeniy Paltsev gpu_core_clk: gpu-core-clk { 167b0470064SEugeniy Paltsev compatible = "fixed-clock"; 168b0470064SEugeniy Paltsev clock-frequency = <400000000>; 169b0470064SEugeniy Paltsev #clock-cells = <0>; 170b0470064SEugeniy Paltsev }; 171b0470064SEugeniy Paltsev 172b0470064SEugeniy Paltsev gpu_dma_clk: gpu-dma-clk { 173b0470064SEugeniy Paltsev compatible = "fixed-clock"; 174b0470064SEugeniy Paltsev clock-frequency = <400000000>; 175b0470064SEugeniy Paltsev #clock-cells = <0>; 176b0470064SEugeniy Paltsev }; 177b0470064SEugeniy Paltsev 178b0470064SEugeniy Paltsev gpu_cfg_clk: gpu-cfg-clk { 179b0470064SEugeniy Paltsev compatible = "fixed-clock"; 180b0470064SEugeniy Paltsev clock-frequency = <200000000>; 181b0470064SEugeniy Paltsev #clock-cells = <0>; 182b0470064SEugeniy Paltsev }; 183b0470064SEugeniy Paltsev 1845d4ab8d0SEugeniy Paltsev dmac_core_clk: dmac-core-clk { 1855d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1865d4ab8d0SEugeniy Paltsev clock-frequency = <400000000>; 1875d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1885d4ab8d0SEugeniy Paltsev }; 1895d4ab8d0SEugeniy Paltsev 1905d4ab8d0SEugeniy Paltsev dmac_cfg_clk: dmac-gpu-cfg-clk { 1915d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1925d4ab8d0SEugeniy Paltsev clock-frequency = <200000000>; 1935d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1945d4ab8d0SEugeniy Paltsev }; 1955d4ab8d0SEugeniy Paltsev 1965c092089SAlexey Brodkin gmac: ethernet@8000 { 197a518d637SAlexey Brodkin #interrupt-cells = <1>; 198a518d637SAlexey Brodkin compatible = "snps,dwmac"; 199a518d637SAlexey Brodkin reg = <0x8000 0x2000>; 200a518d637SAlexey Brodkin interrupts = <10>; 201a518d637SAlexey Brodkin interrupt-names = "macirq"; 202a518d637SAlexey Brodkin phy-mode = "rgmii"; 203a518d637SAlexey Brodkin snps,pbl = <32>; 204ecc906a1SJose Abreu snps,multicast-filter-bins = <256>; 205a518d637SAlexey Brodkin clocks = <&gmacclk>; 206a518d637SAlexey Brodkin clock-names = "stmmaceth"; 207a518d637SAlexey Brodkin phy-handle = <&phy0>; 208ab8eb7dbSEugeniy Paltsev resets = <&cgu_rst HSDK_ETH_RESET>; 209ab8eb7dbSEugeniy Paltsev reset-names = "stmmaceth"; 2105c092089SAlexey Brodkin mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 211678c8110SEugeniy Paltsev dma-coherent; 212a518d637SAlexey Brodkin 2134c70850aSJose Abreu tx-fifo-depth = <4096>; 2144c70850aSJose Abreu rx-fifo-depth = <4096>; 2154c70850aSJose Abreu 216a518d637SAlexey Brodkin mdio { 217a518d637SAlexey Brodkin #address-cells = <1>; 218a518d637SAlexey Brodkin #size-cells = <0>; 219a518d637SAlexey Brodkin compatible = "snps,dwmac-mdio"; 220a518d637SAlexey Brodkin phy0: ethernet-phy@0 { 221a518d637SAlexey Brodkin reg = <0>; 222a518d637SAlexey Brodkin }; 223a518d637SAlexey Brodkin }; 224a518d637SAlexey Brodkin }; 225a518d637SAlexey Brodkin 226a518d637SAlexey Brodkin ohci@60000 { 227a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 228a518d637SAlexey Brodkin reg = <0x60000 0x100>; 229a518d637SAlexey Brodkin interrupts = <15>; 23066f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 231678c8110SEugeniy Paltsev dma-coherent; 232a518d637SAlexey Brodkin }; 233a518d637SAlexey Brodkin 234a518d637SAlexey Brodkin ehci@40000 { 235a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 236a518d637SAlexey Brodkin reg = <0x40000 0x100>; 237a518d637SAlexey Brodkin interrupts = <15>; 23866f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 239678c8110SEugeniy Paltsev dma-coherent; 240a518d637SAlexey Brodkin }; 241a518d637SAlexey Brodkin 242a518d637SAlexey Brodkin mmc@a000 { 243a518d637SAlexey Brodkin compatible = "altr,socfpga-dw-mshc"; 244a518d637SAlexey Brodkin reg = <0xa000 0x400>; 245a518d637SAlexey Brodkin num-slots = <1>; 246a518d637SAlexey Brodkin fifo-depth = <16>; 247a518d637SAlexey Brodkin card-detect-delay = <200>; 248a518d637SAlexey Brodkin clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 249a518d637SAlexey Brodkin clock-names = "biu", "ciu"; 250a518d637SAlexey Brodkin interrupts = <12>; 251a518d637SAlexey Brodkin bus-width = <4>; 252678c8110SEugeniy Paltsev dma-coherent; 253a518d637SAlexey Brodkin }; 2544592f11eSEugeniy Paltsev 255780b35b6SEugeniy Paltsev creg_gpio: gpio@14b0 { 256780b35b6SEugeniy Paltsev compatible = "snps,creg-gpio-hsdk"; 257780b35b6SEugeniy Paltsev reg = <0x14b0 0x4>; 258780b35b6SEugeniy Paltsev gpio-controller; 259780b35b6SEugeniy Paltsev #gpio-cells = <2>; 260780b35b6SEugeniy Paltsev ngpios = <2>; 261780b35b6SEugeniy Paltsev }; 262780b35b6SEugeniy Paltsev 2634592f11eSEugeniy Paltsev gpio: gpio@3000 { 2644592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio"; 2654592f11eSEugeniy Paltsev reg = <0x3000 0x20>; 2664592f11eSEugeniy Paltsev #address-cells = <1>; 2674592f11eSEugeniy Paltsev #size-cells = <0>; 2684592f11eSEugeniy Paltsev 2694592f11eSEugeniy Paltsev gpio_port_a: gpio-controller@0 { 2704592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio-port"; 2714592f11eSEugeniy Paltsev gpio-controller; 2724592f11eSEugeniy Paltsev #gpio-cells = <2>; 2734592f11eSEugeniy Paltsev snps,nr-gpios = <24>; 2744592f11eSEugeniy Paltsev reg = <0>; 2754592f11eSEugeniy Paltsev }; 2764592f11eSEugeniy Paltsev }; 2775d4ab8d0SEugeniy Paltsev 278b0470064SEugeniy Paltsev gpu_3d: gpu@90000 { 279b0470064SEugeniy Paltsev compatible = "vivante,gc"; 280b0470064SEugeniy Paltsev reg = <0x90000 0x4000>; 281b0470064SEugeniy Paltsev clocks = <&gpu_dma_clk>, 282b0470064SEugeniy Paltsev <&gpu_cfg_clk>, 283b0470064SEugeniy Paltsev <&gpu_core_clk>, 284b0470064SEugeniy Paltsev <&gpu_core_clk>; 285b0470064SEugeniy Paltsev clock-names = "bus", "reg", "core", "shader"; 286b0470064SEugeniy Paltsev interrupts = <28>; 287b0470064SEugeniy Paltsev }; 288b0470064SEugeniy Paltsev 2895d4ab8d0SEugeniy Paltsev dmac: dmac@80000 { 2905d4ab8d0SEugeniy Paltsev compatible = "snps,axi-dma-1.01a"; 2915d4ab8d0SEugeniy Paltsev reg = <0x80000 0x400>; 2925d4ab8d0SEugeniy Paltsev interrupts = <27>; 2935d4ab8d0SEugeniy Paltsev clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 2945d4ab8d0SEugeniy Paltsev clock-names = "core-clk", "cfgr-clk"; 2955d4ab8d0SEugeniy Paltsev 2965d4ab8d0SEugeniy Paltsev dma-channels = <4>; 2975d4ab8d0SEugeniy Paltsev snps,dma-masters = <2>; 2985d4ab8d0SEugeniy Paltsev snps,data-width = <3>; 2995d4ab8d0SEugeniy Paltsev snps,block-size = <4096 4096 4096 4096>; 3005d4ab8d0SEugeniy Paltsev snps,priority = <0 1 2 3>; 3015d4ab8d0SEugeniy Paltsev snps,axi-max-burst-len = <16>; 3025d4ab8d0SEugeniy Paltsev }; 303a518d637SAlexey Brodkin }; 304a518d637SAlexey Brodkin 305a518d637SAlexey Brodkin memory@80000000 { 30621cee1bdSVineet Gupta #address-cells = <2>; 30721cee1bdSVineet Gupta #size-cells = <2>; 308a518d637SAlexey Brodkin device_type = "memory"; 30921cee1bdSVineet Gupta reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 31021cee1bdSVineet Gupta /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 311a518d637SAlexey Brodkin }; 312a518d637SAlexey Brodkin}; 313