1a518d637SAlexey Brodkin/* 2a518d637SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 3a518d637SAlexey Brodkin * 4a518d637SAlexey Brodkin * This program is free software; you can redistribute it and/or modify 5a518d637SAlexey Brodkin * it under the terms of the GNU General Public License version 2 as 6a518d637SAlexey Brodkin * published by the Free Software Foundation. 7a518d637SAlexey Brodkin */ 8a518d637SAlexey Brodkin 9a518d637SAlexey Brodkin/* 10a518d637SAlexey Brodkin * Device Tree for ARC HS Development Kit 11a518d637SAlexey Brodkin */ 12a518d637SAlexey Brodkin/dts-v1/; 13a518d637SAlexey Brodkin 14a518d637SAlexey Brodkin#include <dt-bindings/net/ti-dp83867.h> 15ab8eb7dbSEugeniy Paltsev#include <dt-bindings/reset/snps,hsdk-reset.h> 16a518d637SAlexey Brodkin 17a518d637SAlexey Brodkin/ { 18a518d637SAlexey Brodkin model = "snps,hsdk"; 19a518d637SAlexey Brodkin compatible = "snps,hsdk"; 20a518d637SAlexey Brodkin 2121cee1bdSVineet Gupta #address-cells = <2>; 2221cee1bdSVineet Gupta #size-cells = <2>; 23a518d637SAlexey Brodkin 24a518d637SAlexey Brodkin chosen { 25a518d637SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 26a518d637SAlexey Brodkin }; 27a518d637SAlexey Brodkin 285c092089SAlexey Brodkin aliases { 295c092089SAlexey Brodkin ethernet = &gmac; 305c092089SAlexey Brodkin }; 315c092089SAlexey Brodkin 32a518d637SAlexey Brodkin cpus { 33a518d637SAlexey Brodkin #address-cells = <1>; 34a518d637SAlexey Brodkin #size-cells = <0>; 35a518d637SAlexey Brodkin 36a518d637SAlexey Brodkin cpu@0 { 37a518d637SAlexey Brodkin device_type = "cpu"; 38a518d637SAlexey Brodkin compatible = "snps,archs38"; 39a518d637SAlexey Brodkin reg = <0>; 40a518d637SAlexey Brodkin clocks = <&core_clk>; 41a518d637SAlexey Brodkin }; 42a518d637SAlexey Brodkin 43a518d637SAlexey Brodkin cpu@1 { 44a518d637SAlexey Brodkin device_type = "cpu"; 45a518d637SAlexey Brodkin compatible = "snps,archs38"; 46a518d637SAlexey Brodkin reg = <1>; 47a518d637SAlexey Brodkin clocks = <&core_clk>; 48a518d637SAlexey Brodkin }; 49a518d637SAlexey Brodkin 50a518d637SAlexey Brodkin cpu@2 { 51a518d637SAlexey Brodkin device_type = "cpu"; 52a518d637SAlexey Brodkin compatible = "snps,archs38"; 53a518d637SAlexey Brodkin reg = <2>; 54a518d637SAlexey Brodkin clocks = <&core_clk>; 55a518d637SAlexey Brodkin }; 56a518d637SAlexey Brodkin 57a518d637SAlexey Brodkin cpu@3 { 58a518d637SAlexey Brodkin device_type = "cpu"; 59a518d637SAlexey Brodkin compatible = "snps,archs38"; 60a518d637SAlexey Brodkin reg = <3>; 61a518d637SAlexey Brodkin clocks = <&core_clk>; 62a518d637SAlexey Brodkin }; 63a518d637SAlexey Brodkin }; 64a518d637SAlexey Brodkin 65ef833eabSEugeniy Paltsev input_clk: input-clk { 66a518d637SAlexey Brodkin #clock-cells = <0>; 67a518d637SAlexey Brodkin compatible = "fixed-clock"; 68ef833eabSEugeniy Paltsev clock-frequency = <33333333>; 69a518d637SAlexey Brodkin }; 70a518d637SAlexey Brodkin 71a518d637SAlexey Brodkin cpu_intc: cpu-interrupt-controller { 72a518d637SAlexey Brodkin compatible = "snps,archs-intc"; 73a518d637SAlexey Brodkin interrupt-controller; 74a518d637SAlexey Brodkin #interrupt-cells = <1>; 75a518d637SAlexey Brodkin }; 76a518d637SAlexey Brodkin 77a518d637SAlexey Brodkin idu_intc: idu-interrupt-controller { 78a518d637SAlexey Brodkin compatible = "snps,archs-idu-intc"; 79a518d637SAlexey Brodkin interrupt-controller; 80a518d637SAlexey Brodkin #interrupt-cells = <1>; 81a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 82a518d637SAlexey Brodkin }; 83a518d637SAlexey Brodkin 84a518d637SAlexey Brodkin arcpct: pct { 85a518d637SAlexey Brodkin compatible = "snps,archs-pct"; 86a518d637SAlexey Brodkin }; 87a518d637SAlexey Brodkin 88a518d637SAlexey Brodkin /* TIMER0 with interrupt for clockevent */ 89a518d637SAlexey Brodkin timer { 90a518d637SAlexey Brodkin compatible = "snps,arc-timer"; 91a518d637SAlexey Brodkin interrupts = <16>; 92a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 93a518d637SAlexey Brodkin clocks = <&core_clk>; 94a518d637SAlexey Brodkin }; 95a518d637SAlexey Brodkin 96a518d637SAlexey Brodkin /* 64-bit Global Free Running Counter */ 97a518d637SAlexey Brodkin gfrc { 98a518d637SAlexey Brodkin compatible = "snps,archs-timer-gfrc"; 99a518d637SAlexey Brodkin clocks = <&core_clk>; 100a518d637SAlexey Brodkin }; 101a518d637SAlexey Brodkin 102a518d637SAlexey Brodkin soc { 103a518d637SAlexey Brodkin compatible = "simple-bus"; 104a518d637SAlexey Brodkin #address-cells = <1>; 105a518d637SAlexey Brodkin #size-cells = <1>; 106a518d637SAlexey Brodkin interrupt-parent = <&idu_intc>; 107a518d637SAlexey Brodkin 10821cee1bdSVineet Gupta ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 109a518d637SAlexey Brodkin 110ab8eb7dbSEugeniy Paltsev cgu_rst: reset-controller@8a0 { 111ab8eb7dbSEugeniy Paltsev compatible = "snps,hsdk-reset"; 112ab8eb7dbSEugeniy Paltsev #reset-cells = <1>; 113ef4c54c3SAlexey Brodkin reg = <0x8a0 0x4>, <0xff0 0x4>; 114ab8eb7dbSEugeniy Paltsev }; 115ab8eb7dbSEugeniy Paltsev 116ef833eabSEugeniy Paltsev core_clk: core-clk@0 { 117ef833eabSEugeniy Paltsev compatible = "snps,hsdk-core-pll-clock"; 118ef4c54c3SAlexey Brodkin reg = <0x00 0x10>, <0x14b8 0x4>; 119ef833eabSEugeniy Paltsev #clock-cells = <0>; 120ef833eabSEugeniy Paltsev clocks = <&input_clk>; 121a08c832fSEugeniy Paltsev 122a08c832fSEugeniy Paltsev /* 123a08c832fSEugeniy Paltsev * Set initial core pll output frequency to 1GHz. 124a08c832fSEugeniy Paltsev * It will be applied at the core pll driver probing 125a08c832fSEugeniy Paltsev * on early boot. 126a08c832fSEugeniy Paltsev */ 127a08c832fSEugeniy Paltsev assigned-clocks = <&core_clk>; 128a08c832fSEugeniy Paltsev assigned-clock-rates = <1000000000>; 129ef833eabSEugeniy Paltsev }; 130ef833eabSEugeniy Paltsev 131a518d637SAlexey Brodkin serial: serial@5000 { 132a518d637SAlexey Brodkin compatible = "snps,dw-apb-uart"; 133a518d637SAlexey Brodkin reg = <0x5000 0x100>; 134a518d637SAlexey Brodkin clock-frequency = <33330000>; 135a518d637SAlexey Brodkin interrupts = <6>; 136a518d637SAlexey Brodkin baud = <115200>; 137a518d637SAlexey Brodkin reg-shift = <2>; 138a518d637SAlexey Brodkin reg-io-width = <4>; 139a518d637SAlexey Brodkin }; 140a518d637SAlexey Brodkin 141a518d637SAlexey Brodkin gmacclk: gmacclk { 142a518d637SAlexey Brodkin compatible = "fixed-clock"; 143a518d637SAlexey Brodkin clock-frequency = <400000000>; 144a518d637SAlexey Brodkin #clock-cells = <0>; 145a518d637SAlexey Brodkin }; 146a518d637SAlexey Brodkin 147a518d637SAlexey Brodkin mmcclk_ciu: mmcclk-ciu { 148a518d637SAlexey Brodkin compatible = "fixed-clock"; 1496afa3bcfSEugeniy Paltsev /* 1506afa3bcfSEugeniy Paltsev * DW sdio controller has external ciu clock divider 1516afa3bcfSEugeniy Paltsev * controlled via register in SDIO IP. Due to its 152753affbaSEugeniy Paltsev * unexpected default value (it should divide by 1 153753affbaSEugeniy Paltsev * but it divides by 8) SDIO IP uses wrong clock and 1546afa3bcfSEugeniy Paltsev * works unstable (see STAR 9001204800) 155753affbaSEugeniy Paltsev * We switched to the minimum possible value of the 156753affbaSEugeniy Paltsev * divisor (div-by-2) in HSDK platform code. 1576afa3bcfSEugeniy Paltsev * So add temporary fix and change clock frequency 158753affbaSEugeniy Paltsev * to 50000000 Hz until we fix dw sdio driver itself. 1596afa3bcfSEugeniy Paltsev */ 160753affbaSEugeniy Paltsev clock-frequency = <50000000>; 161a518d637SAlexey Brodkin #clock-cells = <0>; 162a518d637SAlexey Brodkin }; 163a518d637SAlexey Brodkin 164a518d637SAlexey Brodkin mmcclk_biu: mmcclk-biu { 165a518d637SAlexey Brodkin compatible = "fixed-clock"; 166a518d637SAlexey Brodkin clock-frequency = <400000000>; 167a518d637SAlexey Brodkin #clock-cells = <0>; 168a518d637SAlexey Brodkin }; 169a518d637SAlexey Brodkin 170b0470064SEugeniy Paltsev gpu_core_clk: gpu-core-clk { 171b0470064SEugeniy Paltsev compatible = "fixed-clock"; 172b0470064SEugeniy Paltsev clock-frequency = <400000000>; 173b0470064SEugeniy Paltsev #clock-cells = <0>; 174b0470064SEugeniy Paltsev }; 175b0470064SEugeniy Paltsev 176b0470064SEugeniy Paltsev gpu_dma_clk: gpu-dma-clk { 177b0470064SEugeniy Paltsev compatible = "fixed-clock"; 178b0470064SEugeniy Paltsev clock-frequency = <400000000>; 179b0470064SEugeniy Paltsev #clock-cells = <0>; 180b0470064SEugeniy Paltsev }; 181b0470064SEugeniy Paltsev 182b0470064SEugeniy Paltsev gpu_cfg_clk: gpu-cfg-clk { 183b0470064SEugeniy Paltsev compatible = "fixed-clock"; 184b0470064SEugeniy Paltsev clock-frequency = <200000000>; 185b0470064SEugeniy Paltsev #clock-cells = <0>; 186b0470064SEugeniy Paltsev }; 187b0470064SEugeniy Paltsev 1885d4ab8d0SEugeniy Paltsev dmac_core_clk: dmac-core-clk { 1895d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1905d4ab8d0SEugeniy Paltsev clock-frequency = <400000000>; 1915d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1925d4ab8d0SEugeniy Paltsev }; 1935d4ab8d0SEugeniy Paltsev 1945d4ab8d0SEugeniy Paltsev dmac_cfg_clk: dmac-gpu-cfg-clk { 1955d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1965d4ab8d0SEugeniy Paltsev clock-frequency = <200000000>; 1975d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1985d4ab8d0SEugeniy Paltsev }; 1995d4ab8d0SEugeniy Paltsev 2005c092089SAlexey Brodkin gmac: ethernet@8000 { 201a518d637SAlexey Brodkin #interrupt-cells = <1>; 202a518d637SAlexey Brodkin compatible = "snps,dwmac"; 203a518d637SAlexey Brodkin reg = <0x8000 0x2000>; 204a518d637SAlexey Brodkin interrupts = <10>; 205a518d637SAlexey Brodkin interrupt-names = "macirq"; 206a518d637SAlexey Brodkin phy-mode = "rgmii"; 207a518d637SAlexey Brodkin snps,pbl = <32>; 208ecc906a1SJose Abreu snps,multicast-filter-bins = <256>; 209a518d637SAlexey Brodkin clocks = <&gmacclk>; 210a518d637SAlexey Brodkin clock-names = "stmmaceth"; 211a518d637SAlexey Brodkin phy-handle = <&phy0>; 212ab8eb7dbSEugeniy Paltsev resets = <&cgu_rst HSDK_ETH_RESET>; 213ab8eb7dbSEugeniy Paltsev reset-names = "stmmaceth"; 2145c092089SAlexey Brodkin mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 215678c8110SEugeniy Paltsev dma-coherent; 216a518d637SAlexey Brodkin 2174c70850aSJose Abreu tx-fifo-depth = <4096>; 2184c70850aSJose Abreu rx-fifo-depth = <4096>; 2194c70850aSJose Abreu 220a518d637SAlexey Brodkin mdio { 221a518d637SAlexey Brodkin #address-cells = <1>; 222a518d637SAlexey Brodkin #size-cells = <0>; 223a518d637SAlexey Brodkin compatible = "snps,dwmac-mdio"; 224a518d637SAlexey Brodkin phy0: ethernet-phy@0 { 225a518d637SAlexey Brodkin reg = <0>; 226a518d637SAlexey Brodkin ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 227a518d637SAlexey Brodkin ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 228a518d637SAlexey Brodkin ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 229a518d637SAlexey Brodkin }; 230a518d637SAlexey Brodkin }; 231a518d637SAlexey Brodkin }; 232a518d637SAlexey Brodkin 233a518d637SAlexey Brodkin ohci@60000 { 234a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 235a518d637SAlexey Brodkin reg = <0x60000 0x100>; 236a518d637SAlexey Brodkin interrupts = <15>; 23766f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 238678c8110SEugeniy Paltsev dma-coherent; 239a518d637SAlexey Brodkin }; 240a518d637SAlexey Brodkin 241a518d637SAlexey Brodkin ehci@40000 { 242a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 243a518d637SAlexey Brodkin reg = <0x40000 0x100>; 244a518d637SAlexey Brodkin interrupts = <15>; 24566f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 246678c8110SEugeniy Paltsev dma-coherent; 247a518d637SAlexey Brodkin }; 248a518d637SAlexey Brodkin 249a518d637SAlexey Brodkin mmc@a000 { 250a518d637SAlexey Brodkin compatible = "altr,socfpga-dw-mshc"; 251a518d637SAlexey Brodkin reg = <0xa000 0x400>; 252a518d637SAlexey Brodkin num-slots = <1>; 253a518d637SAlexey Brodkin fifo-depth = <16>; 254a518d637SAlexey Brodkin card-detect-delay = <200>; 255a518d637SAlexey Brodkin clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 256a518d637SAlexey Brodkin clock-names = "biu", "ciu"; 257a518d637SAlexey Brodkin interrupts = <12>; 258a518d637SAlexey Brodkin bus-width = <4>; 259678c8110SEugeniy Paltsev dma-coherent; 260a518d637SAlexey Brodkin }; 2614592f11eSEugeniy Paltsev 262780b35b6SEugeniy Paltsev creg_gpio: gpio@14b0 { 263780b35b6SEugeniy Paltsev compatible = "snps,creg-gpio-hsdk"; 264780b35b6SEugeniy Paltsev reg = <0x14b0 0x4>; 265780b35b6SEugeniy Paltsev gpio-controller; 266780b35b6SEugeniy Paltsev #gpio-cells = <2>; 267780b35b6SEugeniy Paltsev ngpios = <2>; 268780b35b6SEugeniy Paltsev }; 269780b35b6SEugeniy Paltsev 2704592f11eSEugeniy Paltsev gpio: gpio@3000 { 2714592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio"; 2724592f11eSEugeniy Paltsev reg = <0x3000 0x20>; 2734592f11eSEugeniy Paltsev #address-cells = <1>; 2744592f11eSEugeniy Paltsev #size-cells = <0>; 2754592f11eSEugeniy Paltsev 2764592f11eSEugeniy Paltsev gpio_port_a: gpio-controller@0 { 2774592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio-port"; 2784592f11eSEugeniy Paltsev gpio-controller; 2794592f11eSEugeniy Paltsev #gpio-cells = <2>; 2804592f11eSEugeniy Paltsev snps,nr-gpios = <24>; 2814592f11eSEugeniy Paltsev reg = <0>; 2824592f11eSEugeniy Paltsev }; 2834592f11eSEugeniy Paltsev }; 2845d4ab8d0SEugeniy Paltsev 285b0470064SEugeniy Paltsev gpu_3d: gpu@90000 { 286b0470064SEugeniy Paltsev compatible = "vivante,gc"; 287b0470064SEugeniy Paltsev reg = <0x90000 0x4000>; 288b0470064SEugeniy Paltsev clocks = <&gpu_dma_clk>, 289b0470064SEugeniy Paltsev <&gpu_cfg_clk>, 290b0470064SEugeniy Paltsev <&gpu_core_clk>, 291b0470064SEugeniy Paltsev <&gpu_core_clk>; 292b0470064SEugeniy Paltsev clock-names = "bus", "reg", "core", "shader"; 293b0470064SEugeniy Paltsev interrupts = <28>; 294b0470064SEugeniy Paltsev }; 295b0470064SEugeniy Paltsev 2965d4ab8d0SEugeniy Paltsev dmac: dmac@80000 { 2975d4ab8d0SEugeniy Paltsev compatible = "snps,axi-dma-1.01a"; 2985d4ab8d0SEugeniy Paltsev reg = <0x80000 0x400>; 2995d4ab8d0SEugeniy Paltsev interrupts = <27>; 3005d4ab8d0SEugeniy Paltsev clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 3015d4ab8d0SEugeniy Paltsev clock-names = "core-clk", "cfgr-clk"; 3025d4ab8d0SEugeniy Paltsev 3035d4ab8d0SEugeniy Paltsev dma-channels = <4>; 3045d4ab8d0SEugeniy Paltsev snps,dma-masters = <2>; 3055d4ab8d0SEugeniy Paltsev snps,data-width = <3>; 3065d4ab8d0SEugeniy Paltsev snps,block-size = <4096 4096 4096 4096>; 3075d4ab8d0SEugeniy Paltsev snps,priority = <0 1 2 3>; 3085d4ab8d0SEugeniy Paltsev snps,axi-max-burst-len = <16>; 3095d4ab8d0SEugeniy Paltsev }; 310a518d637SAlexey Brodkin }; 311a518d637SAlexey Brodkin 312a518d637SAlexey Brodkin memory@80000000 { 31321cee1bdSVineet Gupta #address-cells = <2>; 31421cee1bdSVineet Gupta #size-cells = <2>; 315a518d637SAlexey Brodkin device_type = "memory"; 31621cee1bdSVineet Gupta reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 31721cee1bdSVineet Gupta /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 318a518d637SAlexey Brodkin }; 319a518d637SAlexey Brodkin}; 320