1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2a518d637SAlexey Brodkin/* 3a518d637SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 4a518d637SAlexey Brodkin */ 5a518d637SAlexey Brodkin 6a518d637SAlexey Brodkin/* 7a518d637SAlexey Brodkin * Device Tree for ARC HS Development Kit 8a518d637SAlexey Brodkin */ 9a518d637SAlexey Brodkin/dts-v1/; 10a518d637SAlexey Brodkin 11aab128d0SEugeniy Paltsev#include <dt-bindings/gpio/gpio.h> 12ab8eb7dbSEugeniy Paltsev#include <dt-bindings/reset/snps,hsdk-reset.h> 13a518d637SAlexey Brodkin 14a518d637SAlexey Brodkin/ { 15a518d637SAlexey Brodkin model = "snps,hsdk"; 16a518d637SAlexey Brodkin compatible = "snps,hsdk"; 17a518d637SAlexey Brodkin 1821cee1bdSVineet Gupta #address-cells = <2>; 1921cee1bdSVineet Gupta #size-cells = <2>; 20a518d637SAlexey Brodkin 21a518d637SAlexey Brodkin chosen { 22a518d637SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 23a518d637SAlexey Brodkin }; 24a518d637SAlexey Brodkin 255c092089SAlexey Brodkin aliases { 265c092089SAlexey Brodkin ethernet = &gmac; 275c092089SAlexey Brodkin }; 285c092089SAlexey Brodkin 29a518d637SAlexey Brodkin cpus { 30a518d637SAlexey Brodkin #address-cells = <1>; 31a518d637SAlexey Brodkin #size-cells = <0>; 32a518d637SAlexey Brodkin 33a518d637SAlexey Brodkin cpu@0 { 34a518d637SAlexey Brodkin device_type = "cpu"; 35a518d637SAlexey Brodkin compatible = "snps,archs38"; 36a518d637SAlexey Brodkin reg = <0>; 37a518d637SAlexey Brodkin clocks = <&core_clk>; 38a518d637SAlexey Brodkin }; 39a518d637SAlexey Brodkin 40a518d637SAlexey Brodkin cpu@1 { 41a518d637SAlexey Brodkin device_type = "cpu"; 42a518d637SAlexey Brodkin compatible = "snps,archs38"; 43a518d637SAlexey Brodkin reg = <1>; 44a518d637SAlexey Brodkin clocks = <&core_clk>; 45a518d637SAlexey Brodkin }; 46a518d637SAlexey Brodkin 47a518d637SAlexey Brodkin cpu@2 { 48a518d637SAlexey Brodkin device_type = "cpu"; 49a518d637SAlexey Brodkin compatible = "snps,archs38"; 50a518d637SAlexey Brodkin reg = <2>; 51a518d637SAlexey Brodkin clocks = <&core_clk>; 52a518d637SAlexey Brodkin }; 53a518d637SAlexey Brodkin 54a518d637SAlexey Brodkin cpu@3 { 55a518d637SAlexey Brodkin device_type = "cpu"; 56a518d637SAlexey Brodkin compatible = "snps,archs38"; 57a518d637SAlexey Brodkin reg = <3>; 58a518d637SAlexey Brodkin clocks = <&core_clk>; 59a518d637SAlexey Brodkin }; 60a518d637SAlexey Brodkin }; 61a518d637SAlexey Brodkin 62ef833eabSEugeniy Paltsev input_clk: input-clk { 63a518d637SAlexey Brodkin #clock-cells = <0>; 64a518d637SAlexey Brodkin compatible = "fixed-clock"; 65ef833eabSEugeniy Paltsev clock-frequency = <33333333>; 66a518d637SAlexey Brodkin }; 67a518d637SAlexey Brodkin 68ab563bf5SEugeniy Paltsev reg_5v0: regulator-5v0 { 69ab563bf5SEugeniy Paltsev compatible = "regulator-fixed"; 70ab563bf5SEugeniy Paltsev 71ab563bf5SEugeniy Paltsev regulator-name = "5v0-supply"; 72ab563bf5SEugeniy Paltsev regulator-min-microvolt = <5000000>; 73ab563bf5SEugeniy Paltsev regulator-max-microvolt = <5000000>; 74ab563bf5SEugeniy Paltsev }; 75ab563bf5SEugeniy Paltsev 76a518d637SAlexey Brodkin cpu_intc: cpu-interrupt-controller { 77a518d637SAlexey Brodkin compatible = "snps,archs-intc"; 78a518d637SAlexey Brodkin interrupt-controller; 79a518d637SAlexey Brodkin #interrupt-cells = <1>; 80a518d637SAlexey Brodkin }; 81a518d637SAlexey Brodkin 82a518d637SAlexey Brodkin idu_intc: idu-interrupt-controller { 83a518d637SAlexey Brodkin compatible = "snps,archs-idu-intc"; 84a518d637SAlexey Brodkin interrupt-controller; 85a518d637SAlexey Brodkin #interrupt-cells = <1>; 86a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 87a518d637SAlexey Brodkin }; 88a518d637SAlexey Brodkin 89a518d637SAlexey Brodkin arcpct: pct { 90a518d637SAlexey Brodkin compatible = "snps,archs-pct"; 91a518d637SAlexey Brodkin }; 92a518d637SAlexey Brodkin 93a518d637SAlexey Brodkin /* TIMER0 with interrupt for clockevent */ 94a518d637SAlexey Brodkin timer { 95a518d637SAlexey Brodkin compatible = "snps,arc-timer"; 96a518d637SAlexey Brodkin interrupts = <16>; 97a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 98a518d637SAlexey Brodkin clocks = <&core_clk>; 99a518d637SAlexey Brodkin }; 100a518d637SAlexey Brodkin 101a518d637SAlexey Brodkin /* 64-bit Global Free Running Counter */ 102a518d637SAlexey Brodkin gfrc { 103a518d637SAlexey Brodkin compatible = "snps,archs-timer-gfrc"; 104a518d637SAlexey Brodkin clocks = <&core_clk>; 105a518d637SAlexey Brodkin }; 106a518d637SAlexey Brodkin 107a518d637SAlexey Brodkin soc { 108a518d637SAlexey Brodkin compatible = "simple-bus"; 109a518d637SAlexey Brodkin #address-cells = <1>; 110a518d637SAlexey Brodkin #size-cells = <1>; 111a518d637SAlexey Brodkin interrupt-parent = <&idu_intc>; 112a518d637SAlexey Brodkin 11321cee1bdSVineet Gupta ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 114a518d637SAlexey Brodkin 115ab8eb7dbSEugeniy Paltsev cgu_rst: reset-controller@8a0 { 116ab8eb7dbSEugeniy Paltsev compatible = "snps,hsdk-reset"; 117ab8eb7dbSEugeniy Paltsev #reset-cells = <1>; 118ef4c54c3SAlexey Brodkin reg = <0x8a0 0x4>, <0xff0 0x4>; 119ab8eb7dbSEugeniy Paltsev }; 120ab8eb7dbSEugeniy Paltsev 121ef833eabSEugeniy Paltsev core_clk: core-clk@0 { 122ef833eabSEugeniy Paltsev compatible = "snps,hsdk-core-pll-clock"; 123ef4c54c3SAlexey Brodkin reg = <0x00 0x10>, <0x14b8 0x4>; 124ef833eabSEugeniy Paltsev #clock-cells = <0>; 125ef833eabSEugeniy Paltsev clocks = <&input_clk>; 126a08c832fSEugeniy Paltsev 127a08c832fSEugeniy Paltsev /* 128a08c832fSEugeniy Paltsev * Set initial core pll output frequency to 1GHz. 129a08c832fSEugeniy Paltsev * It will be applied at the core pll driver probing 130a08c832fSEugeniy Paltsev * on early boot. 131a08c832fSEugeniy Paltsev */ 132a08c832fSEugeniy Paltsev assigned-clocks = <&core_clk>; 133a08c832fSEugeniy Paltsev assigned-clock-rates = <1000000000>; 134ef833eabSEugeniy Paltsev }; 135ef833eabSEugeniy Paltsev 136a518d637SAlexey Brodkin serial: serial@5000 { 137a518d637SAlexey Brodkin compatible = "snps,dw-apb-uart"; 138a518d637SAlexey Brodkin reg = <0x5000 0x100>; 139a518d637SAlexey Brodkin clock-frequency = <33330000>; 140a518d637SAlexey Brodkin interrupts = <6>; 141a518d637SAlexey Brodkin baud = <115200>; 142a518d637SAlexey Brodkin reg-shift = <2>; 143a518d637SAlexey Brodkin reg-io-width = <4>; 144a518d637SAlexey Brodkin }; 145a518d637SAlexey Brodkin 146a518d637SAlexey Brodkin gmacclk: gmacclk { 147a518d637SAlexey Brodkin compatible = "fixed-clock"; 148a518d637SAlexey Brodkin clock-frequency = <400000000>; 149a518d637SAlexey Brodkin #clock-cells = <0>; 150a518d637SAlexey Brodkin }; 151a518d637SAlexey Brodkin 152a518d637SAlexey Brodkin mmcclk_ciu: mmcclk-ciu { 153a518d637SAlexey Brodkin compatible = "fixed-clock"; 1546afa3bcfSEugeniy Paltsev /* 1556afa3bcfSEugeniy Paltsev * DW sdio controller has external ciu clock divider 1566afa3bcfSEugeniy Paltsev * controlled via register in SDIO IP. Due to its 157753affbaSEugeniy Paltsev * unexpected default value (it should divide by 1 158753affbaSEugeniy Paltsev * but it divides by 8) SDIO IP uses wrong clock and 1596afa3bcfSEugeniy Paltsev * works unstable (see STAR 9001204800) 160753affbaSEugeniy Paltsev * We switched to the minimum possible value of the 161753affbaSEugeniy Paltsev * divisor (div-by-2) in HSDK platform code. 1626afa3bcfSEugeniy Paltsev * So add temporary fix and change clock frequency 163753affbaSEugeniy Paltsev * to 50000000 Hz until we fix dw sdio driver itself. 1646afa3bcfSEugeniy Paltsev */ 165753affbaSEugeniy Paltsev clock-frequency = <50000000>; 166a518d637SAlexey Brodkin #clock-cells = <0>; 167a518d637SAlexey Brodkin }; 168a518d637SAlexey Brodkin 169a518d637SAlexey Brodkin mmcclk_biu: mmcclk-biu { 170a518d637SAlexey Brodkin compatible = "fixed-clock"; 171a518d637SAlexey Brodkin clock-frequency = <400000000>; 172a518d637SAlexey Brodkin #clock-cells = <0>; 173a518d637SAlexey Brodkin }; 174a518d637SAlexey Brodkin 175b0470064SEugeniy Paltsev gpu_core_clk: gpu-core-clk { 176b0470064SEugeniy Paltsev compatible = "fixed-clock"; 177b0470064SEugeniy Paltsev clock-frequency = <400000000>; 178b0470064SEugeniy Paltsev #clock-cells = <0>; 179b0470064SEugeniy Paltsev }; 180b0470064SEugeniy Paltsev 181b0470064SEugeniy Paltsev gpu_dma_clk: gpu-dma-clk { 182b0470064SEugeniy Paltsev compatible = "fixed-clock"; 183b0470064SEugeniy Paltsev clock-frequency = <400000000>; 184b0470064SEugeniy Paltsev #clock-cells = <0>; 185b0470064SEugeniy Paltsev }; 186b0470064SEugeniy Paltsev 187b0470064SEugeniy Paltsev gpu_cfg_clk: gpu-cfg-clk { 188b0470064SEugeniy Paltsev compatible = "fixed-clock"; 189b0470064SEugeniy Paltsev clock-frequency = <200000000>; 190b0470064SEugeniy Paltsev #clock-cells = <0>; 191b0470064SEugeniy Paltsev }; 192b0470064SEugeniy Paltsev 1935d4ab8d0SEugeniy Paltsev dmac_core_clk: dmac-core-clk { 1945d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1955d4ab8d0SEugeniy Paltsev clock-frequency = <400000000>; 1965d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1975d4ab8d0SEugeniy Paltsev }; 1985d4ab8d0SEugeniy Paltsev 1995d4ab8d0SEugeniy Paltsev dmac_cfg_clk: dmac-gpu-cfg-clk { 2005d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 2015d4ab8d0SEugeniy Paltsev clock-frequency = <200000000>; 2025d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 2035d4ab8d0SEugeniy Paltsev }; 2045d4ab8d0SEugeniy Paltsev 2055c092089SAlexey Brodkin gmac: ethernet@8000 { 206a518d637SAlexey Brodkin #interrupt-cells = <1>; 207a518d637SAlexey Brodkin compatible = "snps,dwmac"; 208a518d637SAlexey Brodkin reg = <0x8000 0x2000>; 209a518d637SAlexey Brodkin interrupts = <10>; 210a518d637SAlexey Brodkin interrupt-names = "macirq"; 211a518d637SAlexey Brodkin phy-mode = "rgmii"; 212a518d637SAlexey Brodkin snps,pbl = <32>; 213ecc906a1SJose Abreu snps,multicast-filter-bins = <256>; 214a518d637SAlexey Brodkin clocks = <&gmacclk>; 215a518d637SAlexey Brodkin clock-names = "stmmaceth"; 216a518d637SAlexey Brodkin phy-handle = <&phy0>; 217ab8eb7dbSEugeniy Paltsev resets = <&cgu_rst HSDK_ETH_RESET>; 218ab8eb7dbSEugeniy Paltsev reset-names = "stmmaceth"; 2195c092089SAlexey Brodkin mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 220678c8110SEugeniy Paltsev dma-coherent; 221a518d637SAlexey Brodkin 2224c70850aSJose Abreu tx-fifo-depth = <4096>; 2234c70850aSJose Abreu rx-fifo-depth = <4096>; 2244c70850aSJose Abreu 225a518d637SAlexey Brodkin mdio { 226a518d637SAlexey Brodkin #address-cells = <1>; 227a518d637SAlexey Brodkin #size-cells = <0>; 228a518d637SAlexey Brodkin compatible = "snps,dwmac-mdio"; 229a518d637SAlexey Brodkin phy0: ethernet-phy@0 { 230a518d637SAlexey Brodkin reg = <0>; 231a518d637SAlexey Brodkin }; 232a518d637SAlexey Brodkin }; 233a518d637SAlexey Brodkin }; 234a518d637SAlexey Brodkin 235a518d637SAlexey Brodkin ohci@60000 { 236a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 237a518d637SAlexey Brodkin reg = <0x60000 0x100>; 238a518d637SAlexey Brodkin interrupts = <15>; 23966f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 240678c8110SEugeniy Paltsev dma-coherent; 241a518d637SAlexey Brodkin }; 242a518d637SAlexey Brodkin 243a518d637SAlexey Brodkin ehci@40000 { 244a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 245a518d637SAlexey Brodkin reg = <0x40000 0x100>; 246a518d637SAlexey Brodkin interrupts = <15>; 24766f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 248678c8110SEugeniy Paltsev dma-coherent; 249a518d637SAlexey Brodkin }; 250a518d637SAlexey Brodkin 251a518d637SAlexey Brodkin mmc@a000 { 252a518d637SAlexey Brodkin compatible = "altr,socfpga-dw-mshc"; 253a518d637SAlexey Brodkin reg = <0xa000 0x400>; 254a518d637SAlexey Brodkin num-slots = <1>; 255a518d637SAlexey Brodkin fifo-depth = <16>; 256a518d637SAlexey Brodkin card-detect-delay = <200>; 257a518d637SAlexey Brodkin clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 258a518d637SAlexey Brodkin clock-names = "biu", "ciu"; 259a518d637SAlexey Brodkin interrupts = <12>; 260a518d637SAlexey Brodkin bus-width = <4>; 261678c8110SEugeniy Paltsev dma-coherent; 262a518d637SAlexey Brodkin }; 2634592f11eSEugeniy Paltsev 264aab128d0SEugeniy Paltsev spi0: spi@20000 { 265aab128d0SEugeniy Paltsev compatible = "snps,dw-apb-ssi"; 266aab128d0SEugeniy Paltsev reg = <0x20000 0x100>; 267aab128d0SEugeniy Paltsev #address-cells = <1>; 268aab128d0SEugeniy Paltsev #size-cells = <0>; 269aab128d0SEugeniy Paltsev interrupts = <16>; 270aab128d0SEugeniy Paltsev num-cs = <2>; 271aab128d0SEugeniy Paltsev reg-io-width = <4>; 272aab128d0SEugeniy Paltsev clocks = <&input_clk>; 273aab128d0SEugeniy Paltsev cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, 274aab128d0SEugeniy Paltsev <&creg_gpio 1 GPIO_ACTIVE_LOW>; 2758ca8fa7fSEugeniy Paltsev 2768ca8fa7fSEugeniy Paltsev spi-flash@0 { 2778ca8fa7fSEugeniy Paltsev compatible = "sst26wf016b", "jedec,spi-nor"; 2788ca8fa7fSEugeniy Paltsev reg = <0>; 2798ca8fa7fSEugeniy Paltsev #address-cells = <1>; 2808ca8fa7fSEugeniy Paltsev #size-cells = <1>; 2818ca8fa7fSEugeniy Paltsev spi-max-frequency = <4000000>; 2828ca8fa7fSEugeniy Paltsev }; 283ab563bf5SEugeniy Paltsev 284ab563bf5SEugeniy Paltsev adc@1 { 285ab563bf5SEugeniy Paltsev compatible = "ti,adc108s102"; 286ab563bf5SEugeniy Paltsev reg = <1>; 287ab563bf5SEugeniy Paltsev vref-supply = <®_5v0>; 288ab563bf5SEugeniy Paltsev spi-max-frequency = <1000000>; 289ab563bf5SEugeniy Paltsev }; 290aab128d0SEugeniy Paltsev }; 291aab128d0SEugeniy Paltsev 292780b35b6SEugeniy Paltsev creg_gpio: gpio@14b0 { 293780b35b6SEugeniy Paltsev compatible = "snps,creg-gpio-hsdk"; 294780b35b6SEugeniy Paltsev reg = <0x14b0 0x4>; 295780b35b6SEugeniy Paltsev gpio-controller; 296780b35b6SEugeniy Paltsev #gpio-cells = <2>; 297780b35b6SEugeniy Paltsev ngpios = <2>; 298780b35b6SEugeniy Paltsev }; 299780b35b6SEugeniy Paltsev 3004592f11eSEugeniy Paltsev gpio: gpio@3000 { 3014592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio"; 3024592f11eSEugeniy Paltsev reg = <0x3000 0x20>; 3034592f11eSEugeniy Paltsev #address-cells = <1>; 3044592f11eSEugeniy Paltsev #size-cells = <0>; 3054592f11eSEugeniy Paltsev 3064592f11eSEugeniy Paltsev gpio_port_a: gpio-controller@0 { 3074592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio-port"; 3084592f11eSEugeniy Paltsev gpio-controller; 3094592f11eSEugeniy Paltsev #gpio-cells = <2>; 3104592f11eSEugeniy Paltsev snps,nr-gpios = <24>; 3114592f11eSEugeniy Paltsev reg = <0>; 3124592f11eSEugeniy Paltsev }; 3134592f11eSEugeniy Paltsev }; 3145d4ab8d0SEugeniy Paltsev 315b0470064SEugeniy Paltsev gpu_3d: gpu@90000 { 316b0470064SEugeniy Paltsev compatible = "vivante,gc"; 317b0470064SEugeniy Paltsev reg = <0x90000 0x4000>; 318b0470064SEugeniy Paltsev clocks = <&gpu_dma_clk>, 319b0470064SEugeniy Paltsev <&gpu_cfg_clk>, 320b0470064SEugeniy Paltsev <&gpu_core_clk>, 321b0470064SEugeniy Paltsev <&gpu_core_clk>; 322b0470064SEugeniy Paltsev clock-names = "bus", "reg", "core", "shader"; 323b0470064SEugeniy Paltsev interrupts = <28>; 324b0470064SEugeniy Paltsev }; 325b0470064SEugeniy Paltsev 3265d4ab8d0SEugeniy Paltsev dmac: dmac@80000 { 3275d4ab8d0SEugeniy Paltsev compatible = "snps,axi-dma-1.01a"; 3285d4ab8d0SEugeniy Paltsev reg = <0x80000 0x400>; 3295d4ab8d0SEugeniy Paltsev interrupts = <27>; 3305d4ab8d0SEugeniy Paltsev clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 3315d4ab8d0SEugeniy Paltsev clock-names = "core-clk", "cfgr-clk"; 3325d4ab8d0SEugeniy Paltsev 3335d4ab8d0SEugeniy Paltsev dma-channels = <4>; 3345d4ab8d0SEugeniy Paltsev snps,dma-masters = <2>; 3355d4ab8d0SEugeniy Paltsev snps,data-width = <3>; 3365d4ab8d0SEugeniy Paltsev snps,block-size = <4096 4096 4096 4096>; 3375d4ab8d0SEugeniy Paltsev snps,priority = <0 1 2 3>; 3385d4ab8d0SEugeniy Paltsev snps,axi-max-burst-len = <16>; 3395d4ab8d0SEugeniy Paltsev }; 340a518d637SAlexey Brodkin }; 341a518d637SAlexey Brodkin 342a518d637SAlexey Brodkin memory@80000000 { 34321cee1bdSVineet Gupta #address-cells = <2>; 34421cee1bdSVineet Gupta #size-cells = <2>; 345a518d637SAlexey Brodkin device_type = "memory"; 34621cee1bdSVineet Gupta reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 34721cee1bdSVineet Gupta /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 348a518d637SAlexey Brodkin }; 349a518d637SAlexey Brodkin}; 350