1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2a518d637SAlexey Brodkin/* 3a518d637SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 4a518d637SAlexey Brodkin */ 5a518d637SAlexey Brodkin 6a518d637SAlexey Brodkin/* 7a518d637SAlexey Brodkin * Device Tree for ARC HS Development Kit 8a518d637SAlexey Brodkin */ 9a518d637SAlexey Brodkin/dts-v1/; 10a518d637SAlexey Brodkin 11aab128d0SEugeniy Paltsev#include <dt-bindings/gpio/gpio.h> 12ab8eb7dbSEugeniy Paltsev#include <dt-bindings/reset/snps,hsdk-reset.h> 13a518d637SAlexey Brodkin 14a518d637SAlexey Brodkin/ { 15a518d637SAlexey Brodkin model = "snps,hsdk"; 16a518d637SAlexey Brodkin compatible = "snps,hsdk"; 17a518d637SAlexey Brodkin 1821cee1bdSVineet Gupta #address-cells = <2>; 1921cee1bdSVineet Gupta #size-cells = <2>; 20a518d637SAlexey Brodkin 21a518d637SAlexey Brodkin chosen { 22a518d637SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 23a518d637SAlexey Brodkin }; 24a518d637SAlexey Brodkin 255c092089SAlexey Brodkin aliases { 265c092089SAlexey Brodkin ethernet = &gmac; 275c092089SAlexey Brodkin }; 285c092089SAlexey Brodkin 29a518d637SAlexey Brodkin cpus { 30a518d637SAlexey Brodkin #address-cells = <1>; 31a518d637SAlexey Brodkin #size-cells = <0>; 32a518d637SAlexey Brodkin 33a518d637SAlexey Brodkin cpu@0 { 34a518d637SAlexey Brodkin device_type = "cpu"; 35a518d637SAlexey Brodkin compatible = "snps,archs38"; 36a518d637SAlexey Brodkin reg = <0>; 37a518d637SAlexey Brodkin clocks = <&core_clk>; 38a518d637SAlexey Brodkin }; 39a518d637SAlexey Brodkin 40a518d637SAlexey Brodkin cpu@1 { 41a518d637SAlexey Brodkin device_type = "cpu"; 42a518d637SAlexey Brodkin compatible = "snps,archs38"; 43a518d637SAlexey Brodkin reg = <1>; 44a518d637SAlexey Brodkin clocks = <&core_clk>; 45a518d637SAlexey Brodkin }; 46a518d637SAlexey Brodkin 47a518d637SAlexey Brodkin cpu@2 { 48a518d637SAlexey Brodkin device_type = "cpu"; 49a518d637SAlexey Brodkin compatible = "snps,archs38"; 50a518d637SAlexey Brodkin reg = <2>; 51a518d637SAlexey Brodkin clocks = <&core_clk>; 52a518d637SAlexey Brodkin }; 53a518d637SAlexey Brodkin 54a518d637SAlexey Brodkin cpu@3 { 55a518d637SAlexey Brodkin device_type = "cpu"; 56a518d637SAlexey Brodkin compatible = "snps,archs38"; 57a518d637SAlexey Brodkin reg = <3>; 58a518d637SAlexey Brodkin clocks = <&core_clk>; 59a518d637SAlexey Brodkin }; 60a518d637SAlexey Brodkin }; 61a518d637SAlexey Brodkin 62ef833eabSEugeniy Paltsev input_clk: input-clk { 63a518d637SAlexey Brodkin #clock-cells = <0>; 64a518d637SAlexey Brodkin compatible = "fixed-clock"; 65ef833eabSEugeniy Paltsev clock-frequency = <33333333>; 66a518d637SAlexey Brodkin }; 67a518d637SAlexey Brodkin 68a518d637SAlexey Brodkin cpu_intc: cpu-interrupt-controller { 69a518d637SAlexey Brodkin compatible = "snps,archs-intc"; 70a518d637SAlexey Brodkin interrupt-controller; 71a518d637SAlexey Brodkin #interrupt-cells = <1>; 72a518d637SAlexey Brodkin }; 73a518d637SAlexey Brodkin 74a518d637SAlexey Brodkin idu_intc: idu-interrupt-controller { 75a518d637SAlexey Brodkin compatible = "snps,archs-idu-intc"; 76a518d637SAlexey Brodkin interrupt-controller; 77a518d637SAlexey Brodkin #interrupt-cells = <1>; 78a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 79a518d637SAlexey Brodkin }; 80a518d637SAlexey Brodkin 81a518d637SAlexey Brodkin arcpct: pct { 82a518d637SAlexey Brodkin compatible = "snps,archs-pct"; 83a518d637SAlexey Brodkin }; 84a518d637SAlexey Brodkin 85a518d637SAlexey Brodkin /* TIMER0 with interrupt for clockevent */ 86a518d637SAlexey Brodkin timer { 87a518d637SAlexey Brodkin compatible = "snps,arc-timer"; 88a518d637SAlexey Brodkin interrupts = <16>; 89a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 90a518d637SAlexey Brodkin clocks = <&core_clk>; 91a518d637SAlexey Brodkin }; 92a518d637SAlexey Brodkin 93a518d637SAlexey Brodkin /* 64-bit Global Free Running Counter */ 94a518d637SAlexey Brodkin gfrc { 95a518d637SAlexey Brodkin compatible = "snps,archs-timer-gfrc"; 96a518d637SAlexey Brodkin clocks = <&core_clk>; 97a518d637SAlexey Brodkin }; 98a518d637SAlexey Brodkin 99a518d637SAlexey Brodkin soc { 100a518d637SAlexey Brodkin compatible = "simple-bus"; 101a518d637SAlexey Brodkin #address-cells = <1>; 102a518d637SAlexey Brodkin #size-cells = <1>; 103a518d637SAlexey Brodkin interrupt-parent = <&idu_intc>; 104a518d637SAlexey Brodkin 10521cee1bdSVineet Gupta ranges = <0x00000000 0x0 0xf0000000 0x10000000>; 106a518d637SAlexey Brodkin 107ab8eb7dbSEugeniy Paltsev cgu_rst: reset-controller@8a0 { 108ab8eb7dbSEugeniy Paltsev compatible = "snps,hsdk-reset"; 109ab8eb7dbSEugeniy Paltsev #reset-cells = <1>; 110ef4c54c3SAlexey Brodkin reg = <0x8a0 0x4>, <0xff0 0x4>; 111ab8eb7dbSEugeniy Paltsev }; 112ab8eb7dbSEugeniy Paltsev 113ef833eabSEugeniy Paltsev core_clk: core-clk@0 { 114ef833eabSEugeniy Paltsev compatible = "snps,hsdk-core-pll-clock"; 115ef4c54c3SAlexey Brodkin reg = <0x00 0x10>, <0x14b8 0x4>; 116ef833eabSEugeniy Paltsev #clock-cells = <0>; 117ef833eabSEugeniy Paltsev clocks = <&input_clk>; 118a08c832fSEugeniy Paltsev 119a08c832fSEugeniy Paltsev /* 120a08c832fSEugeniy Paltsev * Set initial core pll output frequency to 1GHz. 121a08c832fSEugeniy Paltsev * It will be applied at the core pll driver probing 122a08c832fSEugeniy Paltsev * on early boot. 123a08c832fSEugeniy Paltsev */ 124a08c832fSEugeniy Paltsev assigned-clocks = <&core_clk>; 125a08c832fSEugeniy Paltsev assigned-clock-rates = <1000000000>; 126ef833eabSEugeniy Paltsev }; 127ef833eabSEugeniy Paltsev 128a518d637SAlexey Brodkin serial: serial@5000 { 129a518d637SAlexey Brodkin compatible = "snps,dw-apb-uart"; 130a518d637SAlexey Brodkin reg = <0x5000 0x100>; 131a518d637SAlexey Brodkin clock-frequency = <33330000>; 132a518d637SAlexey Brodkin interrupts = <6>; 133a518d637SAlexey Brodkin baud = <115200>; 134a518d637SAlexey Brodkin reg-shift = <2>; 135a518d637SAlexey Brodkin reg-io-width = <4>; 136a518d637SAlexey Brodkin }; 137a518d637SAlexey Brodkin 138a518d637SAlexey Brodkin gmacclk: gmacclk { 139a518d637SAlexey Brodkin compatible = "fixed-clock"; 140a518d637SAlexey Brodkin clock-frequency = <400000000>; 141a518d637SAlexey Brodkin #clock-cells = <0>; 142a518d637SAlexey Brodkin }; 143a518d637SAlexey Brodkin 144a518d637SAlexey Brodkin mmcclk_ciu: mmcclk-ciu { 145a518d637SAlexey Brodkin compatible = "fixed-clock"; 1466afa3bcfSEugeniy Paltsev /* 1476afa3bcfSEugeniy Paltsev * DW sdio controller has external ciu clock divider 1486afa3bcfSEugeniy Paltsev * controlled via register in SDIO IP. Due to its 149753affbaSEugeniy Paltsev * unexpected default value (it should divide by 1 150753affbaSEugeniy Paltsev * but it divides by 8) SDIO IP uses wrong clock and 1516afa3bcfSEugeniy Paltsev * works unstable (see STAR 9001204800) 152753affbaSEugeniy Paltsev * We switched to the minimum possible value of the 153753affbaSEugeniy Paltsev * divisor (div-by-2) in HSDK platform code. 1546afa3bcfSEugeniy Paltsev * So add temporary fix and change clock frequency 155753affbaSEugeniy Paltsev * to 50000000 Hz until we fix dw sdio driver itself. 1566afa3bcfSEugeniy Paltsev */ 157753affbaSEugeniy Paltsev clock-frequency = <50000000>; 158a518d637SAlexey Brodkin #clock-cells = <0>; 159a518d637SAlexey Brodkin }; 160a518d637SAlexey Brodkin 161a518d637SAlexey Brodkin mmcclk_biu: mmcclk-biu { 162a518d637SAlexey Brodkin compatible = "fixed-clock"; 163a518d637SAlexey Brodkin clock-frequency = <400000000>; 164a518d637SAlexey Brodkin #clock-cells = <0>; 165a518d637SAlexey Brodkin }; 166a518d637SAlexey Brodkin 167b0470064SEugeniy Paltsev gpu_core_clk: gpu-core-clk { 168b0470064SEugeniy Paltsev compatible = "fixed-clock"; 169b0470064SEugeniy Paltsev clock-frequency = <400000000>; 170b0470064SEugeniy Paltsev #clock-cells = <0>; 171b0470064SEugeniy Paltsev }; 172b0470064SEugeniy Paltsev 173b0470064SEugeniy Paltsev gpu_dma_clk: gpu-dma-clk { 174b0470064SEugeniy Paltsev compatible = "fixed-clock"; 175b0470064SEugeniy Paltsev clock-frequency = <400000000>; 176b0470064SEugeniy Paltsev #clock-cells = <0>; 177b0470064SEugeniy Paltsev }; 178b0470064SEugeniy Paltsev 179b0470064SEugeniy Paltsev gpu_cfg_clk: gpu-cfg-clk { 180b0470064SEugeniy Paltsev compatible = "fixed-clock"; 181b0470064SEugeniy Paltsev clock-frequency = <200000000>; 182b0470064SEugeniy Paltsev #clock-cells = <0>; 183b0470064SEugeniy Paltsev }; 184b0470064SEugeniy Paltsev 1855d4ab8d0SEugeniy Paltsev dmac_core_clk: dmac-core-clk { 1865d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1875d4ab8d0SEugeniy Paltsev clock-frequency = <400000000>; 1885d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1895d4ab8d0SEugeniy Paltsev }; 1905d4ab8d0SEugeniy Paltsev 1915d4ab8d0SEugeniy Paltsev dmac_cfg_clk: dmac-gpu-cfg-clk { 1925d4ab8d0SEugeniy Paltsev compatible = "fixed-clock"; 1935d4ab8d0SEugeniy Paltsev clock-frequency = <200000000>; 1945d4ab8d0SEugeniy Paltsev #clock-cells = <0>; 1955d4ab8d0SEugeniy Paltsev }; 1965d4ab8d0SEugeniy Paltsev 1975c092089SAlexey Brodkin gmac: ethernet@8000 { 198a518d637SAlexey Brodkin #interrupt-cells = <1>; 199a518d637SAlexey Brodkin compatible = "snps,dwmac"; 200a518d637SAlexey Brodkin reg = <0x8000 0x2000>; 201a518d637SAlexey Brodkin interrupts = <10>; 202a518d637SAlexey Brodkin interrupt-names = "macirq"; 203a518d637SAlexey Brodkin phy-mode = "rgmii"; 204a518d637SAlexey Brodkin snps,pbl = <32>; 205ecc906a1SJose Abreu snps,multicast-filter-bins = <256>; 206a518d637SAlexey Brodkin clocks = <&gmacclk>; 207a518d637SAlexey Brodkin clock-names = "stmmaceth"; 208a518d637SAlexey Brodkin phy-handle = <&phy0>; 209ab8eb7dbSEugeniy Paltsev resets = <&cgu_rst HSDK_ETH_RESET>; 210ab8eb7dbSEugeniy Paltsev reset-names = "stmmaceth"; 2115c092089SAlexey Brodkin mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */ 212678c8110SEugeniy Paltsev dma-coherent; 213a518d637SAlexey Brodkin 2144c70850aSJose Abreu tx-fifo-depth = <4096>; 2154c70850aSJose Abreu rx-fifo-depth = <4096>; 2164c70850aSJose Abreu 217a518d637SAlexey Brodkin mdio { 218a518d637SAlexey Brodkin #address-cells = <1>; 219a518d637SAlexey Brodkin #size-cells = <0>; 220a518d637SAlexey Brodkin compatible = "snps,dwmac-mdio"; 221a518d637SAlexey Brodkin phy0: ethernet-phy@0 { 222a518d637SAlexey Brodkin reg = <0>; 223a518d637SAlexey Brodkin }; 224a518d637SAlexey Brodkin }; 225a518d637SAlexey Brodkin }; 226a518d637SAlexey Brodkin 227a518d637SAlexey Brodkin ohci@60000 { 228a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 229a518d637SAlexey Brodkin reg = <0x60000 0x100>; 230a518d637SAlexey Brodkin interrupts = <15>; 23166f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 232678c8110SEugeniy Paltsev dma-coherent; 233a518d637SAlexey Brodkin }; 234a518d637SAlexey Brodkin 235a518d637SAlexey Brodkin ehci@40000 { 236a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 237a518d637SAlexey Brodkin reg = <0x40000 0x100>; 238a518d637SAlexey Brodkin interrupts = <15>; 23966f7d370SEugeniy Paltsev resets = <&cgu_rst HSDK_USB_RESET>; 240678c8110SEugeniy Paltsev dma-coherent; 241a518d637SAlexey Brodkin }; 242a518d637SAlexey Brodkin 243a518d637SAlexey Brodkin mmc@a000 { 244a518d637SAlexey Brodkin compatible = "altr,socfpga-dw-mshc"; 245a518d637SAlexey Brodkin reg = <0xa000 0x400>; 246a518d637SAlexey Brodkin num-slots = <1>; 247a518d637SAlexey Brodkin fifo-depth = <16>; 248a518d637SAlexey Brodkin card-detect-delay = <200>; 249a518d637SAlexey Brodkin clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 250a518d637SAlexey Brodkin clock-names = "biu", "ciu"; 251a518d637SAlexey Brodkin interrupts = <12>; 252a518d637SAlexey Brodkin bus-width = <4>; 253678c8110SEugeniy Paltsev dma-coherent; 254a518d637SAlexey Brodkin }; 2554592f11eSEugeniy Paltsev 256aab128d0SEugeniy Paltsev spi0: spi@20000 { 257aab128d0SEugeniy Paltsev compatible = "snps,dw-apb-ssi"; 258aab128d0SEugeniy Paltsev reg = <0x20000 0x100>; 259aab128d0SEugeniy Paltsev #address-cells = <1>; 260aab128d0SEugeniy Paltsev #size-cells = <0>; 261aab128d0SEugeniy Paltsev interrupts = <16>; 262aab128d0SEugeniy Paltsev num-cs = <2>; 263aab128d0SEugeniy Paltsev reg-io-width = <4>; 264aab128d0SEugeniy Paltsev clocks = <&input_clk>; 265aab128d0SEugeniy Paltsev cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>, 266aab128d0SEugeniy Paltsev <&creg_gpio 1 GPIO_ACTIVE_LOW>; 267aab128d0SEugeniy Paltsev }; 268aab128d0SEugeniy Paltsev 269780b35b6SEugeniy Paltsev creg_gpio: gpio@14b0 { 270780b35b6SEugeniy Paltsev compatible = "snps,creg-gpio-hsdk"; 271780b35b6SEugeniy Paltsev reg = <0x14b0 0x4>; 272780b35b6SEugeniy Paltsev gpio-controller; 273780b35b6SEugeniy Paltsev #gpio-cells = <2>; 274780b35b6SEugeniy Paltsev ngpios = <2>; 275780b35b6SEugeniy Paltsev }; 276780b35b6SEugeniy Paltsev 2774592f11eSEugeniy Paltsev gpio: gpio@3000 { 2784592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio"; 2794592f11eSEugeniy Paltsev reg = <0x3000 0x20>; 2804592f11eSEugeniy Paltsev #address-cells = <1>; 2814592f11eSEugeniy Paltsev #size-cells = <0>; 2824592f11eSEugeniy Paltsev 2834592f11eSEugeniy Paltsev gpio_port_a: gpio-controller@0 { 2844592f11eSEugeniy Paltsev compatible = "snps,dw-apb-gpio-port"; 2854592f11eSEugeniy Paltsev gpio-controller; 2864592f11eSEugeniy Paltsev #gpio-cells = <2>; 2874592f11eSEugeniy Paltsev snps,nr-gpios = <24>; 2884592f11eSEugeniy Paltsev reg = <0>; 2894592f11eSEugeniy Paltsev }; 2904592f11eSEugeniy Paltsev }; 2915d4ab8d0SEugeniy Paltsev 292b0470064SEugeniy Paltsev gpu_3d: gpu@90000 { 293b0470064SEugeniy Paltsev compatible = "vivante,gc"; 294b0470064SEugeniy Paltsev reg = <0x90000 0x4000>; 295b0470064SEugeniy Paltsev clocks = <&gpu_dma_clk>, 296b0470064SEugeniy Paltsev <&gpu_cfg_clk>, 297b0470064SEugeniy Paltsev <&gpu_core_clk>, 298b0470064SEugeniy Paltsev <&gpu_core_clk>; 299b0470064SEugeniy Paltsev clock-names = "bus", "reg", "core", "shader"; 300b0470064SEugeniy Paltsev interrupts = <28>; 301b0470064SEugeniy Paltsev }; 302b0470064SEugeniy Paltsev 3035d4ab8d0SEugeniy Paltsev dmac: dmac@80000 { 3045d4ab8d0SEugeniy Paltsev compatible = "snps,axi-dma-1.01a"; 3055d4ab8d0SEugeniy Paltsev reg = <0x80000 0x400>; 3065d4ab8d0SEugeniy Paltsev interrupts = <27>; 3075d4ab8d0SEugeniy Paltsev clocks = <&dmac_core_clk>, <&dmac_cfg_clk>; 3085d4ab8d0SEugeniy Paltsev clock-names = "core-clk", "cfgr-clk"; 3095d4ab8d0SEugeniy Paltsev 3105d4ab8d0SEugeniy Paltsev dma-channels = <4>; 3115d4ab8d0SEugeniy Paltsev snps,dma-masters = <2>; 3125d4ab8d0SEugeniy Paltsev snps,data-width = <3>; 3135d4ab8d0SEugeniy Paltsev snps,block-size = <4096 4096 4096 4096>; 3145d4ab8d0SEugeniy Paltsev snps,priority = <0 1 2 3>; 3155d4ab8d0SEugeniy Paltsev snps,axi-max-burst-len = <16>; 3165d4ab8d0SEugeniy Paltsev }; 317a518d637SAlexey Brodkin }; 318a518d637SAlexey Brodkin 319a518d637SAlexey Brodkin memory@80000000 { 32021cee1bdSVineet Gupta #address-cells = <2>; 32121cee1bdSVineet Gupta #size-cells = <2>; 322a518d637SAlexey Brodkin device_type = "memory"; 32321cee1bdSVineet Gupta reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */ 32421cee1bdSVineet Gupta /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */ 325a518d637SAlexey Brodkin }; 326a518d637SAlexey Brodkin}; 327