1a518d637SAlexey Brodkin/* 2a518d637SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) 3a518d637SAlexey Brodkin * 4a518d637SAlexey Brodkin * This program is free software; you can redistribute it and/or modify 5a518d637SAlexey Brodkin * it under the terms of the GNU General Public License version 2 as 6a518d637SAlexey Brodkin * published by the Free Software Foundation. 7a518d637SAlexey Brodkin */ 8a518d637SAlexey Brodkin 9a518d637SAlexey Brodkin/* 10a518d637SAlexey Brodkin * Device Tree for ARC HS Development Kit 11a518d637SAlexey Brodkin */ 12a518d637SAlexey Brodkin/dts-v1/; 13a518d637SAlexey Brodkin 14a518d637SAlexey Brodkin#include <dt-bindings/net/ti-dp83867.h> 15ab8eb7dbSEugeniy Paltsev#include <dt-bindings/reset/snps,hsdk-reset.h> 16a518d637SAlexey Brodkin 17a518d637SAlexey Brodkin/ { 18a518d637SAlexey Brodkin model = "snps,hsdk"; 19a518d637SAlexey Brodkin compatible = "snps,hsdk"; 20a518d637SAlexey Brodkin 21a518d637SAlexey Brodkin #address-cells = <1>; 22a518d637SAlexey Brodkin #size-cells = <1>; 23a518d637SAlexey Brodkin 24a518d637SAlexey Brodkin chosen { 25a518d637SAlexey Brodkin bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 26a518d637SAlexey Brodkin }; 27a518d637SAlexey Brodkin 28a518d637SAlexey Brodkin cpus { 29a518d637SAlexey Brodkin #address-cells = <1>; 30a518d637SAlexey Brodkin #size-cells = <0>; 31a518d637SAlexey Brodkin 32a518d637SAlexey Brodkin cpu@0 { 33a518d637SAlexey Brodkin device_type = "cpu"; 34a518d637SAlexey Brodkin compatible = "snps,archs38"; 35a518d637SAlexey Brodkin reg = <0>; 36a518d637SAlexey Brodkin clocks = <&core_clk>; 37a518d637SAlexey Brodkin }; 38a518d637SAlexey Brodkin 39a518d637SAlexey Brodkin cpu@1 { 40a518d637SAlexey Brodkin device_type = "cpu"; 41a518d637SAlexey Brodkin compatible = "snps,archs38"; 42a518d637SAlexey Brodkin reg = <1>; 43a518d637SAlexey Brodkin clocks = <&core_clk>; 44a518d637SAlexey Brodkin }; 45a518d637SAlexey Brodkin 46a518d637SAlexey Brodkin cpu@2 { 47a518d637SAlexey Brodkin device_type = "cpu"; 48a518d637SAlexey Brodkin compatible = "snps,archs38"; 49a518d637SAlexey Brodkin reg = <2>; 50a518d637SAlexey Brodkin clocks = <&core_clk>; 51a518d637SAlexey Brodkin }; 52a518d637SAlexey Brodkin 53a518d637SAlexey Brodkin cpu@3 { 54a518d637SAlexey Brodkin device_type = "cpu"; 55a518d637SAlexey Brodkin compatible = "snps,archs38"; 56a518d637SAlexey Brodkin reg = <3>; 57a518d637SAlexey Brodkin clocks = <&core_clk>; 58a518d637SAlexey Brodkin }; 59a518d637SAlexey Brodkin }; 60a518d637SAlexey Brodkin 61ef833eabSEugeniy Paltsev input_clk: input-clk { 62a518d637SAlexey Brodkin #clock-cells = <0>; 63a518d637SAlexey Brodkin compatible = "fixed-clock"; 64ef833eabSEugeniy Paltsev clock-frequency = <33333333>; 65a518d637SAlexey Brodkin }; 66a518d637SAlexey Brodkin 67a518d637SAlexey Brodkin cpu_intc: cpu-interrupt-controller { 68a518d637SAlexey Brodkin compatible = "snps,archs-intc"; 69a518d637SAlexey Brodkin interrupt-controller; 70a518d637SAlexey Brodkin #interrupt-cells = <1>; 71a518d637SAlexey Brodkin }; 72a518d637SAlexey Brodkin 73a518d637SAlexey Brodkin idu_intc: idu-interrupt-controller { 74a518d637SAlexey Brodkin compatible = "snps,archs-idu-intc"; 75a518d637SAlexey Brodkin interrupt-controller; 76a518d637SAlexey Brodkin #interrupt-cells = <1>; 77a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 78a518d637SAlexey Brodkin }; 79a518d637SAlexey Brodkin 80a518d637SAlexey Brodkin arcpct: pct { 81a518d637SAlexey Brodkin compatible = "snps,archs-pct"; 82a518d637SAlexey Brodkin }; 83a518d637SAlexey Brodkin 84a518d637SAlexey Brodkin /* TIMER0 with interrupt for clockevent */ 85a518d637SAlexey Brodkin timer { 86a518d637SAlexey Brodkin compatible = "snps,arc-timer"; 87a518d637SAlexey Brodkin interrupts = <16>; 88a518d637SAlexey Brodkin interrupt-parent = <&cpu_intc>; 89a518d637SAlexey Brodkin clocks = <&core_clk>; 90a518d637SAlexey Brodkin }; 91a518d637SAlexey Brodkin 92a518d637SAlexey Brodkin /* 64-bit Global Free Running Counter */ 93a518d637SAlexey Brodkin gfrc { 94a518d637SAlexey Brodkin compatible = "snps,archs-timer-gfrc"; 95a518d637SAlexey Brodkin clocks = <&core_clk>; 96a518d637SAlexey Brodkin }; 97a518d637SAlexey Brodkin 98a518d637SAlexey Brodkin soc { 99a518d637SAlexey Brodkin compatible = "simple-bus"; 100a518d637SAlexey Brodkin #address-cells = <1>; 101a518d637SAlexey Brodkin #size-cells = <1>; 102a518d637SAlexey Brodkin interrupt-parent = <&idu_intc>; 103a518d637SAlexey Brodkin 104a518d637SAlexey Brodkin ranges = <0x00000000 0xf0000000 0x10000000>; 105a518d637SAlexey Brodkin 106ab8eb7dbSEugeniy Paltsev cgu_rst: reset-controller@8a0 { 107ab8eb7dbSEugeniy Paltsev compatible = "snps,hsdk-reset"; 108ab8eb7dbSEugeniy Paltsev #reset-cells = <1>; 109ab8eb7dbSEugeniy Paltsev reg = <0x8A0 0x4>, <0xFF0 0x4>; 110ab8eb7dbSEugeniy Paltsev }; 111ab8eb7dbSEugeniy Paltsev 112ef833eabSEugeniy Paltsev core_clk: core-clk@0 { 113ef833eabSEugeniy Paltsev compatible = "snps,hsdk-core-pll-clock"; 114ef833eabSEugeniy Paltsev reg = <0x00 0x10>, <0x14B8 0x4>; 115ef833eabSEugeniy Paltsev #clock-cells = <0>; 116ef833eabSEugeniy Paltsev clocks = <&input_clk>; 117a08c832fSEugeniy Paltsev 118a08c832fSEugeniy Paltsev /* 119a08c832fSEugeniy Paltsev * Set initial core pll output frequency to 1GHz. 120a08c832fSEugeniy Paltsev * It will be applied at the core pll driver probing 121a08c832fSEugeniy Paltsev * on early boot. 122a08c832fSEugeniy Paltsev */ 123a08c832fSEugeniy Paltsev assigned-clocks = <&core_clk>; 124a08c832fSEugeniy Paltsev assigned-clock-rates = <1000000000>; 125ef833eabSEugeniy Paltsev }; 126ef833eabSEugeniy Paltsev 127a518d637SAlexey Brodkin serial: serial@5000 { 128a518d637SAlexey Brodkin compatible = "snps,dw-apb-uart"; 129a518d637SAlexey Brodkin reg = <0x5000 0x100>; 130a518d637SAlexey Brodkin clock-frequency = <33330000>; 131a518d637SAlexey Brodkin interrupts = <6>; 132a518d637SAlexey Brodkin baud = <115200>; 133a518d637SAlexey Brodkin reg-shift = <2>; 134a518d637SAlexey Brodkin reg-io-width = <4>; 135a518d637SAlexey Brodkin }; 136a518d637SAlexey Brodkin 137a518d637SAlexey Brodkin gmacclk: gmacclk { 138a518d637SAlexey Brodkin compatible = "fixed-clock"; 139a518d637SAlexey Brodkin clock-frequency = <400000000>; 140a518d637SAlexey Brodkin #clock-cells = <0>; 141a518d637SAlexey Brodkin }; 142a518d637SAlexey Brodkin 143a518d637SAlexey Brodkin mmcclk_ciu: mmcclk-ciu { 144a518d637SAlexey Brodkin compatible = "fixed-clock"; 1456afa3bcfSEugeniy Paltsev /* 1466afa3bcfSEugeniy Paltsev * DW sdio controller has external ciu clock divider 1476afa3bcfSEugeniy Paltsev * controlled via register in SDIO IP. Due to its 148753affbaSEugeniy Paltsev * unexpected default value (it should divide by 1 149753affbaSEugeniy Paltsev * but it divides by 8) SDIO IP uses wrong clock and 1506afa3bcfSEugeniy Paltsev * works unstable (see STAR 9001204800) 151753affbaSEugeniy Paltsev * We switched to the minimum possible value of the 152753affbaSEugeniy Paltsev * divisor (div-by-2) in HSDK platform code. 1536afa3bcfSEugeniy Paltsev * So add temporary fix and change clock frequency 154753affbaSEugeniy Paltsev * to 50000000 Hz until we fix dw sdio driver itself. 1556afa3bcfSEugeniy Paltsev */ 156753affbaSEugeniy Paltsev clock-frequency = <50000000>; 157a518d637SAlexey Brodkin #clock-cells = <0>; 158a518d637SAlexey Brodkin }; 159a518d637SAlexey Brodkin 160a518d637SAlexey Brodkin mmcclk_biu: mmcclk-biu { 161a518d637SAlexey Brodkin compatible = "fixed-clock"; 162a518d637SAlexey Brodkin clock-frequency = <400000000>; 163a518d637SAlexey Brodkin #clock-cells = <0>; 164a518d637SAlexey Brodkin }; 165a518d637SAlexey Brodkin 166a518d637SAlexey Brodkin ethernet@8000 { 167a518d637SAlexey Brodkin #interrupt-cells = <1>; 168a518d637SAlexey Brodkin compatible = "snps,dwmac"; 169a518d637SAlexey Brodkin reg = <0x8000 0x2000>; 170a518d637SAlexey Brodkin interrupts = <10>; 171a518d637SAlexey Brodkin interrupt-names = "macirq"; 172a518d637SAlexey Brodkin phy-mode = "rgmii"; 173a518d637SAlexey Brodkin snps,pbl = <32>; 174a518d637SAlexey Brodkin clocks = <&gmacclk>; 175a518d637SAlexey Brodkin clock-names = "stmmaceth"; 176a518d637SAlexey Brodkin phy-handle = <&phy0>; 177ab8eb7dbSEugeniy Paltsev resets = <&cgu_rst HSDK_ETH_RESET>; 178ab8eb7dbSEugeniy Paltsev reset-names = "stmmaceth"; 179a518d637SAlexey Brodkin 180a518d637SAlexey Brodkin mdio { 181a518d637SAlexey Brodkin #address-cells = <1>; 182a518d637SAlexey Brodkin #size-cells = <0>; 183a518d637SAlexey Brodkin compatible = "snps,dwmac-mdio"; 184a518d637SAlexey Brodkin phy0: ethernet-phy@0 { 185a518d637SAlexey Brodkin reg = <0>; 186a518d637SAlexey Brodkin ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 187a518d637SAlexey Brodkin ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 188a518d637SAlexey Brodkin ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 189a518d637SAlexey Brodkin }; 190a518d637SAlexey Brodkin }; 191a518d637SAlexey Brodkin }; 192a518d637SAlexey Brodkin 193a518d637SAlexey Brodkin ohci@60000 { 194a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ohci", "generic-ohci"; 195a518d637SAlexey Brodkin reg = <0x60000 0x100>; 196a518d637SAlexey Brodkin interrupts = <15>; 197a518d637SAlexey Brodkin }; 198a518d637SAlexey Brodkin 199a518d637SAlexey Brodkin ehci@40000 { 200a518d637SAlexey Brodkin compatible = "snps,hsdk-v1.0-ehci", "generic-ehci"; 201a518d637SAlexey Brodkin reg = <0x40000 0x100>; 202a518d637SAlexey Brodkin interrupts = <15>; 203a518d637SAlexey Brodkin }; 204a518d637SAlexey Brodkin 205a518d637SAlexey Brodkin mmc@a000 { 206a518d637SAlexey Brodkin compatible = "altr,socfpga-dw-mshc"; 207a518d637SAlexey Brodkin reg = <0xa000 0x400>; 208a518d637SAlexey Brodkin num-slots = <1>; 209a518d637SAlexey Brodkin fifo-depth = <16>; 210a518d637SAlexey Brodkin card-detect-delay = <200>; 211a518d637SAlexey Brodkin clocks = <&mmcclk_biu>, <&mmcclk_ciu>; 212a518d637SAlexey Brodkin clock-names = "biu", "ciu"; 213a518d637SAlexey Brodkin interrupts = <12>; 214a518d637SAlexey Brodkin bus-width = <4>; 215a518d637SAlexey Brodkin }; 216a518d637SAlexey Brodkin }; 217a518d637SAlexey Brodkin 218a518d637SAlexey Brodkin memory@80000000 { 219a518d637SAlexey Brodkin #address-cells = <1>; 220a518d637SAlexey Brodkin #size-cells = <1>; 221a518d637SAlexey Brodkin device_type = "memory"; 222a518d637SAlexey Brodkin reg = <0x80000000 0x40000000>; /* 1 GiB */ 223a518d637SAlexey Brodkin }; 224a518d637SAlexey Brodkin}; 225