1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 54 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 55 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 56 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 57 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 58 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 59 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 60 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 61 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 62 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 63 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 64 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 65 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 66 67 #define AMDGPU_GEM_DOMAIN_CPU 0x1 68 #define AMDGPU_GEM_DOMAIN_GTT 0x2 69 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 70 #define AMDGPU_GEM_DOMAIN_GDS 0x8 71 #define AMDGPU_GEM_DOMAIN_GWS 0x10 72 #define AMDGPU_GEM_DOMAIN_OA 0x20 73 74 /* Flag that CPU access will be required for the case of VRAM domain */ 75 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 76 /* Flag that CPU access will not work, this VRAM domain is invisible */ 77 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 78 /* Flag that USWC attributes should be used for GTT */ 79 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 80 /* Flag that the memory should be in VRAM and cleared */ 81 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 82 /* Flag that create shadow bo(GTT) while allocating vram bo */ 83 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 84 /* Flag that allocating the BO should use linear VRAM */ 85 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 86 87 struct drm_amdgpu_gem_create_in { 88 /** the requested memory size */ 89 __u64 bo_size; 90 /** physical start_addr alignment in bytes for some HW requirements */ 91 __u64 alignment; 92 /** the requested memory domains */ 93 __u64 domains; 94 /** allocation flags */ 95 __u64 domain_flags; 96 }; 97 98 struct drm_amdgpu_gem_create_out { 99 /** returned GEM object handle */ 100 __u32 handle; 101 __u32 _pad; 102 }; 103 104 union drm_amdgpu_gem_create { 105 struct drm_amdgpu_gem_create_in in; 106 struct drm_amdgpu_gem_create_out out; 107 }; 108 109 /** Opcode to create new residency list. */ 110 #define AMDGPU_BO_LIST_OP_CREATE 0 111 /** Opcode to destroy previously created residency list */ 112 #define AMDGPU_BO_LIST_OP_DESTROY 1 113 /** Opcode to update resource information in the list */ 114 #define AMDGPU_BO_LIST_OP_UPDATE 2 115 116 struct drm_amdgpu_bo_list_in { 117 /** Type of operation */ 118 __u32 operation; 119 /** Handle of list or 0 if we want to create one */ 120 __u32 list_handle; 121 /** Number of BOs in list */ 122 __u32 bo_number; 123 /** Size of each element describing BO */ 124 __u32 bo_info_size; 125 /** Pointer to array describing BOs */ 126 __u64 bo_info_ptr; 127 }; 128 129 struct drm_amdgpu_bo_list_entry { 130 /** Handle of BO */ 131 __u32 bo_handle; 132 /** New (if specified) BO priority to be used during migration */ 133 __u32 bo_priority; 134 }; 135 136 struct drm_amdgpu_bo_list_out { 137 /** Handle of resource list */ 138 __u32 list_handle; 139 __u32 _pad; 140 }; 141 142 union drm_amdgpu_bo_list { 143 struct drm_amdgpu_bo_list_in in; 144 struct drm_amdgpu_bo_list_out out; 145 }; 146 147 /* context related */ 148 #define AMDGPU_CTX_OP_ALLOC_CTX 1 149 #define AMDGPU_CTX_OP_FREE_CTX 2 150 #define AMDGPU_CTX_OP_QUERY_STATE 3 151 152 /* GPU reset status */ 153 #define AMDGPU_CTX_NO_RESET 0 154 /* this the context caused it */ 155 #define AMDGPU_CTX_GUILTY_RESET 1 156 /* some other context caused it */ 157 #define AMDGPU_CTX_INNOCENT_RESET 2 158 /* unknown cause */ 159 #define AMDGPU_CTX_UNKNOWN_RESET 3 160 161 struct drm_amdgpu_ctx_in { 162 /** AMDGPU_CTX_OP_* */ 163 __u32 op; 164 /** For future use, no flags defined so far */ 165 __u32 flags; 166 __u32 ctx_id; 167 __u32 _pad; 168 }; 169 170 union drm_amdgpu_ctx_out { 171 struct { 172 __u32 ctx_id; 173 __u32 _pad; 174 } alloc; 175 176 struct { 177 /** For future use, no flags defined so far */ 178 __u64 flags; 179 /** Number of resets caused by this context so far. */ 180 __u32 hangs; 181 /** Reset status since the last call of the ioctl. */ 182 __u32 reset_status; 183 } state; 184 }; 185 186 union drm_amdgpu_ctx { 187 struct drm_amdgpu_ctx_in in; 188 union drm_amdgpu_ctx_out out; 189 }; 190 191 /* 192 * This is not a reliable API and you should expect it to fail for any 193 * number of reasons and have fallback path that do not use userptr to 194 * perform any operation. 195 */ 196 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 197 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 198 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 199 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 200 201 struct drm_amdgpu_gem_userptr { 202 __u64 addr; 203 __u64 size; 204 /* AMDGPU_GEM_USERPTR_* */ 205 __u32 flags; 206 /* Resulting GEM handle */ 207 __u32 handle; 208 }; 209 210 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 211 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 212 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 213 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 214 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 215 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 216 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 217 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 218 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 219 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 220 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 221 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 222 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 223 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 224 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 225 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 226 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 227 228 #define AMDGPU_TILING_SET(field, value) \ 229 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 230 #define AMDGPU_TILING_GET(value, field) \ 231 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 232 233 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 234 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 235 236 /** The same structure is shared for input/output */ 237 struct drm_amdgpu_gem_metadata { 238 /** GEM Object handle */ 239 __u32 handle; 240 /** Do we want get or set metadata */ 241 __u32 op; 242 struct { 243 /** For future use, no flags defined so far */ 244 __u64 flags; 245 /** family specific tiling info */ 246 __u64 tiling_info; 247 __u32 data_size_bytes; 248 __u32 data[64]; 249 } data; 250 }; 251 252 struct drm_amdgpu_gem_mmap_in { 253 /** the GEM object handle */ 254 __u32 handle; 255 __u32 _pad; 256 }; 257 258 struct drm_amdgpu_gem_mmap_out { 259 /** mmap offset from the vma offset manager */ 260 __u64 addr_ptr; 261 }; 262 263 union drm_amdgpu_gem_mmap { 264 struct drm_amdgpu_gem_mmap_in in; 265 struct drm_amdgpu_gem_mmap_out out; 266 }; 267 268 struct drm_amdgpu_gem_wait_idle_in { 269 /** GEM object handle */ 270 __u32 handle; 271 /** For future use, no flags defined so far */ 272 __u32 flags; 273 /** Absolute timeout to wait */ 274 __u64 timeout; 275 }; 276 277 struct drm_amdgpu_gem_wait_idle_out { 278 /** BO status: 0 - BO is idle, 1 - BO is busy */ 279 __u32 status; 280 /** Returned current memory domain */ 281 __u32 domain; 282 }; 283 284 union drm_amdgpu_gem_wait_idle { 285 struct drm_amdgpu_gem_wait_idle_in in; 286 struct drm_amdgpu_gem_wait_idle_out out; 287 }; 288 289 struct drm_amdgpu_wait_cs_in { 290 /** Command submission handle */ 291 __u64 handle; 292 /** Absolute timeout to wait */ 293 __u64 timeout; 294 __u32 ip_type; 295 __u32 ip_instance; 296 __u32 ring; 297 __u32 ctx_id; 298 }; 299 300 struct drm_amdgpu_wait_cs_out { 301 /** CS status: 0 - CS completed, 1 - CS still busy */ 302 __u64 status; 303 }; 304 305 union drm_amdgpu_wait_cs { 306 struct drm_amdgpu_wait_cs_in in; 307 struct drm_amdgpu_wait_cs_out out; 308 }; 309 310 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 311 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 312 313 /* Sets or returns a value associated with a buffer. */ 314 struct drm_amdgpu_gem_op { 315 /** GEM object handle */ 316 __u32 handle; 317 /** AMDGPU_GEM_OP_* */ 318 __u32 op; 319 /** Input or return value */ 320 __u64 value; 321 }; 322 323 #define AMDGPU_VA_OP_MAP 1 324 #define AMDGPU_VA_OP_UNMAP 2 325 326 /* Delay the page table update till the next CS */ 327 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 328 329 /* Mapping flags */ 330 /* readable mapping */ 331 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 332 /* writable mapping */ 333 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 334 /* executable mapping, new for VI */ 335 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 336 337 struct drm_amdgpu_gem_va { 338 /** GEM object handle */ 339 __u32 handle; 340 __u32 _pad; 341 /** AMDGPU_VA_OP_* */ 342 __u32 operation; 343 /** AMDGPU_VM_PAGE_* */ 344 __u32 flags; 345 /** va address to assign . Must be correctly aligned.*/ 346 __u64 va_address; 347 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 348 __u64 offset_in_bo; 349 /** Specify mapping size. Must be correctly aligned. */ 350 __u64 map_size; 351 }; 352 353 #define AMDGPU_HW_IP_GFX 0 354 #define AMDGPU_HW_IP_COMPUTE 1 355 #define AMDGPU_HW_IP_DMA 2 356 #define AMDGPU_HW_IP_UVD 3 357 #define AMDGPU_HW_IP_VCE 4 358 #define AMDGPU_HW_IP_NUM 5 359 360 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 361 362 #define AMDGPU_CHUNK_ID_IB 0x01 363 #define AMDGPU_CHUNK_ID_FENCE 0x02 364 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 365 366 struct drm_amdgpu_cs_chunk { 367 __u32 chunk_id; 368 __u32 length_dw; 369 __u64 chunk_data; 370 }; 371 372 struct drm_amdgpu_cs_in { 373 /** Rendering context id */ 374 __u32 ctx_id; 375 /** Handle of resource list associated with CS */ 376 __u32 bo_list_handle; 377 __u32 num_chunks; 378 __u32 _pad; 379 /** this points to __u64 * which point to cs chunks */ 380 __u64 chunks; 381 }; 382 383 struct drm_amdgpu_cs_out { 384 __u64 handle; 385 }; 386 387 union drm_amdgpu_cs { 388 struct drm_amdgpu_cs_in in; 389 struct drm_amdgpu_cs_out out; 390 }; 391 392 /* Specify flags to be used for IB */ 393 394 /* This IB should be submitted to CE */ 395 #define AMDGPU_IB_FLAG_CE (1<<0) 396 397 /* CE Preamble */ 398 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 399 400 struct drm_amdgpu_cs_chunk_ib { 401 __u32 _pad; 402 /** AMDGPU_IB_FLAG_* */ 403 __u32 flags; 404 /** Virtual address to begin IB execution */ 405 __u64 va_start; 406 /** Size of submission */ 407 __u32 ib_bytes; 408 /** HW IP to submit to */ 409 __u32 ip_type; 410 /** HW IP index of the same type to submit to */ 411 __u32 ip_instance; 412 /** Ring index to submit to */ 413 __u32 ring; 414 }; 415 416 struct drm_amdgpu_cs_chunk_dep { 417 __u32 ip_type; 418 __u32 ip_instance; 419 __u32 ring; 420 __u32 ctx_id; 421 __u64 handle; 422 }; 423 424 struct drm_amdgpu_cs_chunk_fence { 425 __u32 handle; 426 __u32 offset; 427 }; 428 429 struct drm_amdgpu_cs_chunk_data { 430 union { 431 struct drm_amdgpu_cs_chunk_ib ib_data; 432 struct drm_amdgpu_cs_chunk_fence fence_data; 433 }; 434 }; 435 436 /** 437 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 438 * 439 */ 440 #define AMDGPU_IDS_FLAGS_FUSION 0x1 441 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 442 443 /* indicate if acceleration can be working */ 444 #define AMDGPU_INFO_ACCEL_WORKING 0x00 445 /* get the crtc_id from the mode object id? */ 446 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 447 /* query hw IP info */ 448 #define AMDGPU_INFO_HW_IP_INFO 0x02 449 /* query hw IP instance count for the specified type */ 450 #define AMDGPU_INFO_HW_IP_COUNT 0x03 451 /* timestamp for GL_ARB_timer_query */ 452 #define AMDGPU_INFO_TIMESTAMP 0x05 453 /* Query the firmware version */ 454 #define AMDGPU_INFO_FW_VERSION 0x0e 455 /* Subquery id: Query VCE firmware version */ 456 #define AMDGPU_INFO_FW_VCE 0x1 457 /* Subquery id: Query UVD firmware version */ 458 #define AMDGPU_INFO_FW_UVD 0x2 459 /* Subquery id: Query GMC firmware version */ 460 #define AMDGPU_INFO_FW_GMC 0x03 461 /* Subquery id: Query GFX ME firmware version */ 462 #define AMDGPU_INFO_FW_GFX_ME 0x04 463 /* Subquery id: Query GFX PFP firmware version */ 464 #define AMDGPU_INFO_FW_GFX_PFP 0x05 465 /* Subquery id: Query GFX CE firmware version */ 466 #define AMDGPU_INFO_FW_GFX_CE 0x06 467 /* Subquery id: Query GFX RLC firmware version */ 468 #define AMDGPU_INFO_FW_GFX_RLC 0x07 469 /* Subquery id: Query GFX MEC firmware version */ 470 #define AMDGPU_INFO_FW_GFX_MEC 0x08 471 /* Subquery id: Query SMC firmware version */ 472 #define AMDGPU_INFO_FW_SMC 0x0a 473 /* Subquery id: Query SDMA firmware version */ 474 #define AMDGPU_INFO_FW_SDMA 0x0b 475 /* number of bytes moved for TTM migration */ 476 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 477 /* the used VRAM size */ 478 #define AMDGPU_INFO_VRAM_USAGE 0x10 479 /* the used GTT size */ 480 #define AMDGPU_INFO_GTT_USAGE 0x11 481 /* Information about GDS, etc. resource configuration */ 482 #define AMDGPU_INFO_GDS_CONFIG 0x13 483 /* Query information about VRAM and GTT domains */ 484 #define AMDGPU_INFO_VRAM_GTT 0x14 485 /* Query information about register in MMR address space*/ 486 #define AMDGPU_INFO_READ_MMR_REG 0x15 487 /* Query information about device: rev id, family, etc. */ 488 #define AMDGPU_INFO_DEV_INFO 0x16 489 /* visible vram usage */ 490 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 491 /* number of TTM buffer evictions */ 492 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 493 /* Query memory about VRAM and GTT domains */ 494 #define AMDGPU_INFO_MEMORY 0x19 495 /* Query vce clock table */ 496 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 497 498 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 499 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 500 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 501 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 502 503 struct drm_amdgpu_query_fw { 504 /** AMDGPU_INFO_FW_* */ 505 __u32 fw_type; 506 /** 507 * Index of the IP if there are more IPs of 508 * the same type. 509 */ 510 __u32 ip_instance; 511 /** 512 * Index of the engine. Whether this is used depends 513 * on the firmware type. (e.g. MEC, SDMA) 514 */ 515 __u32 index; 516 __u32 _pad; 517 }; 518 519 /* Input structure for the INFO ioctl */ 520 struct drm_amdgpu_info { 521 /* Where the return value will be stored */ 522 __u64 return_pointer; 523 /* The size of the return value. Just like "size" in "snprintf", 524 * it limits how many bytes the kernel can write. */ 525 __u32 return_size; 526 /* The query request id. */ 527 __u32 query; 528 529 union { 530 struct { 531 __u32 id; 532 __u32 _pad; 533 } mode_crtc; 534 535 struct { 536 /** AMDGPU_HW_IP_* */ 537 __u32 type; 538 /** 539 * Index of the IP if there are more IPs of the same 540 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 541 */ 542 __u32 ip_instance; 543 } query_hw_ip; 544 545 struct { 546 __u32 dword_offset; 547 /** number of registers to read */ 548 __u32 count; 549 __u32 instance; 550 /** For future use, no flags defined so far */ 551 __u32 flags; 552 } read_mmr_reg; 553 554 struct drm_amdgpu_query_fw query_fw; 555 }; 556 }; 557 558 struct drm_amdgpu_info_gds { 559 /** GDS GFX partition size */ 560 __u32 gds_gfx_partition_size; 561 /** GDS compute partition size */ 562 __u32 compute_partition_size; 563 /** total GDS memory size */ 564 __u32 gds_total_size; 565 /** GWS size per GFX partition */ 566 __u32 gws_per_gfx_partition; 567 /** GSW size per compute partition */ 568 __u32 gws_per_compute_partition; 569 /** OA size per GFX partition */ 570 __u32 oa_per_gfx_partition; 571 /** OA size per compute partition */ 572 __u32 oa_per_compute_partition; 573 __u32 _pad; 574 }; 575 576 struct drm_amdgpu_info_vram_gtt { 577 __u64 vram_size; 578 __u64 vram_cpu_accessible_size; 579 __u64 gtt_size; 580 }; 581 582 struct drm_amdgpu_heap_info { 583 /** max. physical memory */ 584 __u64 total_heap_size; 585 586 /** Theoretical max. available memory in the given heap */ 587 __u64 usable_heap_size; 588 589 /** 590 * Number of bytes allocated in the heap. This includes all processes 591 * and private allocations in the kernel. It changes when new buffers 592 * are allocated, freed, and moved. It cannot be larger than 593 * heap_size. 594 */ 595 __u64 heap_usage; 596 597 /** 598 * Theoretical possible max. size of buffer which 599 * could be allocated in the given heap 600 */ 601 __u64 max_allocation; 602 }; 603 604 struct drm_amdgpu_memory_info { 605 struct drm_amdgpu_heap_info vram; 606 struct drm_amdgpu_heap_info cpu_accessible_vram; 607 struct drm_amdgpu_heap_info gtt; 608 }; 609 610 struct drm_amdgpu_info_firmware { 611 __u32 ver; 612 __u32 feature; 613 }; 614 615 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 616 #define AMDGPU_VRAM_TYPE_GDDR1 1 617 #define AMDGPU_VRAM_TYPE_DDR2 2 618 #define AMDGPU_VRAM_TYPE_GDDR3 3 619 #define AMDGPU_VRAM_TYPE_GDDR4 4 620 #define AMDGPU_VRAM_TYPE_GDDR5 5 621 #define AMDGPU_VRAM_TYPE_HBM 6 622 #define AMDGPU_VRAM_TYPE_DDR3 7 623 624 struct drm_amdgpu_info_device { 625 /** PCI Device ID */ 626 __u32 device_id; 627 /** Internal chip revision: A0, A1, etc.) */ 628 __u32 chip_rev; 629 __u32 external_rev; 630 /** Revision id in PCI Config space */ 631 __u32 pci_rev; 632 __u32 family; 633 __u32 num_shader_engines; 634 __u32 num_shader_arrays_per_engine; 635 /* in KHz */ 636 __u32 gpu_counter_freq; 637 __u64 max_engine_clock; 638 __u64 max_memory_clock; 639 /* cu information */ 640 __u32 cu_active_number; 641 __u32 cu_ao_mask; 642 __u32 cu_bitmap[4][4]; 643 /** Render backend pipe mask. One render backend is CB+DB. */ 644 __u32 enabled_rb_pipes_mask; 645 __u32 num_rb_pipes; 646 __u32 num_hw_gfx_contexts; 647 __u32 _pad; 648 __u64 ids_flags; 649 /** Starting virtual address for UMDs. */ 650 __u64 virtual_address_offset; 651 /** The maximum virtual address */ 652 __u64 virtual_address_max; 653 /** Required alignment of virtual addresses. */ 654 __u32 virtual_address_alignment; 655 /** Page table entry - fragment size */ 656 __u32 pte_fragment_size; 657 __u32 gart_page_size; 658 /** constant engine ram size*/ 659 __u32 ce_ram_size; 660 /** video memory type info*/ 661 __u32 vram_type; 662 /** video memory bit width*/ 663 __u32 vram_bit_width; 664 /* vce harvesting instance */ 665 __u32 vce_harvest_config; 666 }; 667 668 struct drm_amdgpu_info_hw_ip { 669 /** Version of h/w IP */ 670 __u32 hw_ip_version_major; 671 __u32 hw_ip_version_minor; 672 /** Capabilities */ 673 __u64 capabilities_flags; 674 /** command buffer address start alignment*/ 675 __u32 ib_start_alignment; 676 /** command buffer size alignment*/ 677 __u32 ib_size_alignment; 678 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 679 __u32 available_rings; 680 __u32 _pad; 681 }; 682 683 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 684 685 struct drm_amdgpu_info_vce_clock_table_entry { 686 /** System clock */ 687 __u32 sclk; 688 /** Memory clock */ 689 __u32 mclk; 690 /** VCE clock */ 691 __u32 eclk; 692 __u32 pad; 693 }; 694 695 struct drm_amdgpu_info_vce_clock_table { 696 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 697 __u32 num_valid_entries; 698 __u32 pad; 699 }; 700 701 /* 702 * Supported GPU families 703 */ 704 #define AMDGPU_FAMILY_UNKNOWN 0 705 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 706 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 707 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 708 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 709 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 710 711 #if defined(__cplusplus) 712 } 713 #endif 714 715 #endif 716