1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 55 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 56 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 57 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 58 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 59 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 60 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 61 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 62 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 63 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 64 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 65 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 66 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 67 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 68 69 #define AMDGPU_GEM_DOMAIN_CPU 0x1 70 #define AMDGPU_GEM_DOMAIN_GTT 0x2 71 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 72 #define AMDGPU_GEM_DOMAIN_GDS 0x8 73 #define AMDGPU_GEM_DOMAIN_GWS 0x10 74 #define AMDGPU_GEM_DOMAIN_OA 0x20 75 76 /* Flag that CPU access will be required for the case of VRAM domain */ 77 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 78 /* Flag that CPU access will not work, this VRAM domain is invisible */ 79 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 80 /* Flag that USWC attributes should be used for GTT */ 81 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 82 /* Flag that the memory should be in VRAM and cleared */ 83 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 84 /* Flag that create shadow bo(GTT) while allocating vram bo */ 85 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 86 /* Flag that allocating the BO should use linear VRAM */ 87 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 88 89 struct drm_amdgpu_gem_create_in { 90 /** the requested memory size */ 91 __u64 bo_size; 92 /** physical start_addr alignment in bytes for some HW requirements */ 93 __u64 alignment; 94 /** the requested memory domains */ 95 __u64 domains; 96 /** allocation flags */ 97 __u64 domain_flags; 98 }; 99 100 struct drm_amdgpu_gem_create_out { 101 /** returned GEM object handle */ 102 __u32 handle; 103 __u32 _pad; 104 }; 105 106 union drm_amdgpu_gem_create { 107 struct drm_amdgpu_gem_create_in in; 108 struct drm_amdgpu_gem_create_out out; 109 }; 110 111 /** Opcode to create new residency list. */ 112 #define AMDGPU_BO_LIST_OP_CREATE 0 113 /** Opcode to destroy previously created residency list */ 114 #define AMDGPU_BO_LIST_OP_DESTROY 1 115 /** Opcode to update resource information in the list */ 116 #define AMDGPU_BO_LIST_OP_UPDATE 2 117 118 struct drm_amdgpu_bo_list_in { 119 /** Type of operation */ 120 __u32 operation; 121 /** Handle of list or 0 if we want to create one */ 122 __u32 list_handle; 123 /** Number of BOs in list */ 124 __u32 bo_number; 125 /** Size of each element describing BO */ 126 __u32 bo_info_size; 127 /** Pointer to array describing BOs */ 128 __u64 bo_info_ptr; 129 }; 130 131 struct drm_amdgpu_bo_list_entry { 132 /** Handle of BO */ 133 __u32 bo_handle; 134 /** New (if specified) BO priority to be used during migration */ 135 __u32 bo_priority; 136 }; 137 138 struct drm_amdgpu_bo_list_out { 139 /** Handle of resource list */ 140 __u32 list_handle; 141 __u32 _pad; 142 }; 143 144 union drm_amdgpu_bo_list { 145 struct drm_amdgpu_bo_list_in in; 146 struct drm_amdgpu_bo_list_out out; 147 }; 148 149 /* context related */ 150 #define AMDGPU_CTX_OP_ALLOC_CTX 1 151 #define AMDGPU_CTX_OP_FREE_CTX 2 152 #define AMDGPU_CTX_OP_QUERY_STATE 3 153 154 /* GPU reset status */ 155 #define AMDGPU_CTX_NO_RESET 0 156 /* this the context caused it */ 157 #define AMDGPU_CTX_GUILTY_RESET 1 158 /* some other context caused it */ 159 #define AMDGPU_CTX_INNOCENT_RESET 2 160 /* unknown cause */ 161 #define AMDGPU_CTX_UNKNOWN_RESET 3 162 163 struct drm_amdgpu_ctx_in { 164 /** AMDGPU_CTX_OP_* */ 165 __u32 op; 166 /** For future use, no flags defined so far */ 167 __u32 flags; 168 __u32 ctx_id; 169 __u32 _pad; 170 }; 171 172 union drm_amdgpu_ctx_out { 173 struct { 174 __u32 ctx_id; 175 __u32 _pad; 176 } alloc; 177 178 struct { 179 /** For future use, no flags defined so far */ 180 __u64 flags; 181 /** Number of resets caused by this context so far. */ 182 __u32 hangs; 183 /** Reset status since the last call of the ioctl. */ 184 __u32 reset_status; 185 } state; 186 }; 187 188 union drm_amdgpu_ctx { 189 struct drm_amdgpu_ctx_in in; 190 union drm_amdgpu_ctx_out out; 191 }; 192 193 /* 194 * This is not a reliable API and you should expect it to fail for any 195 * number of reasons and have fallback path that do not use userptr to 196 * perform any operation. 197 */ 198 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 199 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 200 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 201 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 202 203 struct drm_amdgpu_gem_userptr { 204 __u64 addr; 205 __u64 size; 206 /* AMDGPU_GEM_USERPTR_* */ 207 __u32 flags; 208 /* Resulting GEM handle */ 209 __u32 handle; 210 }; 211 212 /* SI-CI-VI: */ 213 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 214 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 215 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 216 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 217 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 218 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 219 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 220 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 221 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 222 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 223 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 224 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 225 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 226 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 227 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 228 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 229 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 230 231 /* GFX9 and later: */ 232 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 233 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 234 235 /* Set/Get helpers for tiling flags. */ 236 #define AMDGPU_TILING_SET(field, value) \ 237 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 238 #define AMDGPU_TILING_GET(value, field) \ 239 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 240 241 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 242 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 243 244 /** The same structure is shared for input/output */ 245 struct drm_amdgpu_gem_metadata { 246 /** GEM Object handle */ 247 __u32 handle; 248 /** Do we want get or set metadata */ 249 __u32 op; 250 struct { 251 /** For future use, no flags defined so far */ 252 __u64 flags; 253 /** family specific tiling info */ 254 __u64 tiling_info; 255 __u32 data_size_bytes; 256 __u32 data[64]; 257 } data; 258 }; 259 260 struct drm_amdgpu_gem_mmap_in { 261 /** the GEM object handle */ 262 __u32 handle; 263 __u32 _pad; 264 }; 265 266 struct drm_amdgpu_gem_mmap_out { 267 /** mmap offset from the vma offset manager */ 268 __u64 addr_ptr; 269 }; 270 271 union drm_amdgpu_gem_mmap { 272 struct drm_amdgpu_gem_mmap_in in; 273 struct drm_amdgpu_gem_mmap_out out; 274 }; 275 276 struct drm_amdgpu_gem_wait_idle_in { 277 /** GEM object handle */ 278 __u32 handle; 279 /** For future use, no flags defined so far */ 280 __u32 flags; 281 /** Absolute timeout to wait */ 282 __u64 timeout; 283 }; 284 285 struct drm_amdgpu_gem_wait_idle_out { 286 /** BO status: 0 - BO is idle, 1 - BO is busy */ 287 __u32 status; 288 /** Returned current memory domain */ 289 __u32 domain; 290 }; 291 292 union drm_amdgpu_gem_wait_idle { 293 struct drm_amdgpu_gem_wait_idle_in in; 294 struct drm_amdgpu_gem_wait_idle_out out; 295 }; 296 297 struct drm_amdgpu_wait_cs_in { 298 /** Command submission handle */ 299 __u64 handle; 300 /** Absolute timeout to wait */ 301 __u64 timeout; 302 __u32 ip_type; 303 __u32 ip_instance; 304 __u32 ring; 305 __u32 ctx_id; 306 }; 307 308 struct drm_amdgpu_wait_cs_out { 309 /** CS status: 0 - CS completed, 1 - CS still busy */ 310 __u64 status; 311 }; 312 313 union drm_amdgpu_wait_cs { 314 struct drm_amdgpu_wait_cs_in in; 315 struct drm_amdgpu_wait_cs_out out; 316 }; 317 318 struct drm_amdgpu_fence { 319 __u32 ctx_id; 320 __u32 ip_type; 321 __u32 ip_instance; 322 __u32 ring; 323 __u64 seq_no; 324 }; 325 326 struct drm_amdgpu_wait_fences_in { 327 /** This points to uint64_t * which points to fences */ 328 __u64 fences; 329 __u32 fence_count; 330 __u32 wait_all; 331 __u64 timeout_ns; 332 }; 333 334 struct drm_amdgpu_wait_fences_out { 335 __u32 status; 336 __u32 first_signaled; 337 }; 338 339 union drm_amdgpu_wait_fences { 340 struct drm_amdgpu_wait_fences_in in; 341 struct drm_amdgpu_wait_fences_out out; 342 }; 343 344 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 345 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 346 347 /* Sets or returns a value associated with a buffer. */ 348 struct drm_amdgpu_gem_op { 349 /** GEM object handle */ 350 __u32 handle; 351 /** AMDGPU_GEM_OP_* */ 352 __u32 op; 353 /** Input or return value */ 354 __u64 value; 355 }; 356 357 #define AMDGPU_VA_OP_MAP 1 358 #define AMDGPU_VA_OP_UNMAP 2 359 #define AMDGPU_VA_OP_CLEAR 3 360 #define AMDGPU_VA_OP_REPLACE 4 361 362 /* Delay the page table update till the next CS */ 363 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 364 365 /* Mapping flags */ 366 /* readable mapping */ 367 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 368 /* writable mapping */ 369 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 370 /* executable mapping, new for VI */ 371 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 372 /* partially resident texture */ 373 #define AMDGPU_VM_PAGE_PRT (1 << 4) 374 /* MTYPE flags use bit 5 to 8 */ 375 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 376 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 377 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 378 /* Use NC MTYPE instead of default MTYPE */ 379 #define AMDGPU_VM_MTYPE_NC (1 << 5) 380 /* Use WC MTYPE instead of default MTYPE */ 381 #define AMDGPU_VM_MTYPE_WC (2 << 5) 382 /* Use CC MTYPE instead of default MTYPE */ 383 #define AMDGPU_VM_MTYPE_CC (3 << 5) 384 /* Use UC MTYPE instead of default MTYPE */ 385 #define AMDGPU_VM_MTYPE_UC (4 << 5) 386 387 struct drm_amdgpu_gem_va { 388 /** GEM object handle */ 389 __u32 handle; 390 __u32 _pad; 391 /** AMDGPU_VA_OP_* */ 392 __u32 operation; 393 /** AMDGPU_VM_PAGE_* */ 394 __u32 flags; 395 /** va address to assign . Must be correctly aligned.*/ 396 __u64 va_address; 397 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 398 __u64 offset_in_bo; 399 /** Specify mapping size. Must be correctly aligned. */ 400 __u64 map_size; 401 }; 402 403 #define AMDGPU_HW_IP_GFX 0 404 #define AMDGPU_HW_IP_COMPUTE 1 405 #define AMDGPU_HW_IP_DMA 2 406 #define AMDGPU_HW_IP_UVD 3 407 #define AMDGPU_HW_IP_VCE 4 408 #define AMDGPU_HW_IP_UVD_ENC 5 409 #define AMDGPU_HW_IP_NUM 6 410 411 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 412 413 #define AMDGPU_CHUNK_ID_IB 0x01 414 #define AMDGPU_CHUNK_ID_FENCE 0x02 415 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 416 417 struct drm_amdgpu_cs_chunk { 418 __u32 chunk_id; 419 __u32 length_dw; 420 __u64 chunk_data; 421 }; 422 423 struct drm_amdgpu_cs_in { 424 /** Rendering context id */ 425 __u32 ctx_id; 426 /** Handle of resource list associated with CS */ 427 __u32 bo_list_handle; 428 __u32 num_chunks; 429 __u32 _pad; 430 /** this points to __u64 * which point to cs chunks */ 431 __u64 chunks; 432 }; 433 434 struct drm_amdgpu_cs_out { 435 __u64 handle; 436 }; 437 438 union drm_amdgpu_cs { 439 struct drm_amdgpu_cs_in in; 440 struct drm_amdgpu_cs_out out; 441 }; 442 443 /* Specify flags to be used for IB */ 444 445 /* This IB should be submitted to CE */ 446 #define AMDGPU_IB_FLAG_CE (1<<0) 447 448 /* Preamble flag, which means the IB could be dropped if no context switch */ 449 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 450 451 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 452 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 453 454 struct drm_amdgpu_cs_chunk_ib { 455 __u32 _pad; 456 /** AMDGPU_IB_FLAG_* */ 457 __u32 flags; 458 /** Virtual address to begin IB execution */ 459 __u64 va_start; 460 /** Size of submission */ 461 __u32 ib_bytes; 462 /** HW IP to submit to */ 463 __u32 ip_type; 464 /** HW IP index of the same type to submit to */ 465 __u32 ip_instance; 466 /** Ring index to submit to */ 467 __u32 ring; 468 }; 469 470 struct drm_amdgpu_cs_chunk_dep { 471 __u32 ip_type; 472 __u32 ip_instance; 473 __u32 ring; 474 __u32 ctx_id; 475 __u64 handle; 476 }; 477 478 struct drm_amdgpu_cs_chunk_fence { 479 __u32 handle; 480 __u32 offset; 481 }; 482 483 struct drm_amdgpu_cs_chunk_data { 484 union { 485 struct drm_amdgpu_cs_chunk_ib ib_data; 486 struct drm_amdgpu_cs_chunk_fence fence_data; 487 }; 488 }; 489 490 /** 491 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 492 * 493 */ 494 #define AMDGPU_IDS_FLAGS_FUSION 0x1 495 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 496 497 /* indicate if acceleration can be working */ 498 #define AMDGPU_INFO_ACCEL_WORKING 0x00 499 /* get the crtc_id from the mode object id? */ 500 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 501 /* query hw IP info */ 502 #define AMDGPU_INFO_HW_IP_INFO 0x02 503 /* query hw IP instance count for the specified type */ 504 #define AMDGPU_INFO_HW_IP_COUNT 0x03 505 /* timestamp for GL_ARB_timer_query */ 506 #define AMDGPU_INFO_TIMESTAMP 0x05 507 /* Query the firmware version */ 508 #define AMDGPU_INFO_FW_VERSION 0x0e 509 /* Subquery id: Query VCE firmware version */ 510 #define AMDGPU_INFO_FW_VCE 0x1 511 /* Subquery id: Query UVD firmware version */ 512 #define AMDGPU_INFO_FW_UVD 0x2 513 /* Subquery id: Query GMC firmware version */ 514 #define AMDGPU_INFO_FW_GMC 0x03 515 /* Subquery id: Query GFX ME firmware version */ 516 #define AMDGPU_INFO_FW_GFX_ME 0x04 517 /* Subquery id: Query GFX PFP firmware version */ 518 #define AMDGPU_INFO_FW_GFX_PFP 0x05 519 /* Subquery id: Query GFX CE firmware version */ 520 #define AMDGPU_INFO_FW_GFX_CE 0x06 521 /* Subquery id: Query GFX RLC firmware version */ 522 #define AMDGPU_INFO_FW_GFX_RLC 0x07 523 /* Subquery id: Query GFX MEC firmware version */ 524 #define AMDGPU_INFO_FW_GFX_MEC 0x08 525 /* Subquery id: Query SMC firmware version */ 526 #define AMDGPU_INFO_FW_SMC 0x0a 527 /* Subquery id: Query SDMA firmware version */ 528 #define AMDGPU_INFO_FW_SDMA 0x0b 529 /* Subquery id: Query PSP SOS firmware version */ 530 #define AMDGPU_INFO_FW_SOS 0x0c 531 /* Subquery id: Query PSP ASD firmware version */ 532 #define AMDGPU_INFO_FW_ASD 0x0d 533 /* number of bytes moved for TTM migration */ 534 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 535 /* the used VRAM size */ 536 #define AMDGPU_INFO_VRAM_USAGE 0x10 537 /* the used GTT size */ 538 #define AMDGPU_INFO_GTT_USAGE 0x11 539 /* Information about GDS, etc. resource configuration */ 540 #define AMDGPU_INFO_GDS_CONFIG 0x13 541 /* Query information about VRAM and GTT domains */ 542 #define AMDGPU_INFO_VRAM_GTT 0x14 543 /* Query information about register in MMR address space*/ 544 #define AMDGPU_INFO_READ_MMR_REG 0x15 545 /* Query information about device: rev id, family, etc. */ 546 #define AMDGPU_INFO_DEV_INFO 0x16 547 /* visible vram usage */ 548 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 549 /* number of TTM buffer evictions */ 550 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 551 /* Query memory about VRAM and GTT domains */ 552 #define AMDGPU_INFO_MEMORY 0x19 553 /* Query vce clock table */ 554 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 555 /* Query vbios related information */ 556 #define AMDGPU_INFO_VBIOS 0x1B 557 /* Subquery id: Query vbios size */ 558 #define AMDGPU_INFO_VBIOS_SIZE 0x1 559 /* Subquery id: Query vbios image */ 560 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 561 /* Query UVD handles */ 562 #define AMDGPU_INFO_NUM_HANDLES 0x1C 563 /* Query sensor related information */ 564 #define AMDGPU_INFO_SENSOR 0x1D 565 /* Subquery id: Query GPU shader clock */ 566 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 567 /* Subquery id: Query GPU memory clock */ 568 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 569 /* Subquery id: Query GPU temperature */ 570 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 571 /* Subquery id: Query GPU load */ 572 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 573 /* Subquery id: Query average GPU power */ 574 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 575 /* Subquery id: Query northbridge voltage */ 576 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 577 /* Subquery id: Query graphics voltage */ 578 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 579 580 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 581 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 582 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 583 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 584 585 struct drm_amdgpu_query_fw { 586 /** AMDGPU_INFO_FW_* */ 587 __u32 fw_type; 588 /** 589 * Index of the IP if there are more IPs of 590 * the same type. 591 */ 592 __u32 ip_instance; 593 /** 594 * Index of the engine. Whether this is used depends 595 * on the firmware type. (e.g. MEC, SDMA) 596 */ 597 __u32 index; 598 __u32 _pad; 599 }; 600 601 /* Input structure for the INFO ioctl */ 602 struct drm_amdgpu_info { 603 /* Where the return value will be stored */ 604 __u64 return_pointer; 605 /* The size of the return value. Just like "size" in "snprintf", 606 * it limits how many bytes the kernel can write. */ 607 __u32 return_size; 608 /* The query request id. */ 609 __u32 query; 610 611 union { 612 struct { 613 __u32 id; 614 __u32 _pad; 615 } mode_crtc; 616 617 struct { 618 /** AMDGPU_HW_IP_* */ 619 __u32 type; 620 /** 621 * Index of the IP if there are more IPs of the same 622 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 623 */ 624 __u32 ip_instance; 625 } query_hw_ip; 626 627 struct { 628 __u32 dword_offset; 629 /** number of registers to read */ 630 __u32 count; 631 __u32 instance; 632 /** For future use, no flags defined so far */ 633 __u32 flags; 634 } read_mmr_reg; 635 636 struct drm_amdgpu_query_fw query_fw; 637 638 struct { 639 __u32 type; 640 __u32 offset; 641 } vbios_info; 642 643 struct { 644 __u32 type; 645 } sensor_info; 646 }; 647 }; 648 649 struct drm_amdgpu_info_gds { 650 /** GDS GFX partition size */ 651 __u32 gds_gfx_partition_size; 652 /** GDS compute partition size */ 653 __u32 compute_partition_size; 654 /** total GDS memory size */ 655 __u32 gds_total_size; 656 /** GWS size per GFX partition */ 657 __u32 gws_per_gfx_partition; 658 /** GSW size per compute partition */ 659 __u32 gws_per_compute_partition; 660 /** OA size per GFX partition */ 661 __u32 oa_per_gfx_partition; 662 /** OA size per compute partition */ 663 __u32 oa_per_compute_partition; 664 __u32 _pad; 665 }; 666 667 struct drm_amdgpu_info_vram_gtt { 668 __u64 vram_size; 669 __u64 vram_cpu_accessible_size; 670 __u64 gtt_size; 671 }; 672 673 struct drm_amdgpu_heap_info { 674 /** max. physical memory */ 675 __u64 total_heap_size; 676 677 /** Theoretical max. available memory in the given heap */ 678 __u64 usable_heap_size; 679 680 /** 681 * Number of bytes allocated in the heap. This includes all processes 682 * and private allocations in the kernel. It changes when new buffers 683 * are allocated, freed, and moved. It cannot be larger than 684 * heap_size. 685 */ 686 __u64 heap_usage; 687 688 /** 689 * Theoretical possible max. size of buffer which 690 * could be allocated in the given heap 691 */ 692 __u64 max_allocation; 693 }; 694 695 struct drm_amdgpu_memory_info { 696 struct drm_amdgpu_heap_info vram; 697 struct drm_amdgpu_heap_info cpu_accessible_vram; 698 struct drm_amdgpu_heap_info gtt; 699 }; 700 701 struct drm_amdgpu_info_firmware { 702 __u32 ver; 703 __u32 feature; 704 }; 705 706 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 707 #define AMDGPU_VRAM_TYPE_GDDR1 1 708 #define AMDGPU_VRAM_TYPE_DDR2 2 709 #define AMDGPU_VRAM_TYPE_GDDR3 3 710 #define AMDGPU_VRAM_TYPE_GDDR4 4 711 #define AMDGPU_VRAM_TYPE_GDDR5 5 712 #define AMDGPU_VRAM_TYPE_HBM 6 713 #define AMDGPU_VRAM_TYPE_DDR3 7 714 715 struct drm_amdgpu_info_device { 716 /** PCI Device ID */ 717 __u32 device_id; 718 /** Internal chip revision: A0, A1, etc.) */ 719 __u32 chip_rev; 720 __u32 external_rev; 721 /** Revision id in PCI Config space */ 722 __u32 pci_rev; 723 __u32 family; 724 __u32 num_shader_engines; 725 __u32 num_shader_arrays_per_engine; 726 /* in KHz */ 727 __u32 gpu_counter_freq; 728 __u64 max_engine_clock; 729 __u64 max_memory_clock; 730 /* cu information */ 731 __u32 cu_active_number; 732 __u32 cu_ao_mask; 733 __u32 cu_bitmap[4][4]; 734 /** Render backend pipe mask. One render backend is CB+DB. */ 735 __u32 enabled_rb_pipes_mask; 736 __u32 num_rb_pipes; 737 __u32 num_hw_gfx_contexts; 738 __u32 _pad; 739 __u64 ids_flags; 740 /** Starting virtual address for UMDs. */ 741 __u64 virtual_address_offset; 742 /** The maximum virtual address */ 743 __u64 virtual_address_max; 744 /** Required alignment of virtual addresses. */ 745 __u32 virtual_address_alignment; 746 /** Page table entry - fragment size */ 747 __u32 pte_fragment_size; 748 __u32 gart_page_size; 749 /** constant engine ram size*/ 750 __u32 ce_ram_size; 751 /** video memory type info*/ 752 __u32 vram_type; 753 /** video memory bit width*/ 754 __u32 vram_bit_width; 755 /* vce harvesting instance */ 756 __u32 vce_harvest_config; 757 /* gfx double offchip LDS buffers */ 758 __u32 gc_double_offchip_lds_buf; 759 /* NGG Primitive Buffer */ 760 __u64 prim_buf_gpu_addr; 761 /* NGG Position Buffer */ 762 __u64 pos_buf_gpu_addr; 763 /* NGG Control Sideband */ 764 __u64 cntl_sb_buf_gpu_addr; 765 /* NGG Parameter Cache */ 766 __u64 param_buf_gpu_addr; 767 }; 768 769 struct drm_amdgpu_info_hw_ip { 770 /** Version of h/w IP */ 771 __u32 hw_ip_version_major; 772 __u32 hw_ip_version_minor; 773 /** Capabilities */ 774 __u64 capabilities_flags; 775 /** command buffer address start alignment*/ 776 __u32 ib_start_alignment; 777 /** command buffer size alignment*/ 778 __u32 ib_size_alignment; 779 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 780 __u32 available_rings; 781 __u32 _pad; 782 }; 783 784 struct drm_amdgpu_info_num_handles { 785 /** Max handles as supported by firmware for UVD */ 786 __u32 uvd_max_handles; 787 /** Handles currently in use for UVD */ 788 __u32 uvd_used_handles; 789 }; 790 791 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 792 793 struct drm_amdgpu_info_vce_clock_table_entry { 794 /** System clock */ 795 __u32 sclk; 796 /** Memory clock */ 797 __u32 mclk; 798 /** VCE clock */ 799 __u32 eclk; 800 __u32 pad; 801 }; 802 803 struct drm_amdgpu_info_vce_clock_table { 804 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 805 __u32 num_valid_entries; 806 __u32 pad; 807 }; 808 809 /* 810 * Supported GPU families 811 */ 812 #define AMDGPU_FAMILY_UNKNOWN 0 813 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 814 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 815 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 816 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 817 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 818 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 819 820 #if defined(__cplusplus) 821 } 822 #endif 823 824 #endif 825