1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linezrized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that create shadow bo(GTT) while allocating vram bo */ 120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 121 /* Flag that allocating the BO should use linear VRAM */ 122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123 /* Flag that BO is always valid in this VM */ 124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125 /* Flag that BO sharing will be explicitly synchronized */ 126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128 * for the second page onward should be set to NC. It should never 129 * be used by user space applications. 130 */ 131 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 132 /* Flag that BO may contain sensitive data that must be wiped before 133 * releasing the memory 134 */ 135 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 136 137 struct drm_amdgpu_gem_create_in { 138 /** the requested memory size */ 139 __u64 bo_size; 140 /** physical start_addr alignment in bytes for some HW requirements */ 141 __u64 alignment; 142 /** the requested memory domains */ 143 __u64 domains; 144 /** allocation flags */ 145 __u64 domain_flags; 146 }; 147 148 struct drm_amdgpu_gem_create_out { 149 /** returned GEM object handle */ 150 __u32 handle; 151 __u32 _pad; 152 }; 153 154 union drm_amdgpu_gem_create { 155 struct drm_amdgpu_gem_create_in in; 156 struct drm_amdgpu_gem_create_out out; 157 }; 158 159 /** Opcode to create new residency list. */ 160 #define AMDGPU_BO_LIST_OP_CREATE 0 161 /** Opcode to destroy previously created residency list */ 162 #define AMDGPU_BO_LIST_OP_DESTROY 1 163 /** Opcode to update resource information in the list */ 164 #define AMDGPU_BO_LIST_OP_UPDATE 2 165 166 struct drm_amdgpu_bo_list_in { 167 /** Type of operation */ 168 __u32 operation; 169 /** Handle of list or 0 if we want to create one */ 170 __u32 list_handle; 171 /** Number of BOs in list */ 172 __u32 bo_number; 173 /** Size of each element describing BO */ 174 __u32 bo_info_size; 175 /** Pointer to array describing BOs */ 176 __u64 bo_info_ptr; 177 }; 178 179 struct drm_amdgpu_bo_list_entry { 180 /** Handle of BO */ 181 __u32 bo_handle; 182 /** New (if specified) BO priority to be used during migration */ 183 __u32 bo_priority; 184 }; 185 186 struct drm_amdgpu_bo_list_out { 187 /** Handle of resource list */ 188 __u32 list_handle; 189 __u32 _pad; 190 }; 191 192 union drm_amdgpu_bo_list { 193 struct drm_amdgpu_bo_list_in in; 194 struct drm_amdgpu_bo_list_out out; 195 }; 196 197 /* context related */ 198 #define AMDGPU_CTX_OP_ALLOC_CTX 1 199 #define AMDGPU_CTX_OP_FREE_CTX 2 200 #define AMDGPU_CTX_OP_QUERY_STATE 3 201 #define AMDGPU_CTX_OP_QUERY_STATE2 4 202 203 /* GPU reset status */ 204 #define AMDGPU_CTX_NO_RESET 0 205 /* this the context caused it */ 206 #define AMDGPU_CTX_GUILTY_RESET 1 207 /* some other context caused it */ 208 #define AMDGPU_CTX_INNOCENT_RESET 2 209 /* unknown cause */ 210 #define AMDGPU_CTX_UNKNOWN_RESET 3 211 212 /* indicate gpu reset occured after ctx created */ 213 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 214 /* indicate vram lost occured after ctx created */ 215 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 216 /* indicate some job from this context once cause gpu hang */ 217 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 218 /* indicate some errors are detected by RAS */ 219 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 220 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 221 222 /* Context priority level */ 223 #define AMDGPU_CTX_PRIORITY_UNSET -2048 224 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 225 #define AMDGPU_CTX_PRIORITY_LOW -512 226 #define AMDGPU_CTX_PRIORITY_NORMAL 0 227 /* 228 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 229 * CAP_SYS_NICE or DRM_MASTER 230 */ 231 #define AMDGPU_CTX_PRIORITY_HIGH 512 232 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 233 234 struct drm_amdgpu_ctx_in { 235 /** AMDGPU_CTX_OP_* */ 236 __u32 op; 237 /** For future use, no flags defined so far */ 238 __u32 flags; 239 __u32 ctx_id; 240 /** AMDGPU_CTX_PRIORITY_* */ 241 __s32 priority; 242 }; 243 244 union drm_amdgpu_ctx_out { 245 struct { 246 __u32 ctx_id; 247 __u32 _pad; 248 } alloc; 249 250 struct { 251 /** For future use, no flags defined so far */ 252 __u64 flags; 253 /** Number of resets caused by this context so far. */ 254 __u32 hangs; 255 /** Reset status since the last call of the ioctl. */ 256 __u32 reset_status; 257 } state; 258 }; 259 260 union drm_amdgpu_ctx { 261 struct drm_amdgpu_ctx_in in; 262 union drm_amdgpu_ctx_out out; 263 }; 264 265 /* vm ioctl */ 266 #define AMDGPU_VM_OP_RESERVE_VMID 1 267 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 268 269 struct drm_amdgpu_vm_in { 270 /** AMDGPU_VM_OP_* */ 271 __u32 op; 272 __u32 flags; 273 }; 274 275 struct drm_amdgpu_vm_out { 276 /** For future use, no flags defined so far */ 277 __u64 flags; 278 }; 279 280 union drm_amdgpu_vm { 281 struct drm_amdgpu_vm_in in; 282 struct drm_amdgpu_vm_out out; 283 }; 284 285 /* sched ioctl */ 286 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 287 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 288 289 struct drm_amdgpu_sched_in { 290 /* AMDGPU_SCHED_OP_* */ 291 __u32 op; 292 __u32 fd; 293 /** AMDGPU_CTX_PRIORITY_* */ 294 __s32 priority; 295 __u32 ctx_id; 296 }; 297 298 union drm_amdgpu_sched { 299 struct drm_amdgpu_sched_in in; 300 }; 301 302 /* 303 * This is not a reliable API and you should expect it to fail for any 304 * number of reasons and have fallback path that do not use userptr to 305 * perform any operation. 306 */ 307 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 308 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 309 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 310 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 311 312 struct drm_amdgpu_gem_userptr { 313 __u64 addr; 314 __u64 size; 315 /* AMDGPU_GEM_USERPTR_* */ 316 __u32 flags; 317 /* Resulting GEM handle */ 318 __u32 handle; 319 }; 320 321 /* SI-CI-VI: */ 322 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 323 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 324 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 325 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 326 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 327 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 328 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 329 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 330 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 331 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 332 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 333 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 334 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 335 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 336 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 337 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 338 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 339 340 /* GFX9 and later: */ 341 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 342 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 343 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 344 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 345 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 346 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 347 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 348 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 349 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 350 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 351 #define AMDGPU_TILING_SCANOUT_SHIFT 63 352 #define AMDGPU_TILING_SCANOUT_MASK 0x1 353 354 /* Set/Get helpers for tiling flags. */ 355 #define AMDGPU_TILING_SET(field, value) \ 356 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 357 #define AMDGPU_TILING_GET(value, field) \ 358 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 359 360 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 361 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 362 363 /** The same structure is shared for input/output */ 364 struct drm_amdgpu_gem_metadata { 365 /** GEM Object handle */ 366 __u32 handle; 367 /** Do we want get or set metadata */ 368 __u32 op; 369 struct { 370 /** For future use, no flags defined so far */ 371 __u64 flags; 372 /** family specific tiling info */ 373 __u64 tiling_info; 374 __u32 data_size_bytes; 375 __u32 data[64]; 376 } data; 377 }; 378 379 struct drm_amdgpu_gem_mmap_in { 380 /** the GEM object handle */ 381 __u32 handle; 382 __u32 _pad; 383 }; 384 385 struct drm_amdgpu_gem_mmap_out { 386 /** mmap offset from the vma offset manager */ 387 __u64 addr_ptr; 388 }; 389 390 union drm_amdgpu_gem_mmap { 391 struct drm_amdgpu_gem_mmap_in in; 392 struct drm_amdgpu_gem_mmap_out out; 393 }; 394 395 struct drm_amdgpu_gem_wait_idle_in { 396 /** GEM object handle */ 397 __u32 handle; 398 /** For future use, no flags defined so far */ 399 __u32 flags; 400 /** Absolute timeout to wait */ 401 __u64 timeout; 402 }; 403 404 struct drm_amdgpu_gem_wait_idle_out { 405 /** BO status: 0 - BO is idle, 1 - BO is busy */ 406 __u32 status; 407 /** Returned current memory domain */ 408 __u32 domain; 409 }; 410 411 union drm_amdgpu_gem_wait_idle { 412 struct drm_amdgpu_gem_wait_idle_in in; 413 struct drm_amdgpu_gem_wait_idle_out out; 414 }; 415 416 struct drm_amdgpu_wait_cs_in { 417 /* Command submission handle 418 * handle equals 0 means none to wait for 419 * handle equals ~0ull means wait for the latest sequence number 420 */ 421 __u64 handle; 422 /** Absolute timeout to wait */ 423 __u64 timeout; 424 __u32 ip_type; 425 __u32 ip_instance; 426 __u32 ring; 427 __u32 ctx_id; 428 }; 429 430 struct drm_amdgpu_wait_cs_out { 431 /** CS status: 0 - CS completed, 1 - CS still busy */ 432 __u64 status; 433 }; 434 435 union drm_amdgpu_wait_cs { 436 struct drm_amdgpu_wait_cs_in in; 437 struct drm_amdgpu_wait_cs_out out; 438 }; 439 440 struct drm_amdgpu_fence { 441 __u32 ctx_id; 442 __u32 ip_type; 443 __u32 ip_instance; 444 __u32 ring; 445 __u64 seq_no; 446 }; 447 448 struct drm_amdgpu_wait_fences_in { 449 /** This points to uint64_t * which points to fences */ 450 __u64 fences; 451 __u32 fence_count; 452 __u32 wait_all; 453 __u64 timeout_ns; 454 }; 455 456 struct drm_amdgpu_wait_fences_out { 457 __u32 status; 458 __u32 first_signaled; 459 }; 460 461 union drm_amdgpu_wait_fences { 462 struct drm_amdgpu_wait_fences_in in; 463 struct drm_amdgpu_wait_fences_out out; 464 }; 465 466 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 467 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 468 469 /* Sets or returns a value associated with a buffer. */ 470 struct drm_amdgpu_gem_op { 471 /** GEM object handle */ 472 __u32 handle; 473 /** AMDGPU_GEM_OP_* */ 474 __u32 op; 475 /** Input or return value */ 476 __u64 value; 477 }; 478 479 #define AMDGPU_VA_OP_MAP 1 480 #define AMDGPU_VA_OP_UNMAP 2 481 #define AMDGPU_VA_OP_CLEAR 3 482 #define AMDGPU_VA_OP_REPLACE 4 483 484 /* Delay the page table update till the next CS */ 485 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 486 487 /* Mapping flags */ 488 /* readable mapping */ 489 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 490 /* writable mapping */ 491 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 492 /* executable mapping, new for VI */ 493 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 494 /* partially resident texture */ 495 #define AMDGPU_VM_PAGE_PRT (1 << 4) 496 /* MTYPE flags use bit 5 to 8 */ 497 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 498 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 499 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 500 /* Use NC MTYPE instead of default MTYPE */ 501 #define AMDGPU_VM_MTYPE_NC (1 << 5) 502 /* Use WC MTYPE instead of default MTYPE */ 503 #define AMDGPU_VM_MTYPE_WC (2 << 5) 504 /* Use CC MTYPE instead of default MTYPE */ 505 #define AMDGPU_VM_MTYPE_CC (3 << 5) 506 /* Use UC MTYPE instead of default MTYPE */ 507 #define AMDGPU_VM_MTYPE_UC (4 << 5) 508 /* Use RW MTYPE instead of default MTYPE */ 509 #define AMDGPU_VM_MTYPE_RW (5 << 5) 510 511 struct drm_amdgpu_gem_va { 512 /** GEM object handle */ 513 __u32 handle; 514 __u32 _pad; 515 /** AMDGPU_VA_OP_* */ 516 __u32 operation; 517 /** AMDGPU_VM_PAGE_* */ 518 __u32 flags; 519 /** va address to assign . Must be correctly aligned.*/ 520 __u64 va_address; 521 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 522 __u64 offset_in_bo; 523 /** Specify mapping size. Must be correctly aligned. */ 524 __u64 map_size; 525 }; 526 527 #define AMDGPU_HW_IP_GFX 0 528 #define AMDGPU_HW_IP_COMPUTE 1 529 #define AMDGPU_HW_IP_DMA 2 530 #define AMDGPU_HW_IP_UVD 3 531 #define AMDGPU_HW_IP_VCE 4 532 #define AMDGPU_HW_IP_UVD_ENC 5 533 #define AMDGPU_HW_IP_VCN_DEC 6 534 #define AMDGPU_HW_IP_VCN_ENC 7 535 #define AMDGPU_HW_IP_VCN_JPEG 8 536 #define AMDGPU_HW_IP_NUM 9 537 538 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 539 540 #define AMDGPU_CHUNK_ID_IB 0x01 541 #define AMDGPU_CHUNK_ID_FENCE 0x02 542 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 543 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 544 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 545 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 546 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 547 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 548 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 549 550 struct drm_amdgpu_cs_chunk { 551 __u32 chunk_id; 552 __u32 length_dw; 553 __u64 chunk_data; 554 }; 555 556 struct drm_amdgpu_cs_in { 557 /** Rendering context id */ 558 __u32 ctx_id; 559 /** Handle of resource list associated with CS */ 560 __u32 bo_list_handle; 561 __u32 num_chunks; 562 __u32 _pad; 563 /** this points to __u64 * which point to cs chunks */ 564 __u64 chunks; 565 }; 566 567 struct drm_amdgpu_cs_out { 568 __u64 handle; 569 }; 570 571 union drm_amdgpu_cs { 572 struct drm_amdgpu_cs_in in; 573 struct drm_amdgpu_cs_out out; 574 }; 575 576 /* Specify flags to be used for IB */ 577 578 /* This IB should be submitted to CE */ 579 #define AMDGPU_IB_FLAG_CE (1<<0) 580 581 /* Preamble flag, which means the IB could be dropped if no context switch */ 582 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 583 584 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 585 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 586 587 /* The IB fence should do the L2 writeback but not invalidate any shader 588 * caches (L2/vL1/sL1/I$). */ 589 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 590 591 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 592 * This will reset wave ID counters for the IB. 593 */ 594 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 595 596 struct drm_amdgpu_cs_chunk_ib { 597 __u32 _pad; 598 /** AMDGPU_IB_FLAG_* */ 599 __u32 flags; 600 /** Virtual address to begin IB execution */ 601 __u64 va_start; 602 /** Size of submission */ 603 __u32 ib_bytes; 604 /** HW IP to submit to */ 605 __u32 ip_type; 606 /** HW IP index of the same type to submit to */ 607 __u32 ip_instance; 608 /** Ring index to submit to */ 609 __u32 ring; 610 }; 611 612 struct drm_amdgpu_cs_chunk_dep { 613 __u32 ip_type; 614 __u32 ip_instance; 615 __u32 ring; 616 __u32 ctx_id; 617 __u64 handle; 618 }; 619 620 struct drm_amdgpu_cs_chunk_fence { 621 __u32 handle; 622 __u32 offset; 623 }; 624 625 struct drm_amdgpu_cs_chunk_sem { 626 __u32 handle; 627 }; 628 629 struct drm_amdgpu_cs_chunk_syncobj { 630 __u32 handle; 631 __u32 flags; 632 __u64 point; 633 }; 634 635 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 636 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 637 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 638 639 union drm_amdgpu_fence_to_handle { 640 struct { 641 struct drm_amdgpu_fence fence; 642 __u32 what; 643 __u32 pad; 644 } in; 645 struct { 646 __u32 handle; 647 } out; 648 }; 649 650 struct drm_amdgpu_cs_chunk_data { 651 union { 652 struct drm_amdgpu_cs_chunk_ib ib_data; 653 struct drm_amdgpu_cs_chunk_fence fence_data; 654 }; 655 }; 656 657 /** 658 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 659 * 660 */ 661 #define AMDGPU_IDS_FLAGS_FUSION 0x1 662 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 663 664 /* indicate if acceleration can be working */ 665 #define AMDGPU_INFO_ACCEL_WORKING 0x00 666 /* get the crtc_id from the mode object id? */ 667 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 668 /* query hw IP info */ 669 #define AMDGPU_INFO_HW_IP_INFO 0x02 670 /* query hw IP instance count for the specified type */ 671 #define AMDGPU_INFO_HW_IP_COUNT 0x03 672 /* timestamp for GL_ARB_timer_query */ 673 #define AMDGPU_INFO_TIMESTAMP 0x05 674 /* Query the firmware version */ 675 #define AMDGPU_INFO_FW_VERSION 0x0e 676 /* Subquery id: Query VCE firmware version */ 677 #define AMDGPU_INFO_FW_VCE 0x1 678 /* Subquery id: Query UVD firmware version */ 679 #define AMDGPU_INFO_FW_UVD 0x2 680 /* Subquery id: Query GMC firmware version */ 681 #define AMDGPU_INFO_FW_GMC 0x03 682 /* Subquery id: Query GFX ME firmware version */ 683 #define AMDGPU_INFO_FW_GFX_ME 0x04 684 /* Subquery id: Query GFX PFP firmware version */ 685 #define AMDGPU_INFO_FW_GFX_PFP 0x05 686 /* Subquery id: Query GFX CE firmware version */ 687 #define AMDGPU_INFO_FW_GFX_CE 0x06 688 /* Subquery id: Query GFX RLC firmware version */ 689 #define AMDGPU_INFO_FW_GFX_RLC 0x07 690 /* Subquery id: Query GFX MEC firmware version */ 691 #define AMDGPU_INFO_FW_GFX_MEC 0x08 692 /* Subquery id: Query SMC firmware version */ 693 #define AMDGPU_INFO_FW_SMC 0x0a 694 /* Subquery id: Query SDMA firmware version */ 695 #define AMDGPU_INFO_FW_SDMA 0x0b 696 /* Subquery id: Query PSP SOS firmware version */ 697 #define AMDGPU_INFO_FW_SOS 0x0c 698 /* Subquery id: Query PSP ASD firmware version */ 699 #define AMDGPU_INFO_FW_ASD 0x0d 700 /* Subquery id: Query VCN firmware version */ 701 #define AMDGPU_INFO_FW_VCN 0x0e 702 /* Subquery id: Query GFX RLC SRLC firmware version */ 703 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 704 /* Subquery id: Query GFX RLC SRLG firmware version */ 705 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 706 /* Subquery id: Query GFX RLC SRLS firmware version */ 707 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 708 /* Subquery id: Query DMCU firmware version */ 709 #define AMDGPU_INFO_FW_DMCU 0x12 710 #define AMDGPU_INFO_FW_TA 0x13 711 /* Subquery id: Query DMCUB firmware version */ 712 #define AMDGPU_INFO_FW_DMCUB 0x14 713 714 /* number of bytes moved for TTM migration */ 715 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 716 /* the used VRAM size */ 717 #define AMDGPU_INFO_VRAM_USAGE 0x10 718 /* the used GTT size */ 719 #define AMDGPU_INFO_GTT_USAGE 0x11 720 /* Information about GDS, etc. resource configuration */ 721 #define AMDGPU_INFO_GDS_CONFIG 0x13 722 /* Query information about VRAM and GTT domains */ 723 #define AMDGPU_INFO_VRAM_GTT 0x14 724 /* Query information about register in MMR address space*/ 725 #define AMDGPU_INFO_READ_MMR_REG 0x15 726 /* Query information about device: rev id, family, etc. */ 727 #define AMDGPU_INFO_DEV_INFO 0x16 728 /* visible vram usage */ 729 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 730 /* number of TTM buffer evictions */ 731 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 732 /* Query memory about VRAM and GTT domains */ 733 #define AMDGPU_INFO_MEMORY 0x19 734 /* Query vce clock table */ 735 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 736 /* Query vbios related information */ 737 #define AMDGPU_INFO_VBIOS 0x1B 738 /* Subquery id: Query vbios size */ 739 #define AMDGPU_INFO_VBIOS_SIZE 0x1 740 /* Subquery id: Query vbios image */ 741 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 742 /* Query UVD handles */ 743 #define AMDGPU_INFO_NUM_HANDLES 0x1C 744 /* Query sensor related information */ 745 #define AMDGPU_INFO_SENSOR 0x1D 746 /* Subquery id: Query GPU shader clock */ 747 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 748 /* Subquery id: Query GPU memory clock */ 749 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 750 /* Subquery id: Query GPU temperature */ 751 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 752 /* Subquery id: Query GPU load */ 753 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 754 /* Subquery id: Query average GPU power */ 755 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 756 /* Subquery id: Query northbridge voltage */ 757 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 758 /* Subquery id: Query graphics voltage */ 759 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 760 /* Subquery id: Query GPU stable pstate shader clock */ 761 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 762 /* Subquery id: Query GPU stable pstate memory clock */ 763 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 764 /* Number of VRAM page faults on CPU access. */ 765 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 766 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 767 /* query ras mask of enabled features*/ 768 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 769 770 /* RAS MASK: UMC (VRAM) */ 771 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 772 /* RAS MASK: SDMA */ 773 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 774 /* RAS MASK: GFX */ 775 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 776 /* RAS MASK: MMHUB */ 777 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 778 /* RAS MASK: ATHUB */ 779 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 780 /* RAS MASK: PCIE */ 781 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 782 /* RAS MASK: HDP */ 783 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 784 /* RAS MASK: XGMI */ 785 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 786 /* RAS MASK: DF */ 787 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 788 /* RAS MASK: SMN */ 789 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 790 /* RAS MASK: SEM */ 791 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 792 /* RAS MASK: MP0 */ 793 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 794 /* RAS MASK: MP1 */ 795 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 796 /* RAS MASK: FUSE */ 797 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 798 799 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 800 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 801 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 802 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 803 804 struct drm_amdgpu_query_fw { 805 /** AMDGPU_INFO_FW_* */ 806 __u32 fw_type; 807 /** 808 * Index of the IP if there are more IPs of 809 * the same type. 810 */ 811 __u32 ip_instance; 812 /** 813 * Index of the engine. Whether this is used depends 814 * on the firmware type. (e.g. MEC, SDMA) 815 */ 816 __u32 index; 817 __u32 _pad; 818 }; 819 820 /* Input structure for the INFO ioctl */ 821 struct drm_amdgpu_info { 822 /* Where the return value will be stored */ 823 __u64 return_pointer; 824 /* The size of the return value. Just like "size" in "snprintf", 825 * it limits how many bytes the kernel can write. */ 826 __u32 return_size; 827 /* The query request id. */ 828 __u32 query; 829 830 union { 831 struct { 832 __u32 id; 833 __u32 _pad; 834 } mode_crtc; 835 836 struct { 837 /** AMDGPU_HW_IP_* */ 838 __u32 type; 839 /** 840 * Index of the IP if there are more IPs of the same 841 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 842 */ 843 __u32 ip_instance; 844 } query_hw_ip; 845 846 struct { 847 __u32 dword_offset; 848 /** number of registers to read */ 849 __u32 count; 850 __u32 instance; 851 /** For future use, no flags defined so far */ 852 __u32 flags; 853 } read_mmr_reg; 854 855 struct drm_amdgpu_query_fw query_fw; 856 857 struct { 858 __u32 type; 859 __u32 offset; 860 } vbios_info; 861 862 struct { 863 __u32 type; 864 } sensor_info; 865 }; 866 }; 867 868 struct drm_amdgpu_info_gds { 869 /** GDS GFX partition size */ 870 __u32 gds_gfx_partition_size; 871 /** GDS compute partition size */ 872 __u32 compute_partition_size; 873 /** total GDS memory size */ 874 __u32 gds_total_size; 875 /** GWS size per GFX partition */ 876 __u32 gws_per_gfx_partition; 877 /** GSW size per compute partition */ 878 __u32 gws_per_compute_partition; 879 /** OA size per GFX partition */ 880 __u32 oa_per_gfx_partition; 881 /** OA size per compute partition */ 882 __u32 oa_per_compute_partition; 883 __u32 _pad; 884 }; 885 886 struct drm_amdgpu_info_vram_gtt { 887 __u64 vram_size; 888 __u64 vram_cpu_accessible_size; 889 __u64 gtt_size; 890 }; 891 892 struct drm_amdgpu_heap_info { 893 /** max. physical memory */ 894 __u64 total_heap_size; 895 896 /** Theoretical max. available memory in the given heap */ 897 __u64 usable_heap_size; 898 899 /** 900 * Number of bytes allocated in the heap. This includes all processes 901 * and private allocations in the kernel. It changes when new buffers 902 * are allocated, freed, and moved. It cannot be larger than 903 * heap_size. 904 */ 905 __u64 heap_usage; 906 907 /** 908 * Theoretical possible max. size of buffer which 909 * could be allocated in the given heap 910 */ 911 __u64 max_allocation; 912 }; 913 914 struct drm_amdgpu_memory_info { 915 struct drm_amdgpu_heap_info vram; 916 struct drm_amdgpu_heap_info cpu_accessible_vram; 917 struct drm_amdgpu_heap_info gtt; 918 }; 919 920 struct drm_amdgpu_info_firmware { 921 __u32 ver; 922 __u32 feature; 923 }; 924 925 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 926 #define AMDGPU_VRAM_TYPE_GDDR1 1 927 #define AMDGPU_VRAM_TYPE_DDR2 2 928 #define AMDGPU_VRAM_TYPE_GDDR3 3 929 #define AMDGPU_VRAM_TYPE_GDDR4 4 930 #define AMDGPU_VRAM_TYPE_GDDR5 5 931 #define AMDGPU_VRAM_TYPE_HBM 6 932 #define AMDGPU_VRAM_TYPE_DDR3 7 933 #define AMDGPU_VRAM_TYPE_DDR4 8 934 #define AMDGPU_VRAM_TYPE_GDDR6 9 935 936 struct drm_amdgpu_info_device { 937 /** PCI Device ID */ 938 __u32 device_id; 939 /** Internal chip revision: A0, A1, etc.) */ 940 __u32 chip_rev; 941 __u32 external_rev; 942 /** Revision id in PCI Config space */ 943 __u32 pci_rev; 944 __u32 family; 945 __u32 num_shader_engines; 946 __u32 num_shader_arrays_per_engine; 947 /* in KHz */ 948 __u32 gpu_counter_freq; 949 __u64 max_engine_clock; 950 __u64 max_memory_clock; 951 /* cu information */ 952 __u32 cu_active_number; 953 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 954 __u32 cu_ao_mask; 955 __u32 cu_bitmap[4][4]; 956 /** Render backend pipe mask. One render backend is CB+DB. */ 957 __u32 enabled_rb_pipes_mask; 958 __u32 num_rb_pipes; 959 __u32 num_hw_gfx_contexts; 960 __u32 _pad; 961 __u64 ids_flags; 962 /** Starting virtual address for UMDs. */ 963 __u64 virtual_address_offset; 964 /** The maximum virtual address */ 965 __u64 virtual_address_max; 966 /** Required alignment of virtual addresses. */ 967 __u32 virtual_address_alignment; 968 /** Page table entry - fragment size */ 969 __u32 pte_fragment_size; 970 __u32 gart_page_size; 971 /** constant engine ram size*/ 972 __u32 ce_ram_size; 973 /** video memory type info*/ 974 __u32 vram_type; 975 /** video memory bit width*/ 976 __u32 vram_bit_width; 977 /* vce harvesting instance */ 978 __u32 vce_harvest_config; 979 /* gfx double offchip LDS buffers */ 980 __u32 gc_double_offchip_lds_buf; 981 /* NGG Primitive Buffer */ 982 __u64 prim_buf_gpu_addr; 983 /* NGG Position Buffer */ 984 __u64 pos_buf_gpu_addr; 985 /* NGG Control Sideband */ 986 __u64 cntl_sb_buf_gpu_addr; 987 /* NGG Parameter Cache */ 988 __u64 param_buf_gpu_addr; 989 __u32 prim_buf_size; 990 __u32 pos_buf_size; 991 __u32 cntl_sb_buf_size; 992 __u32 param_buf_size; 993 /* wavefront size*/ 994 __u32 wave_front_size; 995 /* shader visible vgprs*/ 996 __u32 num_shader_visible_vgprs; 997 /* CU per shader array*/ 998 __u32 num_cu_per_sh; 999 /* number of tcc blocks*/ 1000 __u32 num_tcc_blocks; 1001 /* gs vgt table depth*/ 1002 __u32 gs_vgt_table_depth; 1003 /* gs primitive buffer depth*/ 1004 __u32 gs_prim_buffer_depth; 1005 /* max gs wavefront per vgt*/ 1006 __u32 max_gs_waves_per_vgt; 1007 __u32 _pad1; 1008 /* always on cu bitmap */ 1009 __u32 cu_ao_bitmap[4][4]; 1010 /** Starting high virtual address for UMDs. */ 1011 __u64 high_va_offset; 1012 /** The maximum high virtual address */ 1013 __u64 high_va_max; 1014 /* gfx10 pa_sc_tile_steering_override */ 1015 __u32 pa_sc_tile_steering_override; 1016 /* disabled TCCs */ 1017 __u64 tcc_disabled_mask; 1018 }; 1019 1020 struct drm_amdgpu_info_hw_ip { 1021 /** Version of h/w IP */ 1022 __u32 hw_ip_version_major; 1023 __u32 hw_ip_version_minor; 1024 /** Capabilities */ 1025 __u64 capabilities_flags; 1026 /** command buffer address start alignment*/ 1027 __u32 ib_start_alignment; 1028 /** command buffer size alignment*/ 1029 __u32 ib_size_alignment; 1030 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1031 __u32 available_rings; 1032 __u32 _pad; 1033 }; 1034 1035 struct drm_amdgpu_info_num_handles { 1036 /** Max handles as supported by firmware for UVD */ 1037 __u32 uvd_max_handles; 1038 /** Handles currently in use for UVD */ 1039 __u32 uvd_used_handles; 1040 }; 1041 1042 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1043 1044 struct drm_amdgpu_info_vce_clock_table_entry { 1045 /** System clock */ 1046 __u32 sclk; 1047 /** Memory clock */ 1048 __u32 mclk; 1049 /** VCE clock */ 1050 __u32 eclk; 1051 __u32 pad; 1052 }; 1053 1054 struct drm_amdgpu_info_vce_clock_table { 1055 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1056 __u32 num_valid_entries; 1057 __u32 pad; 1058 }; 1059 1060 /* 1061 * Supported GPU families 1062 */ 1063 #define AMDGPU_FAMILY_UNKNOWN 0 1064 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1065 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1066 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1067 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1068 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1069 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1070 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1071 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1072 1073 #if defined(__cplusplus) 1074 } 1075 #endif 1076 1077 #endif 1078