1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 #define AMDGPU_GEM_DOMAIN_CPU 0x1 76 #define AMDGPU_GEM_DOMAIN_GTT 0x2 77 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 78 #define AMDGPU_GEM_DOMAIN_GDS 0x8 79 #define AMDGPU_GEM_DOMAIN_GWS 0x10 80 #define AMDGPU_GEM_DOMAIN_OA 0x20 81 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 82 AMDGPU_GEM_DOMAIN_GTT | \ 83 AMDGPU_GEM_DOMAIN_VRAM | \ 84 AMDGPU_GEM_DOMAIN_GDS | \ 85 AMDGPU_GEM_DOMAIN_GWS | \ 86 AMDGPU_GEM_DOMAIN_OA) 87 88 /* Flag that CPU access will be required for the case of VRAM domain */ 89 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 90 /* Flag that CPU access will not work, this VRAM domain is invisible */ 91 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 92 /* Flag that USWC attributes should be used for GTT */ 93 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 94 /* Flag that the memory should be in VRAM and cleared */ 95 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 96 /* Flag that create shadow bo(GTT) while allocating vram bo */ 97 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 98 /* Flag that allocating the BO should use linear VRAM */ 99 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 100 /* Flag that BO is always valid in this VM */ 101 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 102 /* Flag that BO sharing will be explicitly synchronized */ 103 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 104 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 105 * for the second page onward should be set to NC. 106 */ 107 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 108 109 struct drm_amdgpu_gem_create_in { 110 /** the requested memory size */ 111 __u64 bo_size; 112 /** physical start_addr alignment in bytes for some HW requirements */ 113 __u64 alignment; 114 /** the requested memory domains */ 115 __u64 domains; 116 /** allocation flags */ 117 __u64 domain_flags; 118 }; 119 120 struct drm_amdgpu_gem_create_out { 121 /** returned GEM object handle */ 122 __u32 handle; 123 __u32 _pad; 124 }; 125 126 union drm_amdgpu_gem_create { 127 struct drm_amdgpu_gem_create_in in; 128 struct drm_amdgpu_gem_create_out out; 129 }; 130 131 /** Opcode to create new residency list. */ 132 #define AMDGPU_BO_LIST_OP_CREATE 0 133 /** Opcode to destroy previously created residency list */ 134 #define AMDGPU_BO_LIST_OP_DESTROY 1 135 /** Opcode to update resource information in the list */ 136 #define AMDGPU_BO_LIST_OP_UPDATE 2 137 138 struct drm_amdgpu_bo_list_in { 139 /** Type of operation */ 140 __u32 operation; 141 /** Handle of list or 0 if we want to create one */ 142 __u32 list_handle; 143 /** Number of BOs in list */ 144 __u32 bo_number; 145 /** Size of each element describing BO */ 146 __u32 bo_info_size; 147 /** Pointer to array describing BOs */ 148 __u64 bo_info_ptr; 149 }; 150 151 struct drm_amdgpu_bo_list_entry { 152 /** Handle of BO */ 153 __u32 bo_handle; 154 /** New (if specified) BO priority to be used during migration */ 155 __u32 bo_priority; 156 }; 157 158 struct drm_amdgpu_bo_list_out { 159 /** Handle of resource list */ 160 __u32 list_handle; 161 __u32 _pad; 162 }; 163 164 union drm_amdgpu_bo_list { 165 struct drm_amdgpu_bo_list_in in; 166 struct drm_amdgpu_bo_list_out out; 167 }; 168 169 /* context related */ 170 #define AMDGPU_CTX_OP_ALLOC_CTX 1 171 #define AMDGPU_CTX_OP_FREE_CTX 2 172 #define AMDGPU_CTX_OP_QUERY_STATE 3 173 #define AMDGPU_CTX_OP_QUERY_STATE2 4 174 175 /* GPU reset status */ 176 #define AMDGPU_CTX_NO_RESET 0 177 /* this the context caused it */ 178 #define AMDGPU_CTX_GUILTY_RESET 1 179 /* some other context caused it */ 180 #define AMDGPU_CTX_INNOCENT_RESET 2 181 /* unknown cause */ 182 #define AMDGPU_CTX_UNKNOWN_RESET 3 183 184 /* indicate gpu reset occured after ctx created */ 185 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 186 /* indicate vram lost occured after ctx created */ 187 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 188 /* indicate some job from this context once cause gpu hang */ 189 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 190 191 /* Context priority level */ 192 #define AMDGPU_CTX_PRIORITY_UNSET -2048 193 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 194 #define AMDGPU_CTX_PRIORITY_LOW -512 195 #define AMDGPU_CTX_PRIORITY_NORMAL 0 196 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ 197 #define AMDGPU_CTX_PRIORITY_HIGH 512 198 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 199 200 struct drm_amdgpu_ctx_in { 201 /** AMDGPU_CTX_OP_* */ 202 __u32 op; 203 /** For future use, no flags defined so far */ 204 __u32 flags; 205 __u32 ctx_id; 206 __s32 priority; 207 }; 208 209 union drm_amdgpu_ctx_out { 210 struct { 211 __u32 ctx_id; 212 __u32 _pad; 213 } alloc; 214 215 struct { 216 /** For future use, no flags defined so far */ 217 __u64 flags; 218 /** Number of resets caused by this context so far. */ 219 __u32 hangs; 220 /** Reset status since the last call of the ioctl. */ 221 __u32 reset_status; 222 } state; 223 }; 224 225 union drm_amdgpu_ctx { 226 struct drm_amdgpu_ctx_in in; 227 union drm_amdgpu_ctx_out out; 228 }; 229 230 /* vm ioctl */ 231 #define AMDGPU_VM_OP_RESERVE_VMID 1 232 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 233 234 struct drm_amdgpu_vm_in { 235 /** AMDGPU_VM_OP_* */ 236 __u32 op; 237 __u32 flags; 238 }; 239 240 struct drm_amdgpu_vm_out { 241 /** For future use, no flags defined so far */ 242 __u64 flags; 243 }; 244 245 union drm_amdgpu_vm { 246 struct drm_amdgpu_vm_in in; 247 struct drm_amdgpu_vm_out out; 248 }; 249 250 /* sched ioctl */ 251 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 252 253 struct drm_amdgpu_sched_in { 254 /* AMDGPU_SCHED_OP_* */ 255 __u32 op; 256 __u32 fd; 257 __s32 priority; 258 __u32 flags; 259 }; 260 261 union drm_amdgpu_sched { 262 struct drm_amdgpu_sched_in in; 263 }; 264 265 /* 266 * This is not a reliable API and you should expect it to fail for any 267 * number of reasons and have fallback path that do not use userptr to 268 * perform any operation. 269 */ 270 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 271 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 272 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 273 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 274 275 struct drm_amdgpu_gem_userptr { 276 __u64 addr; 277 __u64 size; 278 /* AMDGPU_GEM_USERPTR_* */ 279 __u32 flags; 280 /* Resulting GEM handle */ 281 __u32 handle; 282 }; 283 284 /* SI-CI-VI: */ 285 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 286 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 287 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 288 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 289 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 290 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 291 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 292 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 293 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 294 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 295 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 296 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 297 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 298 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 299 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 300 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 301 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 302 303 /* GFX9 and later: */ 304 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 305 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 306 307 /* Set/Get helpers for tiling flags. */ 308 #define AMDGPU_TILING_SET(field, value) \ 309 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 310 #define AMDGPU_TILING_GET(value, field) \ 311 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 312 313 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 314 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 315 316 /** The same structure is shared for input/output */ 317 struct drm_amdgpu_gem_metadata { 318 /** GEM Object handle */ 319 __u32 handle; 320 /** Do we want get or set metadata */ 321 __u32 op; 322 struct { 323 /** For future use, no flags defined so far */ 324 __u64 flags; 325 /** family specific tiling info */ 326 __u64 tiling_info; 327 __u32 data_size_bytes; 328 __u32 data[64]; 329 } data; 330 }; 331 332 struct drm_amdgpu_gem_mmap_in { 333 /** the GEM object handle */ 334 __u32 handle; 335 __u32 _pad; 336 }; 337 338 struct drm_amdgpu_gem_mmap_out { 339 /** mmap offset from the vma offset manager */ 340 __u64 addr_ptr; 341 }; 342 343 union drm_amdgpu_gem_mmap { 344 struct drm_amdgpu_gem_mmap_in in; 345 struct drm_amdgpu_gem_mmap_out out; 346 }; 347 348 struct drm_amdgpu_gem_wait_idle_in { 349 /** GEM object handle */ 350 __u32 handle; 351 /** For future use, no flags defined so far */ 352 __u32 flags; 353 /** Absolute timeout to wait */ 354 __u64 timeout; 355 }; 356 357 struct drm_amdgpu_gem_wait_idle_out { 358 /** BO status: 0 - BO is idle, 1 - BO is busy */ 359 __u32 status; 360 /** Returned current memory domain */ 361 __u32 domain; 362 }; 363 364 union drm_amdgpu_gem_wait_idle { 365 struct drm_amdgpu_gem_wait_idle_in in; 366 struct drm_amdgpu_gem_wait_idle_out out; 367 }; 368 369 struct drm_amdgpu_wait_cs_in { 370 /* Command submission handle 371 * handle equals 0 means none to wait for 372 * handle equals ~0ull means wait for the latest sequence number 373 */ 374 __u64 handle; 375 /** Absolute timeout to wait */ 376 __u64 timeout; 377 __u32 ip_type; 378 __u32 ip_instance; 379 __u32 ring; 380 __u32 ctx_id; 381 }; 382 383 struct drm_amdgpu_wait_cs_out { 384 /** CS status: 0 - CS completed, 1 - CS still busy */ 385 __u64 status; 386 }; 387 388 union drm_amdgpu_wait_cs { 389 struct drm_amdgpu_wait_cs_in in; 390 struct drm_amdgpu_wait_cs_out out; 391 }; 392 393 struct drm_amdgpu_fence { 394 __u32 ctx_id; 395 __u32 ip_type; 396 __u32 ip_instance; 397 __u32 ring; 398 __u64 seq_no; 399 }; 400 401 struct drm_amdgpu_wait_fences_in { 402 /** This points to uint64_t * which points to fences */ 403 __u64 fences; 404 __u32 fence_count; 405 __u32 wait_all; 406 __u64 timeout_ns; 407 }; 408 409 struct drm_amdgpu_wait_fences_out { 410 __u32 status; 411 __u32 first_signaled; 412 }; 413 414 union drm_amdgpu_wait_fences { 415 struct drm_amdgpu_wait_fences_in in; 416 struct drm_amdgpu_wait_fences_out out; 417 }; 418 419 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 420 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 421 422 /* Sets or returns a value associated with a buffer. */ 423 struct drm_amdgpu_gem_op { 424 /** GEM object handle */ 425 __u32 handle; 426 /** AMDGPU_GEM_OP_* */ 427 __u32 op; 428 /** Input or return value */ 429 __u64 value; 430 }; 431 432 #define AMDGPU_VA_OP_MAP 1 433 #define AMDGPU_VA_OP_UNMAP 2 434 #define AMDGPU_VA_OP_CLEAR 3 435 #define AMDGPU_VA_OP_REPLACE 4 436 437 /* Delay the page table update till the next CS */ 438 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 439 440 /* Mapping flags */ 441 /* readable mapping */ 442 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 443 /* writable mapping */ 444 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 445 /* executable mapping, new for VI */ 446 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 447 /* partially resident texture */ 448 #define AMDGPU_VM_PAGE_PRT (1 << 4) 449 /* MTYPE flags use bit 5 to 8 */ 450 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 451 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 452 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 453 /* Use NC MTYPE instead of default MTYPE */ 454 #define AMDGPU_VM_MTYPE_NC (1 << 5) 455 /* Use WC MTYPE instead of default MTYPE */ 456 #define AMDGPU_VM_MTYPE_WC (2 << 5) 457 /* Use CC MTYPE instead of default MTYPE */ 458 #define AMDGPU_VM_MTYPE_CC (3 << 5) 459 /* Use UC MTYPE instead of default MTYPE */ 460 #define AMDGPU_VM_MTYPE_UC (4 << 5) 461 462 struct drm_amdgpu_gem_va { 463 /** GEM object handle */ 464 __u32 handle; 465 __u32 _pad; 466 /** AMDGPU_VA_OP_* */ 467 __u32 operation; 468 /** AMDGPU_VM_PAGE_* */ 469 __u32 flags; 470 /** va address to assign . Must be correctly aligned.*/ 471 __u64 va_address; 472 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 473 __u64 offset_in_bo; 474 /** Specify mapping size. Must be correctly aligned. */ 475 __u64 map_size; 476 }; 477 478 #define AMDGPU_HW_IP_GFX 0 479 #define AMDGPU_HW_IP_COMPUTE 1 480 #define AMDGPU_HW_IP_DMA 2 481 #define AMDGPU_HW_IP_UVD 3 482 #define AMDGPU_HW_IP_VCE 4 483 #define AMDGPU_HW_IP_UVD_ENC 5 484 #define AMDGPU_HW_IP_VCN_DEC 6 485 #define AMDGPU_HW_IP_VCN_ENC 7 486 #define AMDGPU_HW_IP_NUM 8 487 488 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 489 490 #define AMDGPU_CHUNK_ID_IB 0x01 491 #define AMDGPU_CHUNK_ID_FENCE 0x02 492 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 493 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 494 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 495 496 struct drm_amdgpu_cs_chunk { 497 __u32 chunk_id; 498 __u32 length_dw; 499 __u64 chunk_data; 500 }; 501 502 struct drm_amdgpu_cs_in { 503 /** Rendering context id */ 504 __u32 ctx_id; 505 /** Handle of resource list associated with CS */ 506 __u32 bo_list_handle; 507 __u32 num_chunks; 508 __u32 _pad; 509 /** this points to __u64 * which point to cs chunks */ 510 __u64 chunks; 511 }; 512 513 struct drm_amdgpu_cs_out { 514 __u64 handle; 515 }; 516 517 union drm_amdgpu_cs { 518 struct drm_amdgpu_cs_in in; 519 struct drm_amdgpu_cs_out out; 520 }; 521 522 /* Specify flags to be used for IB */ 523 524 /* This IB should be submitted to CE */ 525 #define AMDGPU_IB_FLAG_CE (1<<0) 526 527 /* Preamble flag, which means the IB could be dropped if no context switch */ 528 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 529 530 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 531 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 532 533 /* The IB fence should do the L2 writeback but not invalidate any shader 534 * caches (L2/vL1/sL1/I$). */ 535 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 536 537 struct drm_amdgpu_cs_chunk_ib { 538 __u32 _pad; 539 /** AMDGPU_IB_FLAG_* */ 540 __u32 flags; 541 /** Virtual address to begin IB execution */ 542 __u64 va_start; 543 /** Size of submission */ 544 __u32 ib_bytes; 545 /** HW IP to submit to */ 546 __u32 ip_type; 547 /** HW IP index of the same type to submit to */ 548 __u32 ip_instance; 549 /** Ring index to submit to */ 550 __u32 ring; 551 }; 552 553 struct drm_amdgpu_cs_chunk_dep { 554 __u32 ip_type; 555 __u32 ip_instance; 556 __u32 ring; 557 __u32 ctx_id; 558 __u64 handle; 559 }; 560 561 struct drm_amdgpu_cs_chunk_fence { 562 __u32 handle; 563 __u32 offset; 564 }; 565 566 struct drm_amdgpu_cs_chunk_sem { 567 __u32 handle; 568 }; 569 570 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 571 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 572 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 573 574 union drm_amdgpu_fence_to_handle { 575 struct { 576 struct drm_amdgpu_fence fence; 577 __u32 what; 578 __u32 pad; 579 } in; 580 struct { 581 __u32 handle; 582 } out; 583 }; 584 585 struct drm_amdgpu_cs_chunk_data { 586 union { 587 struct drm_amdgpu_cs_chunk_ib ib_data; 588 struct drm_amdgpu_cs_chunk_fence fence_data; 589 }; 590 }; 591 592 /** 593 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 594 * 595 */ 596 #define AMDGPU_IDS_FLAGS_FUSION 0x1 597 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 598 599 /* indicate if acceleration can be working */ 600 #define AMDGPU_INFO_ACCEL_WORKING 0x00 601 /* get the crtc_id from the mode object id? */ 602 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 603 /* query hw IP info */ 604 #define AMDGPU_INFO_HW_IP_INFO 0x02 605 /* query hw IP instance count for the specified type */ 606 #define AMDGPU_INFO_HW_IP_COUNT 0x03 607 /* timestamp for GL_ARB_timer_query */ 608 #define AMDGPU_INFO_TIMESTAMP 0x05 609 /* Query the firmware version */ 610 #define AMDGPU_INFO_FW_VERSION 0x0e 611 /* Subquery id: Query VCE firmware version */ 612 #define AMDGPU_INFO_FW_VCE 0x1 613 /* Subquery id: Query UVD firmware version */ 614 #define AMDGPU_INFO_FW_UVD 0x2 615 /* Subquery id: Query GMC firmware version */ 616 #define AMDGPU_INFO_FW_GMC 0x03 617 /* Subquery id: Query GFX ME firmware version */ 618 #define AMDGPU_INFO_FW_GFX_ME 0x04 619 /* Subquery id: Query GFX PFP firmware version */ 620 #define AMDGPU_INFO_FW_GFX_PFP 0x05 621 /* Subquery id: Query GFX CE firmware version */ 622 #define AMDGPU_INFO_FW_GFX_CE 0x06 623 /* Subquery id: Query GFX RLC firmware version */ 624 #define AMDGPU_INFO_FW_GFX_RLC 0x07 625 /* Subquery id: Query GFX MEC firmware version */ 626 #define AMDGPU_INFO_FW_GFX_MEC 0x08 627 /* Subquery id: Query SMC firmware version */ 628 #define AMDGPU_INFO_FW_SMC 0x0a 629 /* Subquery id: Query SDMA firmware version */ 630 #define AMDGPU_INFO_FW_SDMA 0x0b 631 /* Subquery id: Query PSP SOS firmware version */ 632 #define AMDGPU_INFO_FW_SOS 0x0c 633 /* Subquery id: Query PSP ASD firmware version */ 634 #define AMDGPU_INFO_FW_ASD 0x0d 635 /* Subquery id: Query VCN firmware version */ 636 #define AMDGPU_INFO_FW_VCN 0x0e 637 /* Subquery id: Query GFX RLC SRLC firmware version */ 638 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 639 /* Subquery id: Query GFX RLC SRLG firmware version */ 640 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 641 /* Subquery id: Query GFX RLC SRLS firmware version */ 642 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 643 /* number of bytes moved for TTM migration */ 644 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 645 /* the used VRAM size */ 646 #define AMDGPU_INFO_VRAM_USAGE 0x10 647 /* the used GTT size */ 648 #define AMDGPU_INFO_GTT_USAGE 0x11 649 /* Information about GDS, etc. resource configuration */ 650 #define AMDGPU_INFO_GDS_CONFIG 0x13 651 /* Query information about VRAM and GTT domains */ 652 #define AMDGPU_INFO_VRAM_GTT 0x14 653 /* Query information about register in MMR address space*/ 654 #define AMDGPU_INFO_READ_MMR_REG 0x15 655 /* Query information about device: rev id, family, etc. */ 656 #define AMDGPU_INFO_DEV_INFO 0x16 657 /* visible vram usage */ 658 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 659 /* number of TTM buffer evictions */ 660 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 661 /* Query memory about VRAM and GTT domains */ 662 #define AMDGPU_INFO_MEMORY 0x19 663 /* Query vce clock table */ 664 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 665 /* Query vbios related information */ 666 #define AMDGPU_INFO_VBIOS 0x1B 667 /* Subquery id: Query vbios size */ 668 #define AMDGPU_INFO_VBIOS_SIZE 0x1 669 /* Subquery id: Query vbios image */ 670 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 671 /* Query UVD handles */ 672 #define AMDGPU_INFO_NUM_HANDLES 0x1C 673 /* Query sensor related information */ 674 #define AMDGPU_INFO_SENSOR 0x1D 675 /* Subquery id: Query GPU shader clock */ 676 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 677 /* Subquery id: Query GPU memory clock */ 678 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 679 /* Subquery id: Query GPU temperature */ 680 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 681 /* Subquery id: Query GPU load */ 682 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 683 /* Subquery id: Query average GPU power */ 684 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 685 /* Subquery id: Query northbridge voltage */ 686 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 687 /* Subquery id: Query graphics voltage */ 688 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 689 /* Subquery id: Query GPU stable pstate shader clock */ 690 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 691 /* Subquery id: Query GPU stable pstate memory clock */ 692 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 693 /* Number of VRAM page faults on CPU access. */ 694 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 695 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 696 697 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 698 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 699 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 700 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 701 702 struct drm_amdgpu_query_fw { 703 /** AMDGPU_INFO_FW_* */ 704 __u32 fw_type; 705 /** 706 * Index of the IP if there are more IPs of 707 * the same type. 708 */ 709 __u32 ip_instance; 710 /** 711 * Index of the engine. Whether this is used depends 712 * on the firmware type. (e.g. MEC, SDMA) 713 */ 714 __u32 index; 715 __u32 _pad; 716 }; 717 718 /* Input structure for the INFO ioctl */ 719 struct drm_amdgpu_info { 720 /* Where the return value will be stored */ 721 __u64 return_pointer; 722 /* The size of the return value. Just like "size" in "snprintf", 723 * it limits how many bytes the kernel can write. */ 724 __u32 return_size; 725 /* The query request id. */ 726 __u32 query; 727 728 union { 729 struct { 730 __u32 id; 731 __u32 _pad; 732 } mode_crtc; 733 734 struct { 735 /** AMDGPU_HW_IP_* */ 736 __u32 type; 737 /** 738 * Index of the IP if there are more IPs of the same 739 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 740 */ 741 __u32 ip_instance; 742 } query_hw_ip; 743 744 struct { 745 __u32 dword_offset; 746 /** number of registers to read */ 747 __u32 count; 748 __u32 instance; 749 /** For future use, no flags defined so far */ 750 __u32 flags; 751 } read_mmr_reg; 752 753 struct drm_amdgpu_query_fw query_fw; 754 755 struct { 756 __u32 type; 757 __u32 offset; 758 } vbios_info; 759 760 struct { 761 __u32 type; 762 } sensor_info; 763 }; 764 }; 765 766 struct drm_amdgpu_info_gds { 767 /** GDS GFX partition size */ 768 __u32 gds_gfx_partition_size; 769 /** GDS compute partition size */ 770 __u32 compute_partition_size; 771 /** total GDS memory size */ 772 __u32 gds_total_size; 773 /** GWS size per GFX partition */ 774 __u32 gws_per_gfx_partition; 775 /** GSW size per compute partition */ 776 __u32 gws_per_compute_partition; 777 /** OA size per GFX partition */ 778 __u32 oa_per_gfx_partition; 779 /** OA size per compute partition */ 780 __u32 oa_per_compute_partition; 781 __u32 _pad; 782 }; 783 784 struct drm_amdgpu_info_vram_gtt { 785 __u64 vram_size; 786 __u64 vram_cpu_accessible_size; 787 __u64 gtt_size; 788 }; 789 790 struct drm_amdgpu_heap_info { 791 /** max. physical memory */ 792 __u64 total_heap_size; 793 794 /** Theoretical max. available memory in the given heap */ 795 __u64 usable_heap_size; 796 797 /** 798 * Number of bytes allocated in the heap. This includes all processes 799 * and private allocations in the kernel. It changes when new buffers 800 * are allocated, freed, and moved. It cannot be larger than 801 * heap_size. 802 */ 803 __u64 heap_usage; 804 805 /** 806 * Theoretical possible max. size of buffer which 807 * could be allocated in the given heap 808 */ 809 __u64 max_allocation; 810 }; 811 812 struct drm_amdgpu_memory_info { 813 struct drm_amdgpu_heap_info vram; 814 struct drm_amdgpu_heap_info cpu_accessible_vram; 815 struct drm_amdgpu_heap_info gtt; 816 }; 817 818 struct drm_amdgpu_info_firmware { 819 __u32 ver; 820 __u32 feature; 821 }; 822 823 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 824 #define AMDGPU_VRAM_TYPE_GDDR1 1 825 #define AMDGPU_VRAM_TYPE_DDR2 2 826 #define AMDGPU_VRAM_TYPE_GDDR3 3 827 #define AMDGPU_VRAM_TYPE_GDDR4 4 828 #define AMDGPU_VRAM_TYPE_GDDR5 5 829 #define AMDGPU_VRAM_TYPE_HBM 6 830 #define AMDGPU_VRAM_TYPE_DDR3 7 831 #define AMDGPU_VRAM_TYPE_DDR4 8 832 833 struct drm_amdgpu_info_device { 834 /** PCI Device ID */ 835 __u32 device_id; 836 /** Internal chip revision: A0, A1, etc.) */ 837 __u32 chip_rev; 838 __u32 external_rev; 839 /** Revision id in PCI Config space */ 840 __u32 pci_rev; 841 __u32 family; 842 __u32 num_shader_engines; 843 __u32 num_shader_arrays_per_engine; 844 /* in KHz */ 845 __u32 gpu_counter_freq; 846 __u64 max_engine_clock; 847 __u64 max_memory_clock; 848 /* cu information */ 849 __u32 cu_active_number; 850 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 851 __u32 cu_ao_mask; 852 __u32 cu_bitmap[4][4]; 853 /** Render backend pipe mask. One render backend is CB+DB. */ 854 __u32 enabled_rb_pipes_mask; 855 __u32 num_rb_pipes; 856 __u32 num_hw_gfx_contexts; 857 __u32 _pad; 858 __u64 ids_flags; 859 /** Starting virtual address for UMDs. */ 860 __u64 virtual_address_offset; 861 /** The maximum virtual address */ 862 __u64 virtual_address_max; 863 /** Required alignment of virtual addresses. */ 864 __u32 virtual_address_alignment; 865 /** Page table entry - fragment size */ 866 __u32 pte_fragment_size; 867 __u32 gart_page_size; 868 /** constant engine ram size*/ 869 __u32 ce_ram_size; 870 /** video memory type info*/ 871 __u32 vram_type; 872 /** video memory bit width*/ 873 __u32 vram_bit_width; 874 /* vce harvesting instance */ 875 __u32 vce_harvest_config; 876 /* gfx double offchip LDS buffers */ 877 __u32 gc_double_offchip_lds_buf; 878 /* NGG Primitive Buffer */ 879 __u64 prim_buf_gpu_addr; 880 /* NGG Position Buffer */ 881 __u64 pos_buf_gpu_addr; 882 /* NGG Control Sideband */ 883 __u64 cntl_sb_buf_gpu_addr; 884 /* NGG Parameter Cache */ 885 __u64 param_buf_gpu_addr; 886 __u32 prim_buf_size; 887 __u32 pos_buf_size; 888 __u32 cntl_sb_buf_size; 889 __u32 param_buf_size; 890 /* wavefront size*/ 891 __u32 wave_front_size; 892 /* shader visible vgprs*/ 893 __u32 num_shader_visible_vgprs; 894 /* CU per shader array*/ 895 __u32 num_cu_per_sh; 896 /* number of tcc blocks*/ 897 __u32 num_tcc_blocks; 898 /* gs vgt table depth*/ 899 __u32 gs_vgt_table_depth; 900 /* gs primitive buffer depth*/ 901 __u32 gs_prim_buffer_depth; 902 /* max gs wavefront per vgt*/ 903 __u32 max_gs_waves_per_vgt; 904 __u32 _pad1; 905 /* always on cu bitmap */ 906 __u32 cu_ao_bitmap[4][4]; 907 /** Starting high virtual address for UMDs. */ 908 __u64 high_va_offset; 909 /** The maximum high virtual address */ 910 __u64 high_va_max; 911 }; 912 913 struct drm_amdgpu_info_hw_ip { 914 /** Version of h/w IP */ 915 __u32 hw_ip_version_major; 916 __u32 hw_ip_version_minor; 917 /** Capabilities */ 918 __u64 capabilities_flags; 919 /** command buffer address start alignment*/ 920 __u32 ib_start_alignment; 921 /** command buffer size alignment*/ 922 __u32 ib_size_alignment; 923 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 924 __u32 available_rings; 925 __u32 _pad; 926 }; 927 928 struct drm_amdgpu_info_num_handles { 929 /** Max handles as supported by firmware for UVD */ 930 __u32 uvd_max_handles; 931 /** Handles currently in use for UVD */ 932 __u32 uvd_used_handles; 933 }; 934 935 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 936 937 struct drm_amdgpu_info_vce_clock_table_entry { 938 /** System clock */ 939 __u32 sclk; 940 /** Memory clock */ 941 __u32 mclk; 942 /** VCE clock */ 943 __u32 eclk; 944 __u32 pad; 945 }; 946 947 struct drm_amdgpu_info_vce_clock_table { 948 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 949 __u32 num_valid_entries; 950 __u32 pad; 951 }; 952 953 /* 954 * Supported GPU families 955 */ 956 #define AMDGPU_FAMILY_UNKNOWN 0 957 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 958 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 959 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 960 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 961 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 962 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 963 #define AMDGPU_FAMILY_RV 142 /* Raven */ 964 965 #if defined(__cplusplus) 966 } 967 #endif 968 969 #endif 970