1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that allocating the BO should use linear VRAM */ 120 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 121 /* Flag that BO is always valid in this VM */ 122 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 123 /* Flag that BO sharing will be explicitly synchronized */ 124 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 125 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 126 * for the second page onward should be set to NC. It should never 127 * be used by user space applications. 128 */ 129 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 130 /* Flag that BO may contain sensitive data that must be wiped before 131 * releasing the memory 132 */ 133 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 134 /* Flag that BO will be encrypted and that the TMZ bit should be 135 * set in the PTEs when mapping this buffer via GPUVM or 136 * accessing it with various hw blocks 137 */ 138 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 139 /* Flag that BO will be used only in preemptible context, which does 140 * not require GTT memory accounting 141 */ 142 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 143 /* Flag that BO can be discarded under memory pressure without keeping the 144 * content. 145 */ 146 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 147 148 struct drm_amdgpu_gem_create_in { 149 /** the requested memory size */ 150 __u64 bo_size; 151 /** physical start_addr alignment in bytes for some HW requirements */ 152 __u64 alignment; 153 /** the requested memory domains */ 154 __u64 domains; 155 /** allocation flags */ 156 __u64 domain_flags; 157 }; 158 159 struct drm_amdgpu_gem_create_out { 160 /** returned GEM object handle */ 161 __u32 handle; 162 __u32 _pad; 163 }; 164 165 union drm_amdgpu_gem_create { 166 struct drm_amdgpu_gem_create_in in; 167 struct drm_amdgpu_gem_create_out out; 168 }; 169 170 /** Opcode to create new residency list. */ 171 #define AMDGPU_BO_LIST_OP_CREATE 0 172 /** Opcode to destroy previously created residency list */ 173 #define AMDGPU_BO_LIST_OP_DESTROY 1 174 /** Opcode to update resource information in the list */ 175 #define AMDGPU_BO_LIST_OP_UPDATE 2 176 177 struct drm_amdgpu_bo_list_in { 178 /** Type of operation */ 179 __u32 operation; 180 /** Handle of list or 0 if we want to create one */ 181 __u32 list_handle; 182 /** Number of BOs in list */ 183 __u32 bo_number; 184 /** Size of each element describing BO */ 185 __u32 bo_info_size; 186 /** Pointer to array describing BOs */ 187 __u64 bo_info_ptr; 188 }; 189 190 struct drm_amdgpu_bo_list_entry { 191 /** Handle of BO */ 192 __u32 bo_handle; 193 /** New (if specified) BO priority to be used during migration */ 194 __u32 bo_priority; 195 }; 196 197 struct drm_amdgpu_bo_list_out { 198 /** Handle of resource list */ 199 __u32 list_handle; 200 __u32 _pad; 201 }; 202 203 union drm_amdgpu_bo_list { 204 struct drm_amdgpu_bo_list_in in; 205 struct drm_amdgpu_bo_list_out out; 206 }; 207 208 /* context related */ 209 #define AMDGPU_CTX_OP_ALLOC_CTX 1 210 #define AMDGPU_CTX_OP_FREE_CTX 2 211 #define AMDGPU_CTX_OP_QUERY_STATE 3 212 #define AMDGPU_CTX_OP_QUERY_STATE2 4 213 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 214 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 215 216 /* GPU reset status */ 217 #define AMDGPU_CTX_NO_RESET 0 218 /* this the context caused it */ 219 #define AMDGPU_CTX_GUILTY_RESET 1 220 /* some other context caused it */ 221 #define AMDGPU_CTX_INNOCENT_RESET 2 222 /* unknown cause */ 223 #define AMDGPU_CTX_UNKNOWN_RESET 3 224 225 /* indicate gpu reset occured after ctx created */ 226 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 227 /* indicate vram lost occured after ctx created */ 228 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 229 /* indicate some job from this context once cause gpu hang */ 230 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 231 /* indicate some errors are detected by RAS */ 232 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 233 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 234 235 /* Context priority level */ 236 #define AMDGPU_CTX_PRIORITY_UNSET -2048 237 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 238 #define AMDGPU_CTX_PRIORITY_LOW -512 239 #define AMDGPU_CTX_PRIORITY_NORMAL 0 240 /* 241 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 242 * CAP_SYS_NICE or DRM_MASTER 243 */ 244 #define AMDGPU_CTX_PRIORITY_HIGH 512 245 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 246 247 /* select a stable profiling pstate for perfmon tools */ 248 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 249 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 250 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 251 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 252 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 253 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 254 255 struct drm_amdgpu_ctx_in { 256 /** AMDGPU_CTX_OP_* */ 257 __u32 op; 258 /** Flags */ 259 __u32 flags; 260 __u32 ctx_id; 261 /** AMDGPU_CTX_PRIORITY_* */ 262 __s32 priority; 263 }; 264 265 union drm_amdgpu_ctx_out { 266 struct { 267 __u32 ctx_id; 268 __u32 _pad; 269 } alloc; 270 271 struct { 272 /** For future use, no flags defined so far */ 273 __u64 flags; 274 /** Number of resets caused by this context so far. */ 275 __u32 hangs; 276 /** Reset status since the last call of the ioctl. */ 277 __u32 reset_status; 278 } state; 279 280 struct { 281 __u32 flags; 282 __u32 _pad; 283 } pstate; 284 }; 285 286 union drm_amdgpu_ctx { 287 struct drm_amdgpu_ctx_in in; 288 union drm_amdgpu_ctx_out out; 289 }; 290 291 /* vm ioctl */ 292 #define AMDGPU_VM_OP_RESERVE_VMID 1 293 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 294 295 struct drm_amdgpu_vm_in { 296 /** AMDGPU_VM_OP_* */ 297 __u32 op; 298 __u32 flags; 299 }; 300 301 struct drm_amdgpu_vm_out { 302 /** For future use, no flags defined so far */ 303 __u64 flags; 304 }; 305 306 union drm_amdgpu_vm { 307 struct drm_amdgpu_vm_in in; 308 struct drm_amdgpu_vm_out out; 309 }; 310 311 /* sched ioctl */ 312 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 313 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 314 315 struct drm_amdgpu_sched_in { 316 /* AMDGPU_SCHED_OP_* */ 317 __u32 op; 318 __u32 fd; 319 /** AMDGPU_CTX_PRIORITY_* */ 320 __s32 priority; 321 __u32 ctx_id; 322 }; 323 324 union drm_amdgpu_sched { 325 struct drm_amdgpu_sched_in in; 326 }; 327 328 /* 329 * This is not a reliable API and you should expect it to fail for any 330 * number of reasons and have fallback path that do not use userptr to 331 * perform any operation. 332 */ 333 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 334 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 335 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 336 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 337 338 struct drm_amdgpu_gem_userptr { 339 __u64 addr; 340 __u64 size; 341 /* AMDGPU_GEM_USERPTR_* */ 342 __u32 flags; 343 /* Resulting GEM handle */ 344 __u32 handle; 345 }; 346 347 /* SI-CI-VI: */ 348 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 349 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 350 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 351 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 352 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 353 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 354 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 355 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 356 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 357 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 358 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 359 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 360 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 361 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 362 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 363 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 364 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 365 366 /* GFX9 and later: */ 367 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 368 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 369 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 370 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 371 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 372 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 373 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 374 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 375 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 376 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 377 #define AMDGPU_TILING_SCANOUT_SHIFT 63 378 #define AMDGPU_TILING_SCANOUT_MASK 0x1 379 380 /* Set/Get helpers for tiling flags. */ 381 #define AMDGPU_TILING_SET(field, value) \ 382 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 383 #define AMDGPU_TILING_GET(value, field) \ 384 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 385 386 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 387 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 388 389 /** The same structure is shared for input/output */ 390 struct drm_amdgpu_gem_metadata { 391 /** GEM Object handle */ 392 __u32 handle; 393 /** Do we want get or set metadata */ 394 __u32 op; 395 struct { 396 /** For future use, no flags defined so far */ 397 __u64 flags; 398 /** family specific tiling info */ 399 __u64 tiling_info; 400 __u32 data_size_bytes; 401 __u32 data[64]; 402 } data; 403 }; 404 405 struct drm_amdgpu_gem_mmap_in { 406 /** the GEM object handle */ 407 __u32 handle; 408 __u32 _pad; 409 }; 410 411 struct drm_amdgpu_gem_mmap_out { 412 /** mmap offset from the vma offset manager */ 413 __u64 addr_ptr; 414 }; 415 416 union drm_amdgpu_gem_mmap { 417 struct drm_amdgpu_gem_mmap_in in; 418 struct drm_amdgpu_gem_mmap_out out; 419 }; 420 421 struct drm_amdgpu_gem_wait_idle_in { 422 /** GEM object handle */ 423 __u32 handle; 424 /** For future use, no flags defined so far */ 425 __u32 flags; 426 /** Absolute timeout to wait */ 427 __u64 timeout; 428 }; 429 430 struct drm_amdgpu_gem_wait_idle_out { 431 /** BO status: 0 - BO is idle, 1 - BO is busy */ 432 __u32 status; 433 /** Returned current memory domain */ 434 __u32 domain; 435 }; 436 437 union drm_amdgpu_gem_wait_idle { 438 struct drm_amdgpu_gem_wait_idle_in in; 439 struct drm_amdgpu_gem_wait_idle_out out; 440 }; 441 442 struct drm_amdgpu_wait_cs_in { 443 /* Command submission handle 444 * handle equals 0 means none to wait for 445 * handle equals ~0ull means wait for the latest sequence number 446 */ 447 __u64 handle; 448 /** Absolute timeout to wait */ 449 __u64 timeout; 450 __u32 ip_type; 451 __u32 ip_instance; 452 __u32 ring; 453 __u32 ctx_id; 454 }; 455 456 struct drm_amdgpu_wait_cs_out { 457 /** CS status: 0 - CS completed, 1 - CS still busy */ 458 __u64 status; 459 }; 460 461 union drm_amdgpu_wait_cs { 462 struct drm_amdgpu_wait_cs_in in; 463 struct drm_amdgpu_wait_cs_out out; 464 }; 465 466 struct drm_amdgpu_fence { 467 __u32 ctx_id; 468 __u32 ip_type; 469 __u32 ip_instance; 470 __u32 ring; 471 __u64 seq_no; 472 }; 473 474 struct drm_amdgpu_wait_fences_in { 475 /** This points to uint64_t * which points to fences */ 476 __u64 fences; 477 __u32 fence_count; 478 __u32 wait_all; 479 __u64 timeout_ns; 480 }; 481 482 struct drm_amdgpu_wait_fences_out { 483 __u32 status; 484 __u32 first_signaled; 485 }; 486 487 union drm_amdgpu_wait_fences { 488 struct drm_amdgpu_wait_fences_in in; 489 struct drm_amdgpu_wait_fences_out out; 490 }; 491 492 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 493 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 494 495 /* Sets or returns a value associated with a buffer. */ 496 struct drm_amdgpu_gem_op { 497 /** GEM object handle */ 498 __u32 handle; 499 /** AMDGPU_GEM_OP_* */ 500 __u32 op; 501 /** Input or return value */ 502 __u64 value; 503 }; 504 505 #define AMDGPU_VA_OP_MAP 1 506 #define AMDGPU_VA_OP_UNMAP 2 507 #define AMDGPU_VA_OP_CLEAR 3 508 #define AMDGPU_VA_OP_REPLACE 4 509 510 /* Delay the page table update till the next CS */ 511 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 512 513 /* Mapping flags */ 514 /* readable mapping */ 515 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 516 /* writable mapping */ 517 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 518 /* executable mapping, new for VI */ 519 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 520 /* partially resident texture */ 521 #define AMDGPU_VM_PAGE_PRT (1 << 4) 522 /* MTYPE flags use bit 5 to 8 */ 523 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 524 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 525 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 526 /* Use Non Coherent MTYPE instead of default MTYPE */ 527 #define AMDGPU_VM_MTYPE_NC (1 << 5) 528 /* Use Write Combine MTYPE instead of default MTYPE */ 529 #define AMDGPU_VM_MTYPE_WC (2 << 5) 530 /* Use Cache Coherent MTYPE instead of default MTYPE */ 531 #define AMDGPU_VM_MTYPE_CC (3 << 5) 532 /* Use UnCached MTYPE instead of default MTYPE */ 533 #define AMDGPU_VM_MTYPE_UC (4 << 5) 534 /* Use Read Write MTYPE instead of default MTYPE */ 535 #define AMDGPU_VM_MTYPE_RW (5 << 5) 536 /* don't allocate MALL */ 537 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 538 539 struct drm_amdgpu_gem_va { 540 /** GEM object handle */ 541 __u32 handle; 542 __u32 _pad; 543 /** AMDGPU_VA_OP_* */ 544 __u32 operation; 545 /** AMDGPU_VM_PAGE_* */ 546 __u32 flags; 547 /** va address to assign . Must be correctly aligned.*/ 548 __u64 va_address; 549 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 550 __u64 offset_in_bo; 551 /** Specify mapping size. Must be correctly aligned. */ 552 __u64 map_size; 553 }; 554 555 #define AMDGPU_HW_IP_GFX 0 556 #define AMDGPU_HW_IP_COMPUTE 1 557 #define AMDGPU_HW_IP_DMA 2 558 #define AMDGPU_HW_IP_UVD 3 559 #define AMDGPU_HW_IP_VCE 4 560 #define AMDGPU_HW_IP_UVD_ENC 5 561 #define AMDGPU_HW_IP_VCN_DEC 6 562 /* 563 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 564 * both encoding and decoding jobs. 565 */ 566 #define AMDGPU_HW_IP_VCN_ENC 7 567 #define AMDGPU_HW_IP_VCN_JPEG 8 568 #define AMDGPU_HW_IP_NUM 9 569 570 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 571 572 #define AMDGPU_CHUNK_ID_IB 0x01 573 #define AMDGPU_CHUNK_ID_FENCE 0x02 574 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 575 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 576 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 577 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 578 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 579 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 580 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 581 582 struct drm_amdgpu_cs_chunk { 583 __u32 chunk_id; 584 __u32 length_dw; 585 __u64 chunk_data; 586 }; 587 588 struct drm_amdgpu_cs_in { 589 /** Rendering context id */ 590 __u32 ctx_id; 591 /** Handle of resource list associated with CS */ 592 __u32 bo_list_handle; 593 __u32 num_chunks; 594 __u32 flags; 595 /** this points to __u64 * which point to cs chunks */ 596 __u64 chunks; 597 }; 598 599 struct drm_amdgpu_cs_out { 600 __u64 handle; 601 }; 602 603 union drm_amdgpu_cs { 604 struct drm_amdgpu_cs_in in; 605 struct drm_amdgpu_cs_out out; 606 }; 607 608 /* Specify flags to be used for IB */ 609 610 /* This IB should be submitted to CE */ 611 #define AMDGPU_IB_FLAG_CE (1<<0) 612 613 /* Preamble flag, which means the IB could be dropped if no context switch */ 614 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 615 616 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 617 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 618 619 /* The IB fence should do the L2 writeback but not invalidate any shader 620 * caches (L2/vL1/sL1/I$). */ 621 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 622 623 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 624 * This will reset wave ID counters for the IB. 625 */ 626 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 627 628 /* Flag the IB as secure (TMZ) 629 */ 630 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 631 632 /* Tell KMD to flush and invalidate caches 633 */ 634 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 635 636 struct drm_amdgpu_cs_chunk_ib { 637 __u32 _pad; 638 /** AMDGPU_IB_FLAG_* */ 639 __u32 flags; 640 /** Virtual address to begin IB execution */ 641 __u64 va_start; 642 /** Size of submission */ 643 __u32 ib_bytes; 644 /** HW IP to submit to */ 645 __u32 ip_type; 646 /** HW IP index of the same type to submit to */ 647 __u32 ip_instance; 648 /** Ring index to submit to */ 649 __u32 ring; 650 }; 651 652 struct drm_amdgpu_cs_chunk_dep { 653 __u32 ip_type; 654 __u32 ip_instance; 655 __u32 ring; 656 __u32 ctx_id; 657 __u64 handle; 658 }; 659 660 struct drm_amdgpu_cs_chunk_fence { 661 __u32 handle; 662 __u32 offset; 663 }; 664 665 struct drm_amdgpu_cs_chunk_sem { 666 __u32 handle; 667 }; 668 669 struct drm_amdgpu_cs_chunk_syncobj { 670 __u32 handle; 671 __u32 flags; 672 __u64 point; 673 }; 674 675 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 676 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 677 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 678 679 union drm_amdgpu_fence_to_handle { 680 struct { 681 struct drm_amdgpu_fence fence; 682 __u32 what; 683 __u32 pad; 684 } in; 685 struct { 686 __u32 handle; 687 } out; 688 }; 689 690 struct drm_amdgpu_cs_chunk_data { 691 union { 692 struct drm_amdgpu_cs_chunk_ib ib_data; 693 struct drm_amdgpu_cs_chunk_fence fence_data; 694 }; 695 }; 696 697 /* 698 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 699 * 700 */ 701 #define AMDGPU_IDS_FLAGS_FUSION 0x1 702 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 703 #define AMDGPU_IDS_FLAGS_TMZ 0x4 704 705 /* indicate if acceleration can be working */ 706 #define AMDGPU_INFO_ACCEL_WORKING 0x00 707 /* get the crtc_id from the mode object id? */ 708 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 709 /* query hw IP info */ 710 #define AMDGPU_INFO_HW_IP_INFO 0x02 711 /* query hw IP instance count for the specified type */ 712 #define AMDGPU_INFO_HW_IP_COUNT 0x03 713 /* timestamp for GL_ARB_timer_query */ 714 #define AMDGPU_INFO_TIMESTAMP 0x05 715 /* Query the firmware version */ 716 #define AMDGPU_INFO_FW_VERSION 0x0e 717 /* Subquery id: Query VCE firmware version */ 718 #define AMDGPU_INFO_FW_VCE 0x1 719 /* Subquery id: Query UVD firmware version */ 720 #define AMDGPU_INFO_FW_UVD 0x2 721 /* Subquery id: Query GMC firmware version */ 722 #define AMDGPU_INFO_FW_GMC 0x03 723 /* Subquery id: Query GFX ME firmware version */ 724 #define AMDGPU_INFO_FW_GFX_ME 0x04 725 /* Subquery id: Query GFX PFP firmware version */ 726 #define AMDGPU_INFO_FW_GFX_PFP 0x05 727 /* Subquery id: Query GFX CE firmware version */ 728 #define AMDGPU_INFO_FW_GFX_CE 0x06 729 /* Subquery id: Query GFX RLC firmware version */ 730 #define AMDGPU_INFO_FW_GFX_RLC 0x07 731 /* Subquery id: Query GFX MEC firmware version */ 732 #define AMDGPU_INFO_FW_GFX_MEC 0x08 733 /* Subquery id: Query SMC firmware version */ 734 #define AMDGPU_INFO_FW_SMC 0x0a 735 /* Subquery id: Query SDMA firmware version */ 736 #define AMDGPU_INFO_FW_SDMA 0x0b 737 /* Subquery id: Query PSP SOS firmware version */ 738 #define AMDGPU_INFO_FW_SOS 0x0c 739 /* Subquery id: Query PSP ASD firmware version */ 740 #define AMDGPU_INFO_FW_ASD 0x0d 741 /* Subquery id: Query VCN firmware version */ 742 #define AMDGPU_INFO_FW_VCN 0x0e 743 /* Subquery id: Query GFX RLC SRLC firmware version */ 744 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 745 /* Subquery id: Query GFX RLC SRLG firmware version */ 746 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 747 /* Subquery id: Query GFX RLC SRLS firmware version */ 748 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 749 /* Subquery id: Query DMCU firmware version */ 750 #define AMDGPU_INFO_FW_DMCU 0x12 751 #define AMDGPU_INFO_FW_TA 0x13 752 /* Subquery id: Query DMCUB firmware version */ 753 #define AMDGPU_INFO_FW_DMCUB 0x14 754 /* Subquery id: Query TOC firmware version */ 755 #define AMDGPU_INFO_FW_TOC 0x15 756 /* Subquery id: Query CAP firmware version */ 757 #define AMDGPU_INFO_FW_CAP 0x16 758 759 /* number of bytes moved for TTM migration */ 760 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 761 /* the used VRAM size */ 762 #define AMDGPU_INFO_VRAM_USAGE 0x10 763 /* the used GTT size */ 764 #define AMDGPU_INFO_GTT_USAGE 0x11 765 /* Information about GDS, etc. resource configuration */ 766 #define AMDGPU_INFO_GDS_CONFIG 0x13 767 /* Query information about VRAM and GTT domains */ 768 #define AMDGPU_INFO_VRAM_GTT 0x14 769 /* Query information about register in MMR address space*/ 770 #define AMDGPU_INFO_READ_MMR_REG 0x15 771 /* Query information about device: rev id, family, etc. */ 772 #define AMDGPU_INFO_DEV_INFO 0x16 773 /* visible vram usage */ 774 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 775 /* number of TTM buffer evictions */ 776 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 777 /* Query memory about VRAM and GTT domains */ 778 #define AMDGPU_INFO_MEMORY 0x19 779 /* Query vce clock table */ 780 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 781 /* Query vbios related information */ 782 #define AMDGPU_INFO_VBIOS 0x1B 783 /* Subquery id: Query vbios size */ 784 #define AMDGPU_INFO_VBIOS_SIZE 0x1 785 /* Subquery id: Query vbios image */ 786 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 787 /* Subquery id: Query vbios info */ 788 #define AMDGPU_INFO_VBIOS_INFO 0x3 789 /* Query UVD handles */ 790 #define AMDGPU_INFO_NUM_HANDLES 0x1C 791 /* Query sensor related information */ 792 #define AMDGPU_INFO_SENSOR 0x1D 793 /* Subquery id: Query GPU shader clock */ 794 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 795 /* Subquery id: Query GPU memory clock */ 796 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 797 /* Subquery id: Query GPU temperature */ 798 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 799 /* Subquery id: Query GPU load */ 800 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 801 /* Subquery id: Query average GPU power */ 802 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 803 /* Subquery id: Query northbridge voltage */ 804 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 805 /* Subquery id: Query graphics voltage */ 806 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 807 /* Subquery id: Query GPU stable pstate shader clock */ 808 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 809 /* Subquery id: Query GPU stable pstate memory clock */ 810 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 811 /* Number of VRAM page faults on CPU access. */ 812 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 813 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 814 /* query ras mask of enabled features*/ 815 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 816 /* RAS MASK: UMC (VRAM) */ 817 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 818 /* RAS MASK: SDMA */ 819 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 820 /* RAS MASK: GFX */ 821 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 822 /* RAS MASK: MMHUB */ 823 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 824 /* RAS MASK: ATHUB */ 825 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 826 /* RAS MASK: PCIE */ 827 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 828 /* RAS MASK: HDP */ 829 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 830 /* RAS MASK: XGMI */ 831 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 832 /* RAS MASK: DF */ 833 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 834 /* RAS MASK: SMN */ 835 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 836 /* RAS MASK: SEM */ 837 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 838 /* RAS MASK: MP0 */ 839 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 840 /* RAS MASK: MP1 */ 841 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 842 /* RAS MASK: FUSE */ 843 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 844 /* query video encode/decode caps */ 845 #define AMDGPU_INFO_VIDEO_CAPS 0x21 846 /* Subquery id: Decode */ 847 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 848 /* Subquery id: Encode */ 849 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 850 851 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 852 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 853 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 854 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 855 856 struct drm_amdgpu_query_fw { 857 /** AMDGPU_INFO_FW_* */ 858 __u32 fw_type; 859 /** 860 * Index of the IP if there are more IPs of 861 * the same type. 862 */ 863 __u32 ip_instance; 864 /** 865 * Index of the engine. Whether this is used depends 866 * on the firmware type. (e.g. MEC, SDMA) 867 */ 868 __u32 index; 869 __u32 _pad; 870 }; 871 872 /* Input structure for the INFO ioctl */ 873 struct drm_amdgpu_info { 874 /* Where the return value will be stored */ 875 __u64 return_pointer; 876 /* The size of the return value. Just like "size" in "snprintf", 877 * it limits how many bytes the kernel can write. */ 878 __u32 return_size; 879 /* The query request id. */ 880 __u32 query; 881 882 union { 883 struct { 884 __u32 id; 885 __u32 _pad; 886 } mode_crtc; 887 888 struct { 889 /** AMDGPU_HW_IP_* */ 890 __u32 type; 891 /** 892 * Index of the IP if there are more IPs of the same 893 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 894 */ 895 __u32 ip_instance; 896 } query_hw_ip; 897 898 struct { 899 __u32 dword_offset; 900 /** number of registers to read */ 901 __u32 count; 902 __u32 instance; 903 /** For future use, no flags defined so far */ 904 __u32 flags; 905 } read_mmr_reg; 906 907 struct drm_amdgpu_query_fw query_fw; 908 909 struct { 910 __u32 type; 911 __u32 offset; 912 } vbios_info; 913 914 struct { 915 __u32 type; 916 } sensor_info; 917 918 struct { 919 __u32 type; 920 } video_cap; 921 }; 922 }; 923 924 struct drm_amdgpu_info_gds { 925 /** GDS GFX partition size */ 926 __u32 gds_gfx_partition_size; 927 /** GDS compute partition size */ 928 __u32 compute_partition_size; 929 /** total GDS memory size */ 930 __u32 gds_total_size; 931 /** GWS size per GFX partition */ 932 __u32 gws_per_gfx_partition; 933 /** GSW size per compute partition */ 934 __u32 gws_per_compute_partition; 935 /** OA size per GFX partition */ 936 __u32 oa_per_gfx_partition; 937 /** OA size per compute partition */ 938 __u32 oa_per_compute_partition; 939 __u32 _pad; 940 }; 941 942 struct drm_amdgpu_info_vram_gtt { 943 __u64 vram_size; 944 __u64 vram_cpu_accessible_size; 945 __u64 gtt_size; 946 }; 947 948 struct drm_amdgpu_heap_info { 949 /** max. physical memory */ 950 __u64 total_heap_size; 951 952 /** Theoretical max. available memory in the given heap */ 953 __u64 usable_heap_size; 954 955 /** 956 * Number of bytes allocated in the heap. This includes all processes 957 * and private allocations in the kernel. It changes when new buffers 958 * are allocated, freed, and moved. It cannot be larger than 959 * heap_size. 960 */ 961 __u64 heap_usage; 962 963 /** 964 * Theoretical possible max. size of buffer which 965 * could be allocated in the given heap 966 */ 967 __u64 max_allocation; 968 }; 969 970 struct drm_amdgpu_memory_info { 971 struct drm_amdgpu_heap_info vram; 972 struct drm_amdgpu_heap_info cpu_accessible_vram; 973 struct drm_amdgpu_heap_info gtt; 974 }; 975 976 struct drm_amdgpu_info_firmware { 977 __u32 ver; 978 __u32 feature; 979 }; 980 981 struct drm_amdgpu_info_vbios { 982 __u8 name[64]; 983 __u8 vbios_pn[64]; 984 __u32 version; 985 __u32 pad; 986 __u8 vbios_ver_str[32]; 987 __u8 date[32]; 988 }; 989 990 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 991 #define AMDGPU_VRAM_TYPE_GDDR1 1 992 #define AMDGPU_VRAM_TYPE_DDR2 2 993 #define AMDGPU_VRAM_TYPE_GDDR3 3 994 #define AMDGPU_VRAM_TYPE_GDDR4 4 995 #define AMDGPU_VRAM_TYPE_GDDR5 5 996 #define AMDGPU_VRAM_TYPE_HBM 6 997 #define AMDGPU_VRAM_TYPE_DDR3 7 998 #define AMDGPU_VRAM_TYPE_DDR4 8 999 #define AMDGPU_VRAM_TYPE_GDDR6 9 1000 #define AMDGPU_VRAM_TYPE_DDR5 10 1001 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1002 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1003 1004 struct drm_amdgpu_info_device { 1005 /** PCI Device ID */ 1006 __u32 device_id; 1007 /** Internal chip revision: A0, A1, etc.) */ 1008 __u32 chip_rev; 1009 __u32 external_rev; 1010 /** Revision id in PCI Config space */ 1011 __u32 pci_rev; 1012 __u32 family; 1013 __u32 num_shader_engines; 1014 __u32 num_shader_arrays_per_engine; 1015 /* in KHz */ 1016 __u32 gpu_counter_freq; 1017 __u64 max_engine_clock; 1018 __u64 max_memory_clock; 1019 /* cu information */ 1020 __u32 cu_active_number; 1021 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1022 __u32 cu_ao_mask; 1023 __u32 cu_bitmap[4][4]; 1024 /** Render backend pipe mask. One render backend is CB+DB. */ 1025 __u32 enabled_rb_pipes_mask; 1026 __u32 num_rb_pipes; 1027 __u32 num_hw_gfx_contexts; 1028 __u32 _pad; 1029 __u64 ids_flags; 1030 /** Starting virtual address for UMDs. */ 1031 __u64 virtual_address_offset; 1032 /** The maximum virtual address */ 1033 __u64 virtual_address_max; 1034 /** Required alignment of virtual addresses. */ 1035 __u32 virtual_address_alignment; 1036 /** Page table entry - fragment size */ 1037 __u32 pte_fragment_size; 1038 __u32 gart_page_size; 1039 /** constant engine ram size*/ 1040 __u32 ce_ram_size; 1041 /** video memory type info*/ 1042 __u32 vram_type; 1043 /** video memory bit width*/ 1044 __u32 vram_bit_width; 1045 /* vce harvesting instance */ 1046 __u32 vce_harvest_config; 1047 /* gfx double offchip LDS buffers */ 1048 __u32 gc_double_offchip_lds_buf; 1049 /* NGG Primitive Buffer */ 1050 __u64 prim_buf_gpu_addr; 1051 /* NGG Position Buffer */ 1052 __u64 pos_buf_gpu_addr; 1053 /* NGG Control Sideband */ 1054 __u64 cntl_sb_buf_gpu_addr; 1055 /* NGG Parameter Cache */ 1056 __u64 param_buf_gpu_addr; 1057 __u32 prim_buf_size; 1058 __u32 pos_buf_size; 1059 __u32 cntl_sb_buf_size; 1060 __u32 param_buf_size; 1061 /* wavefront size*/ 1062 __u32 wave_front_size; 1063 /* shader visible vgprs*/ 1064 __u32 num_shader_visible_vgprs; 1065 /* CU per shader array*/ 1066 __u32 num_cu_per_sh; 1067 /* number of tcc blocks*/ 1068 __u32 num_tcc_blocks; 1069 /* gs vgt table depth*/ 1070 __u32 gs_vgt_table_depth; 1071 /* gs primitive buffer depth*/ 1072 __u32 gs_prim_buffer_depth; 1073 /* max gs wavefront per vgt*/ 1074 __u32 max_gs_waves_per_vgt; 1075 __u32 _pad1; 1076 /* always on cu bitmap */ 1077 __u32 cu_ao_bitmap[4][4]; 1078 /** Starting high virtual address for UMDs. */ 1079 __u64 high_va_offset; 1080 /** The maximum high virtual address */ 1081 __u64 high_va_max; 1082 /* gfx10 pa_sc_tile_steering_override */ 1083 __u32 pa_sc_tile_steering_override; 1084 /* disabled TCCs */ 1085 __u64 tcc_disabled_mask; 1086 }; 1087 1088 struct drm_amdgpu_info_hw_ip { 1089 /** Version of h/w IP */ 1090 __u32 hw_ip_version_major; 1091 __u32 hw_ip_version_minor; 1092 /** Capabilities */ 1093 __u64 capabilities_flags; 1094 /** command buffer address start alignment*/ 1095 __u32 ib_start_alignment; 1096 /** command buffer size alignment*/ 1097 __u32 ib_size_alignment; 1098 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1099 __u32 available_rings; 1100 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1101 __u32 ip_discovery_version; 1102 }; 1103 1104 struct drm_amdgpu_info_num_handles { 1105 /** Max handles as supported by firmware for UVD */ 1106 __u32 uvd_max_handles; 1107 /** Handles currently in use for UVD */ 1108 __u32 uvd_used_handles; 1109 }; 1110 1111 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1112 1113 struct drm_amdgpu_info_vce_clock_table_entry { 1114 /** System clock */ 1115 __u32 sclk; 1116 /** Memory clock */ 1117 __u32 mclk; 1118 /** VCE clock */ 1119 __u32 eclk; 1120 __u32 pad; 1121 }; 1122 1123 struct drm_amdgpu_info_vce_clock_table { 1124 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1125 __u32 num_valid_entries; 1126 __u32 pad; 1127 }; 1128 1129 /* query video encode/decode caps */ 1130 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1131 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1132 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1133 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1134 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1135 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1136 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1137 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1138 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1139 1140 struct drm_amdgpu_info_video_codec_info { 1141 __u32 valid; 1142 __u32 max_width; 1143 __u32 max_height; 1144 __u32 max_pixels_per_frame; 1145 __u32 max_level; 1146 __u32 pad; 1147 }; 1148 1149 struct drm_amdgpu_info_video_caps { 1150 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1151 }; 1152 1153 /* 1154 * Supported GPU families 1155 */ 1156 #define AMDGPU_FAMILY_UNKNOWN 0 1157 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1158 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1159 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1160 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1161 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1162 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1163 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1164 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1165 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1166 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1167 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1168 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1169 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1170 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1171 1172 #if defined(__cplusplus) 1173 } 1174 #endif 1175 1176 #endif 1177