1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linezrized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that create shadow bo(GTT) while allocating vram bo */ 120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 121 /* Flag that allocating the BO should use linear VRAM */ 122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123 /* Flag that BO is always valid in this VM */ 124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125 /* Flag that BO sharing will be explicitly synchronized */ 126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128 * for the second page onward should be set to NC. 129 */ 130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 131 132 struct drm_amdgpu_gem_create_in { 133 /** the requested memory size */ 134 __u64 bo_size; 135 /** physical start_addr alignment in bytes for some HW requirements */ 136 __u64 alignment; 137 /** the requested memory domains */ 138 __u64 domains; 139 /** allocation flags */ 140 __u64 domain_flags; 141 }; 142 143 struct drm_amdgpu_gem_create_out { 144 /** returned GEM object handle */ 145 __u32 handle; 146 __u32 _pad; 147 }; 148 149 union drm_amdgpu_gem_create { 150 struct drm_amdgpu_gem_create_in in; 151 struct drm_amdgpu_gem_create_out out; 152 }; 153 154 /** Opcode to create new residency list. */ 155 #define AMDGPU_BO_LIST_OP_CREATE 0 156 /** Opcode to destroy previously created residency list */ 157 #define AMDGPU_BO_LIST_OP_DESTROY 1 158 /** Opcode to update resource information in the list */ 159 #define AMDGPU_BO_LIST_OP_UPDATE 2 160 161 struct drm_amdgpu_bo_list_in { 162 /** Type of operation */ 163 __u32 operation; 164 /** Handle of list or 0 if we want to create one */ 165 __u32 list_handle; 166 /** Number of BOs in list */ 167 __u32 bo_number; 168 /** Size of each element describing BO */ 169 __u32 bo_info_size; 170 /** Pointer to array describing BOs */ 171 __u64 bo_info_ptr; 172 }; 173 174 struct drm_amdgpu_bo_list_entry { 175 /** Handle of BO */ 176 __u32 bo_handle; 177 /** New (if specified) BO priority to be used during migration */ 178 __u32 bo_priority; 179 }; 180 181 struct drm_amdgpu_bo_list_out { 182 /** Handle of resource list */ 183 __u32 list_handle; 184 __u32 _pad; 185 }; 186 187 union drm_amdgpu_bo_list { 188 struct drm_amdgpu_bo_list_in in; 189 struct drm_amdgpu_bo_list_out out; 190 }; 191 192 /* context related */ 193 #define AMDGPU_CTX_OP_ALLOC_CTX 1 194 #define AMDGPU_CTX_OP_FREE_CTX 2 195 #define AMDGPU_CTX_OP_QUERY_STATE 3 196 #define AMDGPU_CTX_OP_QUERY_STATE2 4 197 198 /* GPU reset status */ 199 #define AMDGPU_CTX_NO_RESET 0 200 /* this the context caused it */ 201 #define AMDGPU_CTX_GUILTY_RESET 1 202 /* some other context caused it */ 203 #define AMDGPU_CTX_INNOCENT_RESET 2 204 /* unknown cause */ 205 #define AMDGPU_CTX_UNKNOWN_RESET 3 206 207 /* indicate gpu reset occured after ctx created */ 208 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 209 /* indicate vram lost occured after ctx created */ 210 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 211 /* indicate some job from this context once cause gpu hang */ 212 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 213 214 /* Context priority level */ 215 #define AMDGPU_CTX_PRIORITY_UNSET -2048 216 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 217 #define AMDGPU_CTX_PRIORITY_LOW -512 218 #define AMDGPU_CTX_PRIORITY_NORMAL 0 219 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ 220 #define AMDGPU_CTX_PRIORITY_HIGH 512 221 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 222 223 struct drm_amdgpu_ctx_in { 224 /** AMDGPU_CTX_OP_* */ 225 __u32 op; 226 /** For future use, no flags defined so far */ 227 __u32 flags; 228 __u32 ctx_id; 229 __s32 priority; 230 }; 231 232 union drm_amdgpu_ctx_out { 233 struct { 234 __u32 ctx_id; 235 __u32 _pad; 236 } alloc; 237 238 struct { 239 /** For future use, no flags defined so far */ 240 __u64 flags; 241 /** Number of resets caused by this context so far. */ 242 __u32 hangs; 243 /** Reset status since the last call of the ioctl. */ 244 __u32 reset_status; 245 } state; 246 }; 247 248 union drm_amdgpu_ctx { 249 struct drm_amdgpu_ctx_in in; 250 union drm_amdgpu_ctx_out out; 251 }; 252 253 /* vm ioctl */ 254 #define AMDGPU_VM_OP_RESERVE_VMID 1 255 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 256 257 struct drm_amdgpu_vm_in { 258 /** AMDGPU_VM_OP_* */ 259 __u32 op; 260 __u32 flags; 261 }; 262 263 struct drm_amdgpu_vm_out { 264 /** For future use, no flags defined so far */ 265 __u64 flags; 266 }; 267 268 union drm_amdgpu_vm { 269 struct drm_amdgpu_vm_in in; 270 struct drm_amdgpu_vm_out out; 271 }; 272 273 /* sched ioctl */ 274 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 275 276 struct drm_amdgpu_sched_in { 277 /* AMDGPU_SCHED_OP_* */ 278 __u32 op; 279 __u32 fd; 280 __s32 priority; 281 __u32 flags; 282 }; 283 284 union drm_amdgpu_sched { 285 struct drm_amdgpu_sched_in in; 286 }; 287 288 /* 289 * This is not a reliable API and you should expect it to fail for any 290 * number of reasons and have fallback path that do not use userptr to 291 * perform any operation. 292 */ 293 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 294 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 295 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 296 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 297 298 struct drm_amdgpu_gem_userptr { 299 __u64 addr; 300 __u64 size; 301 /* AMDGPU_GEM_USERPTR_* */ 302 __u32 flags; 303 /* Resulting GEM handle */ 304 __u32 handle; 305 }; 306 307 /* SI-CI-VI: */ 308 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 309 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 310 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 311 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 312 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 313 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 314 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 315 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 316 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 317 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 318 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 319 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 320 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 321 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 322 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 323 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 324 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 325 326 /* GFX9 and later: */ 327 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 328 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 329 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 330 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 331 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 332 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 333 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 334 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 335 336 /* Set/Get helpers for tiling flags. */ 337 #define AMDGPU_TILING_SET(field, value) \ 338 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 339 #define AMDGPU_TILING_GET(value, field) \ 340 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 341 342 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 343 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 344 345 /** The same structure is shared for input/output */ 346 struct drm_amdgpu_gem_metadata { 347 /** GEM Object handle */ 348 __u32 handle; 349 /** Do we want get or set metadata */ 350 __u32 op; 351 struct { 352 /** For future use, no flags defined so far */ 353 __u64 flags; 354 /** family specific tiling info */ 355 __u64 tiling_info; 356 __u32 data_size_bytes; 357 __u32 data[64]; 358 } data; 359 }; 360 361 struct drm_amdgpu_gem_mmap_in { 362 /** the GEM object handle */ 363 __u32 handle; 364 __u32 _pad; 365 }; 366 367 struct drm_amdgpu_gem_mmap_out { 368 /** mmap offset from the vma offset manager */ 369 __u64 addr_ptr; 370 }; 371 372 union drm_amdgpu_gem_mmap { 373 struct drm_amdgpu_gem_mmap_in in; 374 struct drm_amdgpu_gem_mmap_out out; 375 }; 376 377 struct drm_amdgpu_gem_wait_idle_in { 378 /** GEM object handle */ 379 __u32 handle; 380 /** For future use, no flags defined so far */ 381 __u32 flags; 382 /** Absolute timeout to wait */ 383 __u64 timeout; 384 }; 385 386 struct drm_amdgpu_gem_wait_idle_out { 387 /** BO status: 0 - BO is idle, 1 - BO is busy */ 388 __u32 status; 389 /** Returned current memory domain */ 390 __u32 domain; 391 }; 392 393 union drm_amdgpu_gem_wait_idle { 394 struct drm_amdgpu_gem_wait_idle_in in; 395 struct drm_amdgpu_gem_wait_idle_out out; 396 }; 397 398 struct drm_amdgpu_wait_cs_in { 399 /* Command submission handle 400 * handle equals 0 means none to wait for 401 * handle equals ~0ull means wait for the latest sequence number 402 */ 403 __u64 handle; 404 /** Absolute timeout to wait */ 405 __u64 timeout; 406 __u32 ip_type; 407 __u32 ip_instance; 408 __u32 ring; 409 __u32 ctx_id; 410 }; 411 412 struct drm_amdgpu_wait_cs_out { 413 /** CS status: 0 - CS completed, 1 - CS still busy */ 414 __u64 status; 415 }; 416 417 union drm_amdgpu_wait_cs { 418 struct drm_amdgpu_wait_cs_in in; 419 struct drm_amdgpu_wait_cs_out out; 420 }; 421 422 struct drm_amdgpu_fence { 423 __u32 ctx_id; 424 __u32 ip_type; 425 __u32 ip_instance; 426 __u32 ring; 427 __u64 seq_no; 428 }; 429 430 struct drm_amdgpu_wait_fences_in { 431 /** This points to uint64_t * which points to fences */ 432 __u64 fences; 433 __u32 fence_count; 434 __u32 wait_all; 435 __u64 timeout_ns; 436 }; 437 438 struct drm_amdgpu_wait_fences_out { 439 __u32 status; 440 __u32 first_signaled; 441 }; 442 443 union drm_amdgpu_wait_fences { 444 struct drm_amdgpu_wait_fences_in in; 445 struct drm_amdgpu_wait_fences_out out; 446 }; 447 448 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 449 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 450 451 /* Sets or returns a value associated with a buffer. */ 452 struct drm_amdgpu_gem_op { 453 /** GEM object handle */ 454 __u32 handle; 455 /** AMDGPU_GEM_OP_* */ 456 __u32 op; 457 /** Input or return value */ 458 __u64 value; 459 }; 460 461 #define AMDGPU_VA_OP_MAP 1 462 #define AMDGPU_VA_OP_UNMAP 2 463 #define AMDGPU_VA_OP_CLEAR 3 464 #define AMDGPU_VA_OP_REPLACE 4 465 466 /* Delay the page table update till the next CS */ 467 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 468 469 /* Mapping flags */ 470 /* readable mapping */ 471 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 472 /* writable mapping */ 473 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 474 /* executable mapping, new for VI */ 475 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 476 /* partially resident texture */ 477 #define AMDGPU_VM_PAGE_PRT (1 << 4) 478 /* MTYPE flags use bit 5 to 8 */ 479 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 480 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 481 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 482 /* Use NC MTYPE instead of default MTYPE */ 483 #define AMDGPU_VM_MTYPE_NC (1 << 5) 484 /* Use WC MTYPE instead of default MTYPE */ 485 #define AMDGPU_VM_MTYPE_WC (2 << 5) 486 /* Use CC MTYPE instead of default MTYPE */ 487 #define AMDGPU_VM_MTYPE_CC (3 << 5) 488 /* Use UC MTYPE instead of default MTYPE */ 489 #define AMDGPU_VM_MTYPE_UC (4 << 5) 490 491 struct drm_amdgpu_gem_va { 492 /** GEM object handle */ 493 __u32 handle; 494 __u32 _pad; 495 /** AMDGPU_VA_OP_* */ 496 __u32 operation; 497 /** AMDGPU_VM_PAGE_* */ 498 __u32 flags; 499 /** va address to assign . Must be correctly aligned.*/ 500 __u64 va_address; 501 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 502 __u64 offset_in_bo; 503 /** Specify mapping size. Must be correctly aligned. */ 504 __u64 map_size; 505 }; 506 507 #define AMDGPU_HW_IP_GFX 0 508 #define AMDGPU_HW_IP_COMPUTE 1 509 #define AMDGPU_HW_IP_DMA 2 510 #define AMDGPU_HW_IP_UVD 3 511 #define AMDGPU_HW_IP_VCE 4 512 #define AMDGPU_HW_IP_UVD_ENC 5 513 #define AMDGPU_HW_IP_VCN_DEC 6 514 #define AMDGPU_HW_IP_VCN_ENC 7 515 #define AMDGPU_HW_IP_VCN_JPEG 8 516 #define AMDGPU_HW_IP_NUM 9 517 518 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 519 520 #define AMDGPU_CHUNK_ID_IB 0x01 521 #define AMDGPU_CHUNK_ID_FENCE 0x02 522 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 523 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 524 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 525 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 526 527 struct drm_amdgpu_cs_chunk { 528 __u32 chunk_id; 529 __u32 length_dw; 530 __u64 chunk_data; 531 }; 532 533 struct drm_amdgpu_cs_in { 534 /** Rendering context id */ 535 __u32 ctx_id; 536 /** Handle of resource list associated with CS */ 537 __u32 bo_list_handle; 538 __u32 num_chunks; 539 __u32 _pad; 540 /** this points to __u64 * which point to cs chunks */ 541 __u64 chunks; 542 }; 543 544 struct drm_amdgpu_cs_out { 545 __u64 handle; 546 }; 547 548 union drm_amdgpu_cs { 549 struct drm_amdgpu_cs_in in; 550 struct drm_amdgpu_cs_out out; 551 }; 552 553 /* Specify flags to be used for IB */ 554 555 /* This IB should be submitted to CE */ 556 #define AMDGPU_IB_FLAG_CE (1<<0) 557 558 /* Preamble flag, which means the IB could be dropped if no context switch */ 559 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 560 561 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 562 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 563 564 /* The IB fence should do the L2 writeback but not invalidate any shader 565 * caches (L2/vL1/sL1/I$). */ 566 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 567 568 struct drm_amdgpu_cs_chunk_ib { 569 __u32 _pad; 570 /** AMDGPU_IB_FLAG_* */ 571 __u32 flags; 572 /** Virtual address to begin IB execution */ 573 __u64 va_start; 574 /** Size of submission */ 575 __u32 ib_bytes; 576 /** HW IP to submit to */ 577 __u32 ip_type; 578 /** HW IP index of the same type to submit to */ 579 __u32 ip_instance; 580 /** Ring index to submit to */ 581 __u32 ring; 582 }; 583 584 struct drm_amdgpu_cs_chunk_dep { 585 __u32 ip_type; 586 __u32 ip_instance; 587 __u32 ring; 588 __u32 ctx_id; 589 __u64 handle; 590 }; 591 592 struct drm_amdgpu_cs_chunk_fence { 593 __u32 handle; 594 __u32 offset; 595 }; 596 597 struct drm_amdgpu_cs_chunk_sem { 598 __u32 handle; 599 }; 600 601 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 602 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 603 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 604 605 union drm_amdgpu_fence_to_handle { 606 struct { 607 struct drm_amdgpu_fence fence; 608 __u32 what; 609 __u32 pad; 610 } in; 611 struct { 612 __u32 handle; 613 } out; 614 }; 615 616 struct drm_amdgpu_cs_chunk_data { 617 union { 618 struct drm_amdgpu_cs_chunk_ib ib_data; 619 struct drm_amdgpu_cs_chunk_fence fence_data; 620 }; 621 }; 622 623 /** 624 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 625 * 626 */ 627 #define AMDGPU_IDS_FLAGS_FUSION 0x1 628 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 629 630 /* indicate if acceleration can be working */ 631 #define AMDGPU_INFO_ACCEL_WORKING 0x00 632 /* get the crtc_id from the mode object id? */ 633 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 634 /* query hw IP info */ 635 #define AMDGPU_INFO_HW_IP_INFO 0x02 636 /* query hw IP instance count for the specified type */ 637 #define AMDGPU_INFO_HW_IP_COUNT 0x03 638 /* timestamp for GL_ARB_timer_query */ 639 #define AMDGPU_INFO_TIMESTAMP 0x05 640 /* Query the firmware version */ 641 #define AMDGPU_INFO_FW_VERSION 0x0e 642 /* Subquery id: Query VCE firmware version */ 643 #define AMDGPU_INFO_FW_VCE 0x1 644 /* Subquery id: Query UVD firmware version */ 645 #define AMDGPU_INFO_FW_UVD 0x2 646 /* Subquery id: Query GMC firmware version */ 647 #define AMDGPU_INFO_FW_GMC 0x03 648 /* Subquery id: Query GFX ME firmware version */ 649 #define AMDGPU_INFO_FW_GFX_ME 0x04 650 /* Subquery id: Query GFX PFP firmware version */ 651 #define AMDGPU_INFO_FW_GFX_PFP 0x05 652 /* Subquery id: Query GFX CE firmware version */ 653 #define AMDGPU_INFO_FW_GFX_CE 0x06 654 /* Subquery id: Query GFX RLC firmware version */ 655 #define AMDGPU_INFO_FW_GFX_RLC 0x07 656 /* Subquery id: Query GFX MEC firmware version */ 657 #define AMDGPU_INFO_FW_GFX_MEC 0x08 658 /* Subquery id: Query SMC firmware version */ 659 #define AMDGPU_INFO_FW_SMC 0x0a 660 /* Subquery id: Query SDMA firmware version */ 661 #define AMDGPU_INFO_FW_SDMA 0x0b 662 /* Subquery id: Query PSP SOS firmware version */ 663 #define AMDGPU_INFO_FW_SOS 0x0c 664 /* Subquery id: Query PSP ASD firmware version */ 665 #define AMDGPU_INFO_FW_ASD 0x0d 666 /* Subquery id: Query VCN firmware version */ 667 #define AMDGPU_INFO_FW_VCN 0x0e 668 /* Subquery id: Query GFX RLC SRLC firmware version */ 669 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 670 /* Subquery id: Query GFX RLC SRLG firmware version */ 671 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 672 /* Subquery id: Query GFX RLC SRLS firmware version */ 673 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 674 /* Subquery id: Query DMCU firmware version */ 675 #define AMDGPU_INFO_FW_DMCU 0x12 676 /* number of bytes moved for TTM migration */ 677 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 678 /* the used VRAM size */ 679 #define AMDGPU_INFO_VRAM_USAGE 0x10 680 /* the used GTT size */ 681 #define AMDGPU_INFO_GTT_USAGE 0x11 682 /* Information about GDS, etc. resource configuration */ 683 #define AMDGPU_INFO_GDS_CONFIG 0x13 684 /* Query information about VRAM and GTT domains */ 685 #define AMDGPU_INFO_VRAM_GTT 0x14 686 /* Query information about register in MMR address space*/ 687 #define AMDGPU_INFO_READ_MMR_REG 0x15 688 /* Query information about device: rev id, family, etc. */ 689 #define AMDGPU_INFO_DEV_INFO 0x16 690 /* visible vram usage */ 691 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 692 /* number of TTM buffer evictions */ 693 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 694 /* Query memory about VRAM and GTT domains */ 695 #define AMDGPU_INFO_MEMORY 0x19 696 /* Query vce clock table */ 697 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 698 /* Query vbios related information */ 699 #define AMDGPU_INFO_VBIOS 0x1B 700 /* Subquery id: Query vbios size */ 701 #define AMDGPU_INFO_VBIOS_SIZE 0x1 702 /* Subquery id: Query vbios image */ 703 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 704 /* Query UVD handles */ 705 #define AMDGPU_INFO_NUM_HANDLES 0x1C 706 /* Query sensor related information */ 707 #define AMDGPU_INFO_SENSOR 0x1D 708 /* Subquery id: Query GPU shader clock */ 709 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 710 /* Subquery id: Query GPU memory clock */ 711 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 712 /* Subquery id: Query GPU temperature */ 713 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 714 /* Subquery id: Query GPU load */ 715 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 716 /* Subquery id: Query average GPU power */ 717 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 718 /* Subquery id: Query northbridge voltage */ 719 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 720 /* Subquery id: Query graphics voltage */ 721 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 722 /* Subquery id: Query GPU stable pstate shader clock */ 723 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 724 /* Subquery id: Query GPU stable pstate memory clock */ 725 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 726 /* Number of VRAM page faults on CPU access. */ 727 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 728 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 729 730 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 731 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 732 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 733 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 734 735 struct drm_amdgpu_query_fw { 736 /** AMDGPU_INFO_FW_* */ 737 __u32 fw_type; 738 /** 739 * Index of the IP if there are more IPs of 740 * the same type. 741 */ 742 __u32 ip_instance; 743 /** 744 * Index of the engine. Whether this is used depends 745 * on the firmware type. (e.g. MEC, SDMA) 746 */ 747 __u32 index; 748 __u32 _pad; 749 }; 750 751 /* Input structure for the INFO ioctl */ 752 struct drm_amdgpu_info { 753 /* Where the return value will be stored */ 754 __u64 return_pointer; 755 /* The size of the return value. Just like "size" in "snprintf", 756 * it limits how many bytes the kernel can write. */ 757 __u32 return_size; 758 /* The query request id. */ 759 __u32 query; 760 761 union { 762 struct { 763 __u32 id; 764 __u32 _pad; 765 } mode_crtc; 766 767 struct { 768 /** AMDGPU_HW_IP_* */ 769 __u32 type; 770 /** 771 * Index of the IP if there are more IPs of the same 772 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 773 */ 774 __u32 ip_instance; 775 } query_hw_ip; 776 777 struct { 778 __u32 dword_offset; 779 /** number of registers to read */ 780 __u32 count; 781 __u32 instance; 782 /** For future use, no flags defined so far */ 783 __u32 flags; 784 } read_mmr_reg; 785 786 struct drm_amdgpu_query_fw query_fw; 787 788 struct { 789 __u32 type; 790 __u32 offset; 791 } vbios_info; 792 793 struct { 794 __u32 type; 795 } sensor_info; 796 }; 797 }; 798 799 struct drm_amdgpu_info_gds { 800 /** GDS GFX partition size */ 801 __u32 gds_gfx_partition_size; 802 /** GDS compute partition size */ 803 __u32 compute_partition_size; 804 /** total GDS memory size */ 805 __u32 gds_total_size; 806 /** GWS size per GFX partition */ 807 __u32 gws_per_gfx_partition; 808 /** GSW size per compute partition */ 809 __u32 gws_per_compute_partition; 810 /** OA size per GFX partition */ 811 __u32 oa_per_gfx_partition; 812 /** OA size per compute partition */ 813 __u32 oa_per_compute_partition; 814 __u32 _pad; 815 }; 816 817 struct drm_amdgpu_info_vram_gtt { 818 __u64 vram_size; 819 __u64 vram_cpu_accessible_size; 820 __u64 gtt_size; 821 }; 822 823 struct drm_amdgpu_heap_info { 824 /** max. physical memory */ 825 __u64 total_heap_size; 826 827 /** Theoretical max. available memory in the given heap */ 828 __u64 usable_heap_size; 829 830 /** 831 * Number of bytes allocated in the heap. This includes all processes 832 * and private allocations in the kernel. It changes when new buffers 833 * are allocated, freed, and moved. It cannot be larger than 834 * heap_size. 835 */ 836 __u64 heap_usage; 837 838 /** 839 * Theoretical possible max. size of buffer which 840 * could be allocated in the given heap 841 */ 842 __u64 max_allocation; 843 }; 844 845 struct drm_amdgpu_memory_info { 846 struct drm_amdgpu_heap_info vram; 847 struct drm_amdgpu_heap_info cpu_accessible_vram; 848 struct drm_amdgpu_heap_info gtt; 849 }; 850 851 struct drm_amdgpu_info_firmware { 852 __u32 ver; 853 __u32 feature; 854 }; 855 856 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 857 #define AMDGPU_VRAM_TYPE_GDDR1 1 858 #define AMDGPU_VRAM_TYPE_DDR2 2 859 #define AMDGPU_VRAM_TYPE_GDDR3 3 860 #define AMDGPU_VRAM_TYPE_GDDR4 4 861 #define AMDGPU_VRAM_TYPE_GDDR5 5 862 #define AMDGPU_VRAM_TYPE_HBM 6 863 #define AMDGPU_VRAM_TYPE_DDR3 7 864 #define AMDGPU_VRAM_TYPE_DDR4 8 865 866 struct drm_amdgpu_info_device { 867 /** PCI Device ID */ 868 __u32 device_id; 869 /** Internal chip revision: A0, A1, etc.) */ 870 __u32 chip_rev; 871 __u32 external_rev; 872 /** Revision id in PCI Config space */ 873 __u32 pci_rev; 874 __u32 family; 875 __u32 num_shader_engines; 876 __u32 num_shader_arrays_per_engine; 877 /* in KHz */ 878 __u32 gpu_counter_freq; 879 __u64 max_engine_clock; 880 __u64 max_memory_clock; 881 /* cu information */ 882 __u32 cu_active_number; 883 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 884 __u32 cu_ao_mask; 885 __u32 cu_bitmap[4][4]; 886 /** Render backend pipe mask. One render backend is CB+DB. */ 887 __u32 enabled_rb_pipes_mask; 888 __u32 num_rb_pipes; 889 __u32 num_hw_gfx_contexts; 890 __u32 _pad; 891 __u64 ids_flags; 892 /** Starting virtual address for UMDs. */ 893 __u64 virtual_address_offset; 894 /** The maximum virtual address */ 895 __u64 virtual_address_max; 896 /** Required alignment of virtual addresses. */ 897 __u32 virtual_address_alignment; 898 /** Page table entry - fragment size */ 899 __u32 pte_fragment_size; 900 __u32 gart_page_size; 901 /** constant engine ram size*/ 902 __u32 ce_ram_size; 903 /** video memory type info*/ 904 __u32 vram_type; 905 /** video memory bit width*/ 906 __u32 vram_bit_width; 907 /* vce harvesting instance */ 908 __u32 vce_harvest_config; 909 /* gfx double offchip LDS buffers */ 910 __u32 gc_double_offchip_lds_buf; 911 /* NGG Primitive Buffer */ 912 __u64 prim_buf_gpu_addr; 913 /* NGG Position Buffer */ 914 __u64 pos_buf_gpu_addr; 915 /* NGG Control Sideband */ 916 __u64 cntl_sb_buf_gpu_addr; 917 /* NGG Parameter Cache */ 918 __u64 param_buf_gpu_addr; 919 __u32 prim_buf_size; 920 __u32 pos_buf_size; 921 __u32 cntl_sb_buf_size; 922 __u32 param_buf_size; 923 /* wavefront size*/ 924 __u32 wave_front_size; 925 /* shader visible vgprs*/ 926 __u32 num_shader_visible_vgprs; 927 /* CU per shader array*/ 928 __u32 num_cu_per_sh; 929 /* number of tcc blocks*/ 930 __u32 num_tcc_blocks; 931 /* gs vgt table depth*/ 932 __u32 gs_vgt_table_depth; 933 /* gs primitive buffer depth*/ 934 __u32 gs_prim_buffer_depth; 935 /* max gs wavefront per vgt*/ 936 __u32 max_gs_waves_per_vgt; 937 __u32 _pad1; 938 /* always on cu bitmap */ 939 __u32 cu_ao_bitmap[4][4]; 940 /** Starting high virtual address for UMDs. */ 941 __u64 high_va_offset; 942 /** The maximum high virtual address */ 943 __u64 high_va_max; 944 }; 945 946 struct drm_amdgpu_info_hw_ip { 947 /** Version of h/w IP */ 948 __u32 hw_ip_version_major; 949 __u32 hw_ip_version_minor; 950 /** Capabilities */ 951 __u64 capabilities_flags; 952 /** command buffer address start alignment*/ 953 __u32 ib_start_alignment; 954 /** command buffer size alignment*/ 955 __u32 ib_size_alignment; 956 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 957 __u32 available_rings; 958 __u32 _pad; 959 }; 960 961 struct drm_amdgpu_info_num_handles { 962 /** Max handles as supported by firmware for UVD */ 963 __u32 uvd_max_handles; 964 /** Handles currently in use for UVD */ 965 __u32 uvd_used_handles; 966 }; 967 968 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 969 970 struct drm_amdgpu_info_vce_clock_table_entry { 971 /** System clock */ 972 __u32 sclk; 973 /** Memory clock */ 974 __u32 mclk; 975 /** VCE clock */ 976 __u32 eclk; 977 __u32 pad; 978 }; 979 980 struct drm_amdgpu_info_vce_clock_table { 981 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 982 __u32 num_valid_entries; 983 __u32 pad; 984 }; 985 986 /* 987 * Supported GPU families 988 */ 989 #define AMDGPU_FAMILY_UNKNOWN 0 990 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 991 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 992 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 993 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 994 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 995 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 996 #define AMDGPU_FAMILY_RV 142 /* Raven */ 997 998 #if defined(__cplusplus) 999 } 1000 #endif 1001 1002 #endif 1003