1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 * 98 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for 99 * signalling user mode queues. 100 */ 101 #define AMDGPU_GEM_DOMAIN_CPU 0x1 102 #define AMDGPU_GEM_DOMAIN_GTT 0x2 103 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 104 #define AMDGPU_GEM_DOMAIN_GDS 0x8 105 #define AMDGPU_GEM_DOMAIN_GWS 0x10 106 #define AMDGPU_GEM_DOMAIN_OA 0x20 107 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 108 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 109 AMDGPU_GEM_DOMAIN_GTT | \ 110 AMDGPU_GEM_DOMAIN_VRAM | \ 111 AMDGPU_GEM_DOMAIN_GDS | \ 112 AMDGPU_GEM_DOMAIN_GWS | \ 113 AMDGPU_GEM_DOMAIN_OA | \ 114 AMDGPU_GEM_DOMAIN_DOORBELL) 115 116 /* Flag that CPU access will be required for the case of VRAM domain */ 117 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 118 /* Flag that CPU access will not work, this VRAM domain is invisible */ 119 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 120 /* Flag that USWC attributes should be used for GTT */ 121 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 122 /* Flag that the memory should be in VRAM and cleared */ 123 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 124 /* Flag that allocating the BO should use linear VRAM */ 125 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 126 /* Flag that BO is always valid in this VM */ 127 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 128 /* Flag that BO sharing will be explicitly synchronized */ 129 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 130 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 131 * for the second page onward should be set to NC. It should never 132 * be used by user space applications. 133 */ 134 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 135 /* Flag that BO may contain sensitive data that must be wiped before 136 * releasing the memory 137 */ 138 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 139 /* Flag that BO will be encrypted and that the TMZ bit should be 140 * set in the PTEs when mapping this buffer via GPUVM or 141 * accessing it with various hw blocks 142 */ 143 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 144 /* Flag that BO will be used only in preemptible context, which does 145 * not require GTT memory accounting 146 */ 147 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 148 /* Flag that BO can be discarded under memory pressure without keeping the 149 * content. 150 */ 151 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 152 /* Flag that BO is shared coherently between multiple devices or CPU threads. 153 * May depend on GPU instructions to flush caches explicitly 154 * 155 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 156 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 157 */ 158 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 159 /* Flag that BO should not be cached by GPU. Coherent without having to flush 160 * GPU caches explicitly 161 * 162 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 163 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 164 */ 165 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 166 167 struct drm_amdgpu_gem_create_in { 168 /** the requested memory size */ 169 __u64 bo_size; 170 /** physical start_addr alignment in bytes for some HW requirements */ 171 __u64 alignment; 172 /** the requested memory domains */ 173 __u64 domains; 174 /** allocation flags */ 175 __u64 domain_flags; 176 }; 177 178 struct drm_amdgpu_gem_create_out { 179 /** returned GEM object handle */ 180 __u32 handle; 181 __u32 _pad; 182 }; 183 184 union drm_amdgpu_gem_create { 185 struct drm_amdgpu_gem_create_in in; 186 struct drm_amdgpu_gem_create_out out; 187 }; 188 189 /** Opcode to create new residency list. */ 190 #define AMDGPU_BO_LIST_OP_CREATE 0 191 /** Opcode to destroy previously created residency list */ 192 #define AMDGPU_BO_LIST_OP_DESTROY 1 193 /** Opcode to update resource information in the list */ 194 #define AMDGPU_BO_LIST_OP_UPDATE 2 195 196 struct drm_amdgpu_bo_list_in { 197 /** Type of operation */ 198 __u32 operation; 199 /** Handle of list or 0 if we want to create one */ 200 __u32 list_handle; 201 /** Number of BOs in list */ 202 __u32 bo_number; 203 /** Size of each element describing BO */ 204 __u32 bo_info_size; 205 /** Pointer to array describing BOs */ 206 __u64 bo_info_ptr; 207 }; 208 209 struct drm_amdgpu_bo_list_entry { 210 /** Handle of BO */ 211 __u32 bo_handle; 212 /** New (if specified) BO priority to be used during migration */ 213 __u32 bo_priority; 214 }; 215 216 struct drm_amdgpu_bo_list_out { 217 /** Handle of resource list */ 218 __u32 list_handle; 219 __u32 _pad; 220 }; 221 222 union drm_amdgpu_bo_list { 223 struct drm_amdgpu_bo_list_in in; 224 struct drm_amdgpu_bo_list_out out; 225 }; 226 227 /* context related */ 228 #define AMDGPU_CTX_OP_ALLOC_CTX 1 229 #define AMDGPU_CTX_OP_FREE_CTX 2 230 #define AMDGPU_CTX_OP_QUERY_STATE 3 231 #define AMDGPU_CTX_OP_QUERY_STATE2 4 232 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 233 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 234 235 /* GPU reset status */ 236 #define AMDGPU_CTX_NO_RESET 0 237 /* this the context caused it */ 238 #define AMDGPU_CTX_GUILTY_RESET 1 239 /* some other context caused it */ 240 #define AMDGPU_CTX_INNOCENT_RESET 2 241 /* unknown cause */ 242 #define AMDGPU_CTX_UNKNOWN_RESET 3 243 244 /* indicate gpu reset occured after ctx created */ 245 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 246 /* indicate vram lost occured after ctx created */ 247 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 248 /* indicate some job from this context once cause gpu hang */ 249 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 250 /* indicate some errors are detected by RAS */ 251 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 252 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 253 /* indicate that the reset hasn't completed yet */ 254 #define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5) 255 256 /* Context priority level */ 257 #define AMDGPU_CTX_PRIORITY_UNSET -2048 258 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 259 #define AMDGPU_CTX_PRIORITY_LOW -512 260 #define AMDGPU_CTX_PRIORITY_NORMAL 0 261 /* 262 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 263 * CAP_SYS_NICE or DRM_MASTER 264 */ 265 #define AMDGPU_CTX_PRIORITY_HIGH 512 266 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 267 268 /* select a stable profiling pstate for perfmon tools */ 269 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 270 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 271 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 272 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 273 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 274 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 275 276 struct drm_amdgpu_ctx_in { 277 /** AMDGPU_CTX_OP_* */ 278 __u32 op; 279 /** Flags */ 280 __u32 flags; 281 __u32 ctx_id; 282 /** AMDGPU_CTX_PRIORITY_* */ 283 __s32 priority; 284 }; 285 286 union drm_amdgpu_ctx_out { 287 struct { 288 __u32 ctx_id; 289 __u32 _pad; 290 } alloc; 291 292 struct { 293 /** For future use, no flags defined so far */ 294 __u64 flags; 295 /** Number of resets caused by this context so far. */ 296 __u32 hangs; 297 /** Reset status since the last call of the ioctl. */ 298 __u32 reset_status; 299 } state; 300 301 struct { 302 __u32 flags; 303 __u32 _pad; 304 } pstate; 305 }; 306 307 union drm_amdgpu_ctx { 308 struct drm_amdgpu_ctx_in in; 309 union drm_amdgpu_ctx_out out; 310 }; 311 312 /* vm ioctl */ 313 #define AMDGPU_VM_OP_RESERVE_VMID 1 314 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 315 316 struct drm_amdgpu_vm_in { 317 /** AMDGPU_VM_OP_* */ 318 __u32 op; 319 __u32 flags; 320 }; 321 322 struct drm_amdgpu_vm_out { 323 /** For future use, no flags defined so far */ 324 __u64 flags; 325 }; 326 327 union drm_amdgpu_vm { 328 struct drm_amdgpu_vm_in in; 329 struct drm_amdgpu_vm_out out; 330 }; 331 332 /* sched ioctl */ 333 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 334 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 335 336 struct drm_amdgpu_sched_in { 337 /* AMDGPU_SCHED_OP_* */ 338 __u32 op; 339 __u32 fd; 340 /** AMDGPU_CTX_PRIORITY_* */ 341 __s32 priority; 342 __u32 ctx_id; 343 }; 344 345 union drm_amdgpu_sched { 346 struct drm_amdgpu_sched_in in; 347 }; 348 349 /* 350 * This is not a reliable API and you should expect it to fail for any 351 * number of reasons and have fallback path that do not use userptr to 352 * perform any operation. 353 */ 354 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 355 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 356 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 357 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 358 359 struct drm_amdgpu_gem_userptr { 360 __u64 addr; 361 __u64 size; 362 /* AMDGPU_GEM_USERPTR_* */ 363 __u32 flags; 364 /* Resulting GEM handle */ 365 __u32 handle; 366 }; 367 368 /* SI-CI-VI: */ 369 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 370 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 371 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 372 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 373 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 374 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 375 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 376 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 377 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 378 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 379 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 380 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 381 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 382 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 383 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 384 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 385 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 386 387 /* GFX9 and later: */ 388 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 389 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 390 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 391 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 392 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 393 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 394 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 395 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 396 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 397 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 398 #define AMDGPU_TILING_SCANOUT_SHIFT 63 399 #define AMDGPU_TILING_SCANOUT_MASK 0x1 400 401 /* Set/Get helpers for tiling flags. */ 402 #define AMDGPU_TILING_SET(field, value) \ 403 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 404 #define AMDGPU_TILING_GET(value, field) \ 405 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 406 407 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 408 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 409 410 /** The same structure is shared for input/output */ 411 struct drm_amdgpu_gem_metadata { 412 /** GEM Object handle */ 413 __u32 handle; 414 /** Do we want get or set metadata */ 415 __u32 op; 416 struct { 417 /** For future use, no flags defined so far */ 418 __u64 flags; 419 /** family specific tiling info */ 420 __u64 tiling_info; 421 __u32 data_size_bytes; 422 __u32 data[64]; 423 } data; 424 }; 425 426 struct drm_amdgpu_gem_mmap_in { 427 /** the GEM object handle */ 428 __u32 handle; 429 __u32 _pad; 430 }; 431 432 struct drm_amdgpu_gem_mmap_out { 433 /** mmap offset from the vma offset manager */ 434 __u64 addr_ptr; 435 }; 436 437 union drm_amdgpu_gem_mmap { 438 struct drm_amdgpu_gem_mmap_in in; 439 struct drm_amdgpu_gem_mmap_out out; 440 }; 441 442 struct drm_amdgpu_gem_wait_idle_in { 443 /** GEM object handle */ 444 __u32 handle; 445 /** For future use, no flags defined so far */ 446 __u32 flags; 447 /** Absolute timeout to wait */ 448 __u64 timeout; 449 }; 450 451 struct drm_amdgpu_gem_wait_idle_out { 452 /** BO status: 0 - BO is idle, 1 - BO is busy */ 453 __u32 status; 454 /** Returned current memory domain */ 455 __u32 domain; 456 }; 457 458 union drm_amdgpu_gem_wait_idle { 459 struct drm_amdgpu_gem_wait_idle_in in; 460 struct drm_amdgpu_gem_wait_idle_out out; 461 }; 462 463 struct drm_amdgpu_wait_cs_in { 464 /* Command submission handle 465 * handle equals 0 means none to wait for 466 * handle equals ~0ull means wait for the latest sequence number 467 */ 468 __u64 handle; 469 /** Absolute timeout to wait */ 470 __u64 timeout; 471 __u32 ip_type; 472 __u32 ip_instance; 473 __u32 ring; 474 __u32 ctx_id; 475 }; 476 477 struct drm_amdgpu_wait_cs_out { 478 /** CS status: 0 - CS completed, 1 - CS still busy */ 479 __u64 status; 480 }; 481 482 union drm_amdgpu_wait_cs { 483 struct drm_amdgpu_wait_cs_in in; 484 struct drm_amdgpu_wait_cs_out out; 485 }; 486 487 struct drm_amdgpu_fence { 488 __u32 ctx_id; 489 __u32 ip_type; 490 __u32 ip_instance; 491 __u32 ring; 492 __u64 seq_no; 493 }; 494 495 struct drm_amdgpu_wait_fences_in { 496 /** This points to uint64_t * which points to fences */ 497 __u64 fences; 498 __u32 fence_count; 499 __u32 wait_all; 500 __u64 timeout_ns; 501 }; 502 503 struct drm_amdgpu_wait_fences_out { 504 __u32 status; 505 __u32 first_signaled; 506 }; 507 508 union drm_amdgpu_wait_fences { 509 struct drm_amdgpu_wait_fences_in in; 510 struct drm_amdgpu_wait_fences_out out; 511 }; 512 513 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 514 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 515 516 /* Sets or returns a value associated with a buffer. */ 517 struct drm_amdgpu_gem_op { 518 /** GEM object handle */ 519 __u32 handle; 520 /** AMDGPU_GEM_OP_* */ 521 __u32 op; 522 /** Input or return value */ 523 __u64 value; 524 }; 525 526 #define AMDGPU_VA_OP_MAP 1 527 #define AMDGPU_VA_OP_UNMAP 2 528 #define AMDGPU_VA_OP_CLEAR 3 529 #define AMDGPU_VA_OP_REPLACE 4 530 531 /* Delay the page table update till the next CS */ 532 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 533 534 /* Mapping flags */ 535 /* readable mapping */ 536 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 537 /* writable mapping */ 538 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 539 /* executable mapping, new for VI */ 540 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 541 /* partially resident texture */ 542 #define AMDGPU_VM_PAGE_PRT (1 << 4) 543 /* MTYPE flags use bit 5 to 8 */ 544 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 545 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 546 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 547 /* Use Non Coherent MTYPE instead of default MTYPE */ 548 #define AMDGPU_VM_MTYPE_NC (1 << 5) 549 /* Use Write Combine MTYPE instead of default MTYPE */ 550 #define AMDGPU_VM_MTYPE_WC (2 << 5) 551 /* Use Cache Coherent MTYPE instead of default MTYPE */ 552 #define AMDGPU_VM_MTYPE_CC (3 << 5) 553 /* Use UnCached MTYPE instead of default MTYPE */ 554 #define AMDGPU_VM_MTYPE_UC (4 << 5) 555 /* Use Read Write MTYPE instead of default MTYPE */ 556 #define AMDGPU_VM_MTYPE_RW (5 << 5) 557 /* don't allocate MALL */ 558 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 559 560 struct drm_amdgpu_gem_va { 561 /** GEM object handle */ 562 __u32 handle; 563 __u32 _pad; 564 /** AMDGPU_VA_OP_* */ 565 __u32 operation; 566 /** AMDGPU_VM_PAGE_* */ 567 __u32 flags; 568 /** va address to assign . Must be correctly aligned.*/ 569 __u64 va_address; 570 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 571 __u64 offset_in_bo; 572 /** Specify mapping size. Must be correctly aligned. */ 573 __u64 map_size; 574 }; 575 576 #define AMDGPU_HW_IP_GFX 0 577 #define AMDGPU_HW_IP_COMPUTE 1 578 #define AMDGPU_HW_IP_DMA 2 579 #define AMDGPU_HW_IP_UVD 3 580 #define AMDGPU_HW_IP_VCE 4 581 #define AMDGPU_HW_IP_UVD_ENC 5 582 #define AMDGPU_HW_IP_VCN_DEC 6 583 /* 584 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 585 * both encoding and decoding jobs. 586 */ 587 #define AMDGPU_HW_IP_VCN_ENC 7 588 #define AMDGPU_HW_IP_VCN_JPEG 8 589 #define AMDGPU_HW_IP_NUM 9 590 591 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 592 593 #define AMDGPU_CHUNK_ID_IB 0x01 594 #define AMDGPU_CHUNK_ID_FENCE 0x02 595 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 596 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 597 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 598 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 599 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 600 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 601 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 602 #define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a 603 604 struct drm_amdgpu_cs_chunk { 605 __u32 chunk_id; 606 __u32 length_dw; 607 __u64 chunk_data; 608 }; 609 610 struct drm_amdgpu_cs_in { 611 /** Rendering context id */ 612 __u32 ctx_id; 613 /** Handle of resource list associated with CS */ 614 __u32 bo_list_handle; 615 __u32 num_chunks; 616 __u32 flags; 617 /** this points to __u64 * which point to cs chunks */ 618 __u64 chunks; 619 }; 620 621 struct drm_amdgpu_cs_out { 622 __u64 handle; 623 }; 624 625 union drm_amdgpu_cs { 626 struct drm_amdgpu_cs_in in; 627 struct drm_amdgpu_cs_out out; 628 }; 629 630 /* Specify flags to be used for IB */ 631 632 /* This IB should be submitted to CE */ 633 #define AMDGPU_IB_FLAG_CE (1<<0) 634 635 /* Preamble flag, which means the IB could be dropped if no context switch */ 636 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 637 638 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 639 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 640 641 /* The IB fence should do the L2 writeback but not invalidate any shader 642 * caches (L2/vL1/sL1/I$). */ 643 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 644 645 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 646 * This will reset wave ID counters for the IB. 647 */ 648 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 649 650 /* Flag the IB as secure (TMZ) 651 */ 652 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 653 654 /* Tell KMD to flush and invalidate caches 655 */ 656 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 657 658 struct drm_amdgpu_cs_chunk_ib { 659 __u32 _pad; 660 /** AMDGPU_IB_FLAG_* */ 661 __u32 flags; 662 /** Virtual address to begin IB execution */ 663 __u64 va_start; 664 /** Size of submission */ 665 __u32 ib_bytes; 666 /** HW IP to submit to */ 667 __u32 ip_type; 668 /** HW IP index of the same type to submit to */ 669 __u32 ip_instance; 670 /** Ring index to submit to */ 671 __u32 ring; 672 }; 673 674 struct drm_amdgpu_cs_chunk_dep { 675 __u32 ip_type; 676 __u32 ip_instance; 677 __u32 ring; 678 __u32 ctx_id; 679 __u64 handle; 680 }; 681 682 struct drm_amdgpu_cs_chunk_fence { 683 __u32 handle; 684 __u32 offset; 685 }; 686 687 struct drm_amdgpu_cs_chunk_sem { 688 __u32 handle; 689 }; 690 691 struct drm_amdgpu_cs_chunk_syncobj { 692 __u32 handle; 693 __u32 flags; 694 __u64 point; 695 }; 696 697 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 698 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 699 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 700 701 union drm_amdgpu_fence_to_handle { 702 struct { 703 struct drm_amdgpu_fence fence; 704 __u32 what; 705 __u32 pad; 706 } in; 707 struct { 708 __u32 handle; 709 } out; 710 }; 711 712 struct drm_amdgpu_cs_chunk_data { 713 union { 714 struct drm_amdgpu_cs_chunk_ib ib_data; 715 struct drm_amdgpu_cs_chunk_fence fence_data; 716 }; 717 }; 718 719 #define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1 720 721 struct drm_amdgpu_cs_chunk_cp_gfx_shadow { 722 __u64 shadow_va; 723 __u64 csa_va; 724 __u64 gds_va; 725 __u64 flags; 726 }; 727 728 /* 729 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 730 * 731 */ 732 #define AMDGPU_IDS_FLAGS_FUSION 0x1 733 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 734 #define AMDGPU_IDS_FLAGS_TMZ 0x4 735 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 736 737 /* indicate if acceleration can be working */ 738 #define AMDGPU_INFO_ACCEL_WORKING 0x00 739 /* get the crtc_id from the mode object id? */ 740 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 741 /* query hw IP info */ 742 #define AMDGPU_INFO_HW_IP_INFO 0x02 743 /* query hw IP instance count for the specified type */ 744 #define AMDGPU_INFO_HW_IP_COUNT 0x03 745 /* timestamp for GL_ARB_timer_query */ 746 #define AMDGPU_INFO_TIMESTAMP 0x05 747 /* Query the firmware version */ 748 #define AMDGPU_INFO_FW_VERSION 0x0e 749 /* Subquery id: Query VCE firmware version */ 750 #define AMDGPU_INFO_FW_VCE 0x1 751 /* Subquery id: Query UVD firmware version */ 752 #define AMDGPU_INFO_FW_UVD 0x2 753 /* Subquery id: Query GMC firmware version */ 754 #define AMDGPU_INFO_FW_GMC 0x03 755 /* Subquery id: Query GFX ME firmware version */ 756 #define AMDGPU_INFO_FW_GFX_ME 0x04 757 /* Subquery id: Query GFX PFP firmware version */ 758 #define AMDGPU_INFO_FW_GFX_PFP 0x05 759 /* Subquery id: Query GFX CE firmware version */ 760 #define AMDGPU_INFO_FW_GFX_CE 0x06 761 /* Subquery id: Query GFX RLC firmware version */ 762 #define AMDGPU_INFO_FW_GFX_RLC 0x07 763 /* Subquery id: Query GFX MEC firmware version */ 764 #define AMDGPU_INFO_FW_GFX_MEC 0x08 765 /* Subquery id: Query SMC firmware version */ 766 #define AMDGPU_INFO_FW_SMC 0x0a 767 /* Subquery id: Query SDMA firmware version */ 768 #define AMDGPU_INFO_FW_SDMA 0x0b 769 /* Subquery id: Query PSP SOS firmware version */ 770 #define AMDGPU_INFO_FW_SOS 0x0c 771 /* Subquery id: Query PSP ASD firmware version */ 772 #define AMDGPU_INFO_FW_ASD 0x0d 773 /* Subquery id: Query VCN firmware version */ 774 #define AMDGPU_INFO_FW_VCN 0x0e 775 /* Subquery id: Query GFX RLC SRLC firmware version */ 776 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 777 /* Subquery id: Query GFX RLC SRLG firmware version */ 778 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 779 /* Subquery id: Query GFX RLC SRLS firmware version */ 780 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 781 /* Subquery id: Query DMCU firmware version */ 782 #define AMDGPU_INFO_FW_DMCU 0x12 783 #define AMDGPU_INFO_FW_TA 0x13 784 /* Subquery id: Query DMCUB firmware version */ 785 #define AMDGPU_INFO_FW_DMCUB 0x14 786 /* Subquery id: Query TOC firmware version */ 787 #define AMDGPU_INFO_FW_TOC 0x15 788 /* Subquery id: Query CAP firmware version */ 789 #define AMDGPU_INFO_FW_CAP 0x16 790 /* Subquery id: Query GFX RLCP firmware version */ 791 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 792 /* Subquery id: Query GFX RLCV firmware version */ 793 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 794 /* Subquery id: Query MES_KIQ firmware version */ 795 #define AMDGPU_INFO_FW_MES_KIQ 0x19 796 /* Subquery id: Query MES firmware version */ 797 #define AMDGPU_INFO_FW_MES 0x1a 798 /* Subquery id: Query IMU firmware version */ 799 #define AMDGPU_INFO_FW_IMU 0x1b 800 801 /* number of bytes moved for TTM migration */ 802 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 803 /* the used VRAM size */ 804 #define AMDGPU_INFO_VRAM_USAGE 0x10 805 /* the used GTT size */ 806 #define AMDGPU_INFO_GTT_USAGE 0x11 807 /* Information about GDS, etc. resource configuration */ 808 #define AMDGPU_INFO_GDS_CONFIG 0x13 809 /* Query information about VRAM and GTT domains */ 810 #define AMDGPU_INFO_VRAM_GTT 0x14 811 /* Query information about register in MMR address space*/ 812 #define AMDGPU_INFO_READ_MMR_REG 0x15 813 /* Query information about device: rev id, family, etc. */ 814 #define AMDGPU_INFO_DEV_INFO 0x16 815 /* visible vram usage */ 816 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 817 /* number of TTM buffer evictions */ 818 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 819 /* Query memory about VRAM and GTT domains */ 820 #define AMDGPU_INFO_MEMORY 0x19 821 /* Query vce clock table */ 822 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 823 /* Query vbios related information */ 824 #define AMDGPU_INFO_VBIOS 0x1B 825 /* Subquery id: Query vbios size */ 826 #define AMDGPU_INFO_VBIOS_SIZE 0x1 827 /* Subquery id: Query vbios image */ 828 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 829 /* Subquery id: Query vbios info */ 830 #define AMDGPU_INFO_VBIOS_INFO 0x3 831 /* Query UVD handles */ 832 #define AMDGPU_INFO_NUM_HANDLES 0x1C 833 /* Query sensor related information */ 834 #define AMDGPU_INFO_SENSOR 0x1D 835 /* Subquery id: Query GPU shader clock */ 836 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 837 /* Subquery id: Query GPU memory clock */ 838 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 839 /* Subquery id: Query GPU temperature */ 840 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 841 /* Subquery id: Query GPU load */ 842 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 843 /* Subquery id: Query average GPU power */ 844 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 845 /* Subquery id: Query northbridge voltage */ 846 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 847 /* Subquery id: Query graphics voltage */ 848 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 849 /* Subquery id: Query GPU stable pstate shader clock */ 850 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 851 /* Subquery id: Query GPU stable pstate memory clock */ 852 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 853 /* Subquery id: Query GPU peak pstate shader clock */ 854 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 855 /* Subquery id: Query GPU peak pstate memory clock */ 856 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 857 /* Number of VRAM page faults on CPU access. */ 858 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 859 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 860 /* query ras mask of enabled features*/ 861 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 862 /* RAS MASK: UMC (VRAM) */ 863 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 864 /* RAS MASK: SDMA */ 865 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 866 /* RAS MASK: GFX */ 867 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 868 /* RAS MASK: MMHUB */ 869 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 870 /* RAS MASK: ATHUB */ 871 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 872 /* RAS MASK: PCIE */ 873 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 874 /* RAS MASK: HDP */ 875 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 876 /* RAS MASK: XGMI */ 877 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 878 /* RAS MASK: DF */ 879 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 880 /* RAS MASK: SMN */ 881 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 882 /* RAS MASK: SEM */ 883 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 884 /* RAS MASK: MP0 */ 885 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 886 /* RAS MASK: MP1 */ 887 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 888 /* RAS MASK: FUSE */ 889 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 890 /* query video encode/decode caps */ 891 #define AMDGPU_INFO_VIDEO_CAPS 0x21 892 /* Subquery id: Decode */ 893 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 894 /* Subquery id: Encode */ 895 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 896 /* Query the max number of IBs per gang per submission */ 897 #define AMDGPU_INFO_MAX_IBS 0x22 898 899 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 900 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 901 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 902 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 903 904 struct drm_amdgpu_query_fw { 905 /** AMDGPU_INFO_FW_* */ 906 __u32 fw_type; 907 /** 908 * Index of the IP if there are more IPs of 909 * the same type. 910 */ 911 __u32 ip_instance; 912 /** 913 * Index of the engine. Whether this is used depends 914 * on the firmware type. (e.g. MEC, SDMA) 915 */ 916 __u32 index; 917 __u32 _pad; 918 }; 919 920 /* Input structure for the INFO ioctl */ 921 struct drm_amdgpu_info { 922 /* Where the return value will be stored */ 923 __u64 return_pointer; 924 /* The size of the return value. Just like "size" in "snprintf", 925 * it limits how many bytes the kernel can write. */ 926 __u32 return_size; 927 /* The query request id. */ 928 __u32 query; 929 930 union { 931 struct { 932 __u32 id; 933 __u32 _pad; 934 } mode_crtc; 935 936 struct { 937 /** AMDGPU_HW_IP_* */ 938 __u32 type; 939 /** 940 * Index of the IP if there are more IPs of the same 941 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 942 */ 943 __u32 ip_instance; 944 } query_hw_ip; 945 946 struct { 947 __u32 dword_offset; 948 /** number of registers to read */ 949 __u32 count; 950 __u32 instance; 951 /** For future use, no flags defined so far */ 952 __u32 flags; 953 } read_mmr_reg; 954 955 struct drm_amdgpu_query_fw query_fw; 956 957 struct { 958 __u32 type; 959 __u32 offset; 960 } vbios_info; 961 962 struct { 963 __u32 type; 964 } sensor_info; 965 966 struct { 967 __u32 type; 968 } video_cap; 969 }; 970 }; 971 972 struct drm_amdgpu_info_gds { 973 /** GDS GFX partition size */ 974 __u32 gds_gfx_partition_size; 975 /** GDS compute partition size */ 976 __u32 compute_partition_size; 977 /** total GDS memory size */ 978 __u32 gds_total_size; 979 /** GWS size per GFX partition */ 980 __u32 gws_per_gfx_partition; 981 /** GSW size per compute partition */ 982 __u32 gws_per_compute_partition; 983 /** OA size per GFX partition */ 984 __u32 oa_per_gfx_partition; 985 /** OA size per compute partition */ 986 __u32 oa_per_compute_partition; 987 __u32 _pad; 988 }; 989 990 struct drm_amdgpu_info_vram_gtt { 991 __u64 vram_size; 992 __u64 vram_cpu_accessible_size; 993 __u64 gtt_size; 994 }; 995 996 struct drm_amdgpu_heap_info { 997 /** max. physical memory */ 998 __u64 total_heap_size; 999 1000 /** Theoretical max. available memory in the given heap */ 1001 __u64 usable_heap_size; 1002 1003 /** 1004 * Number of bytes allocated in the heap. This includes all processes 1005 * and private allocations in the kernel. It changes when new buffers 1006 * are allocated, freed, and moved. It cannot be larger than 1007 * heap_size. 1008 */ 1009 __u64 heap_usage; 1010 1011 /** 1012 * Theoretical possible max. size of buffer which 1013 * could be allocated in the given heap 1014 */ 1015 __u64 max_allocation; 1016 }; 1017 1018 struct drm_amdgpu_memory_info { 1019 struct drm_amdgpu_heap_info vram; 1020 struct drm_amdgpu_heap_info cpu_accessible_vram; 1021 struct drm_amdgpu_heap_info gtt; 1022 }; 1023 1024 struct drm_amdgpu_info_firmware { 1025 __u32 ver; 1026 __u32 feature; 1027 }; 1028 1029 struct drm_amdgpu_info_vbios { 1030 __u8 name[64]; 1031 __u8 vbios_pn[64]; 1032 __u32 version; 1033 __u32 pad; 1034 __u8 vbios_ver_str[32]; 1035 __u8 date[32]; 1036 }; 1037 1038 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1039 #define AMDGPU_VRAM_TYPE_GDDR1 1 1040 #define AMDGPU_VRAM_TYPE_DDR2 2 1041 #define AMDGPU_VRAM_TYPE_GDDR3 3 1042 #define AMDGPU_VRAM_TYPE_GDDR4 4 1043 #define AMDGPU_VRAM_TYPE_GDDR5 5 1044 #define AMDGPU_VRAM_TYPE_HBM 6 1045 #define AMDGPU_VRAM_TYPE_DDR3 7 1046 #define AMDGPU_VRAM_TYPE_DDR4 8 1047 #define AMDGPU_VRAM_TYPE_GDDR6 9 1048 #define AMDGPU_VRAM_TYPE_DDR5 10 1049 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1050 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1051 1052 struct drm_amdgpu_info_device { 1053 /** PCI Device ID */ 1054 __u32 device_id; 1055 /** Internal chip revision: A0, A1, etc.) */ 1056 __u32 chip_rev; 1057 __u32 external_rev; 1058 /** Revision id in PCI Config space */ 1059 __u32 pci_rev; 1060 __u32 family; 1061 __u32 num_shader_engines; 1062 __u32 num_shader_arrays_per_engine; 1063 /* in KHz */ 1064 __u32 gpu_counter_freq; 1065 __u64 max_engine_clock; 1066 __u64 max_memory_clock; 1067 /* cu information */ 1068 __u32 cu_active_number; 1069 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1070 __u32 cu_ao_mask; 1071 __u32 cu_bitmap[4][4]; 1072 /** Render backend pipe mask. One render backend is CB+DB. */ 1073 __u32 enabled_rb_pipes_mask; 1074 __u32 num_rb_pipes; 1075 __u32 num_hw_gfx_contexts; 1076 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1077 __u32 pcie_gen; 1078 __u64 ids_flags; 1079 /** Starting virtual address for UMDs. */ 1080 __u64 virtual_address_offset; 1081 /** The maximum virtual address */ 1082 __u64 virtual_address_max; 1083 /** Required alignment of virtual addresses. */ 1084 __u32 virtual_address_alignment; 1085 /** Page table entry - fragment size */ 1086 __u32 pte_fragment_size; 1087 __u32 gart_page_size; 1088 /** constant engine ram size*/ 1089 __u32 ce_ram_size; 1090 /** video memory type info*/ 1091 __u32 vram_type; 1092 /** video memory bit width*/ 1093 __u32 vram_bit_width; 1094 /* vce harvesting instance */ 1095 __u32 vce_harvest_config; 1096 /* gfx double offchip LDS buffers */ 1097 __u32 gc_double_offchip_lds_buf; 1098 /* NGG Primitive Buffer */ 1099 __u64 prim_buf_gpu_addr; 1100 /* NGG Position Buffer */ 1101 __u64 pos_buf_gpu_addr; 1102 /* NGG Control Sideband */ 1103 __u64 cntl_sb_buf_gpu_addr; 1104 /* NGG Parameter Cache */ 1105 __u64 param_buf_gpu_addr; 1106 __u32 prim_buf_size; 1107 __u32 pos_buf_size; 1108 __u32 cntl_sb_buf_size; 1109 __u32 param_buf_size; 1110 /* wavefront size*/ 1111 __u32 wave_front_size; 1112 /* shader visible vgprs*/ 1113 __u32 num_shader_visible_vgprs; 1114 /* CU per shader array*/ 1115 __u32 num_cu_per_sh; 1116 /* number of tcc blocks*/ 1117 __u32 num_tcc_blocks; 1118 /* gs vgt table depth*/ 1119 __u32 gs_vgt_table_depth; 1120 /* gs primitive buffer depth*/ 1121 __u32 gs_prim_buffer_depth; 1122 /* max gs wavefront per vgt*/ 1123 __u32 max_gs_waves_per_vgt; 1124 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1125 __u32 pcie_num_lanes; 1126 /* always on cu bitmap */ 1127 __u32 cu_ao_bitmap[4][4]; 1128 /** Starting high virtual address for UMDs. */ 1129 __u64 high_va_offset; 1130 /** The maximum high virtual address */ 1131 __u64 high_va_max; 1132 /* gfx10 pa_sc_tile_steering_override */ 1133 __u32 pa_sc_tile_steering_override; 1134 /* disabled TCCs */ 1135 __u64 tcc_disabled_mask; 1136 __u64 min_engine_clock; 1137 __u64 min_memory_clock; 1138 /* The following fields are only set on gfx11+, older chips set 0. */ 1139 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1140 __u32 num_sqc_per_wgp; 1141 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1142 __u32 sqc_inst_cache_size; 1143 __u32 gl1c_cache_size; 1144 __u32 gl2c_cache_size; 1145 __u64 mall_size; /* AKA infinity cache */ 1146 /* high 32 bits of the rb pipes mask */ 1147 __u32 enabled_rb_pipes_mask_hi; 1148 /* shadow area size for gfx11 */ 1149 __u32 shadow_size; 1150 /* shadow area base virtual alignment for gfx11 */ 1151 __u32 shadow_alignment; 1152 /* context save area size for gfx11 */ 1153 __u32 csa_size; 1154 /* context save area base virtual alignment for gfx11 */ 1155 __u32 csa_alignment; 1156 }; 1157 1158 struct drm_amdgpu_info_hw_ip { 1159 /** Version of h/w IP */ 1160 __u32 hw_ip_version_major; 1161 __u32 hw_ip_version_minor; 1162 /** Capabilities */ 1163 __u64 capabilities_flags; 1164 /** command buffer address start alignment*/ 1165 __u32 ib_start_alignment; 1166 /** command buffer size alignment*/ 1167 __u32 ib_size_alignment; 1168 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1169 __u32 available_rings; 1170 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1171 __u32 ip_discovery_version; 1172 }; 1173 1174 struct drm_amdgpu_info_num_handles { 1175 /** Max handles as supported by firmware for UVD */ 1176 __u32 uvd_max_handles; 1177 /** Handles currently in use for UVD */ 1178 __u32 uvd_used_handles; 1179 }; 1180 1181 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1182 1183 struct drm_amdgpu_info_vce_clock_table_entry { 1184 /** System clock */ 1185 __u32 sclk; 1186 /** Memory clock */ 1187 __u32 mclk; 1188 /** VCE clock */ 1189 __u32 eclk; 1190 __u32 pad; 1191 }; 1192 1193 struct drm_amdgpu_info_vce_clock_table { 1194 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1195 __u32 num_valid_entries; 1196 __u32 pad; 1197 }; 1198 1199 /* query video encode/decode caps */ 1200 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1201 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1202 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1203 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1204 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1205 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1206 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1207 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1208 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1209 1210 struct drm_amdgpu_info_video_codec_info { 1211 __u32 valid; 1212 __u32 max_width; 1213 __u32 max_height; 1214 __u32 max_pixels_per_frame; 1215 __u32 max_level; 1216 __u32 pad; 1217 }; 1218 1219 struct drm_amdgpu_info_video_caps { 1220 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1221 }; 1222 1223 /* 1224 * Supported GPU families 1225 */ 1226 #define AMDGPU_FAMILY_UNKNOWN 0 1227 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1228 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1229 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1230 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1231 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1232 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1233 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1234 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1235 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1236 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1237 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1238 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1239 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1240 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1241 1242 #if defined(__cplusplus) 1243 } 1244 #endif 1245 1246 #endif 1247