1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linezrized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that create shadow bo(GTT) while allocating vram bo */ 120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 121 /* Flag that allocating the BO should use linear VRAM */ 122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123 /* Flag that BO is always valid in this VM */ 124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125 /* Flag that BO sharing will be explicitly synchronized */ 126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128 * for the second page onward should be set to NC. 129 */ 130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 131 /* Flag that BO may contain sensitive data that must be wiped before 132 * releasing the memory 133 */ 134 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 135 136 struct drm_amdgpu_gem_create_in { 137 /** the requested memory size */ 138 __u64 bo_size; 139 /** physical start_addr alignment in bytes for some HW requirements */ 140 __u64 alignment; 141 /** the requested memory domains */ 142 __u64 domains; 143 /** allocation flags */ 144 __u64 domain_flags; 145 }; 146 147 struct drm_amdgpu_gem_create_out { 148 /** returned GEM object handle */ 149 __u32 handle; 150 __u32 _pad; 151 }; 152 153 union drm_amdgpu_gem_create { 154 struct drm_amdgpu_gem_create_in in; 155 struct drm_amdgpu_gem_create_out out; 156 }; 157 158 /** Opcode to create new residency list. */ 159 #define AMDGPU_BO_LIST_OP_CREATE 0 160 /** Opcode to destroy previously created residency list */ 161 #define AMDGPU_BO_LIST_OP_DESTROY 1 162 /** Opcode to update resource information in the list */ 163 #define AMDGPU_BO_LIST_OP_UPDATE 2 164 165 struct drm_amdgpu_bo_list_in { 166 /** Type of operation */ 167 __u32 operation; 168 /** Handle of list or 0 if we want to create one */ 169 __u32 list_handle; 170 /** Number of BOs in list */ 171 __u32 bo_number; 172 /** Size of each element describing BO */ 173 __u32 bo_info_size; 174 /** Pointer to array describing BOs */ 175 __u64 bo_info_ptr; 176 }; 177 178 struct drm_amdgpu_bo_list_entry { 179 /** Handle of BO */ 180 __u32 bo_handle; 181 /** New (if specified) BO priority to be used during migration */ 182 __u32 bo_priority; 183 }; 184 185 struct drm_amdgpu_bo_list_out { 186 /** Handle of resource list */ 187 __u32 list_handle; 188 __u32 _pad; 189 }; 190 191 union drm_amdgpu_bo_list { 192 struct drm_amdgpu_bo_list_in in; 193 struct drm_amdgpu_bo_list_out out; 194 }; 195 196 /* context related */ 197 #define AMDGPU_CTX_OP_ALLOC_CTX 1 198 #define AMDGPU_CTX_OP_FREE_CTX 2 199 #define AMDGPU_CTX_OP_QUERY_STATE 3 200 #define AMDGPU_CTX_OP_QUERY_STATE2 4 201 202 /* GPU reset status */ 203 #define AMDGPU_CTX_NO_RESET 0 204 /* this the context caused it */ 205 #define AMDGPU_CTX_GUILTY_RESET 1 206 /* some other context caused it */ 207 #define AMDGPU_CTX_INNOCENT_RESET 2 208 /* unknown cause */ 209 #define AMDGPU_CTX_UNKNOWN_RESET 3 210 211 /* indicate gpu reset occured after ctx created */ 212 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 213 /* indicate vram lost occured after ctx created */ 214 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 215 /* indicate some job from this context once cause gpu hang */ 216 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 217 /* indicate some errors are detected by RAS */ 218 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 219 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 220 221 /* Context priority level */ 222 #define AMDGPU_CTX_PRIORITY_UNSET -2048 223 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 224 #define AMDGPU_CTX_PRIORITY_LOW -512 225 #define AMDGPU_CTX_PRIORITY_NORMAL 0 226 /* 227 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 228 * CAP_SYS_NICE or DRM_MASTER 229 */ 230 #define AMDGPU_CTX_PRIORITY_HIGH 512 231 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 232 233 struct drm_amdgpu_ctx_in { 234 /** AMDGPU_CTX_OP_* */ 235 __u32 op; 236 /** For future use, no flags defined so far */ 237 __u32 flags; 238 __u32 ctx_id; 239 /** AMDGPU_CTX_PRIORITY_* */ 240 __s32 priority; 241 }; 242 243 union drm_amdgpu_ctx_out { 244 struct { 245 __u32 ctx_id; 246 __u32 _pad; 247 } alloc; 248 249 struct { 250 /** For future use, no flags defined so far */ 251 __u64 flags; 252 /** Number of resets caused by this context so far. */ 253 __u32 hangs; 254 /** Reset status since the last call of the ioctl. */ 255 __u32 reset_status; 256 } state; 257 }; 258 259 union drm_amdgpu_ctx { 260 struct drm_amdgpu_ctx_in in; 261 union drm_amdgpu_ctx_out out; 262 }; 263 264 /* vm ioctl */ 265 #define AMDGPU_VM_OP_RESERVE_VMID 1 266 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 267 268 struct drm_amdgpu_vm_in { 269 /** AMDGPU_VM_OP_* */ 270 __u32 op; 271 __u32 flags; 272 }; 273 274 struct drm_amdgpu_vm_out { 275 /** For future use, no flags defined so far */ 276 __u64 flags; 277 }; 278 279 union drm_amdgpu_vm { 280 struct drm_amdgpu_vm_in in; 281 struct drm_amdgpu_vm_out out; 282 }; 283 284 /* sched ioctl */ 285 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 286 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 287 288 struct drm_amdgpu_sched_in { 289 /* AMDGPU_SCHED_OP_* */ 290 __u32 op; 291 __u32 fd; 292 /** AMDGPU_CTX_PRIORITY_* */ 293 __s32 priority; 294 __u32 ctx_id; 295 }; 296 297 union drm_amdgpu_sched { 298 struct drm_amdgpu_sched_in in; 299 }; 300 301 /* 302 * This is not a reliable API and you should expect it to fail for any 303 * number of reasons and have fallback path that do not use userptr to 304 * perform any operation. 305 */ 306 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 307 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 308 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 309 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 310 311 struct drm_amdgpu_gem_userptr { 312 __u64 addr; 313 __u64 size; 314 /* AMDGPU_GEM_USERPTR_* */ 315 __u32 flags; 316 /* Resulting GEM handle */ 317 __u32 handle; 318 }; 319 320 /* SI-CI-VI: */ 321 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 322 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 323 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 324 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 325 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 326 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 327 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 328 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 329 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 330 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 331 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 332 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 333 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 334 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 335 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 336 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 337 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 338 339 /* GFX9 and later: */ 340 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 341 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 342 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 343 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 344 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 345 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 346 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 347 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 348 349 /* Set/Get helpers for tiling flags. */ 350 #define AMDGPU_TILING_SET(field, value) \ 351 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 352 #define AMDGPU_TILING_GET(value, field) \ 353 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 354 355 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 356 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 357 358 /** The same structure is shared for input/output */ 359 struct drm_amdgpu_gem_metadata { 360 /** GEM Object handle */ 361 __u32 handle; 362 /** Do we want get or set metadata */ 363 __u32 op; 364 struct { 365 /** For future use, no flags defined so far */ 366 __u64 flags; 367 /** family specific tiling info */ 368 __u64 tiling_info; 369 __u32 data_size_bytes; 370 __u32 data[64]; 371 } data; 372 }; 373 374 struct drm_amdgpu_gem_mmap_in { 375 /** the GEM object handle */ 376 __u32 handle; 377 __u32 _pad; 378 }; 379 380 struct drm_amdgpu_gem_mmap_out { 381 /** mmap offset from the vma offset manager */ 382 __u64 addr_ptr; 383 }; 384 385 union drm_amdgpu_gem_mmap { 386 struct drm_amdgpu_gem_mmap_in in; 387 struct drm_amdgpu_gem_mmap_out out; 388 }; 389 390 struct drm_amdgpu_gem_wait_idle_in { 391 /** GEM object handle */ 392 __u32 handle; 393 /** For future use, no flags defined so far */ 394 __u32 flags; 395 /** Absolute timeout to wait */ 396 __u64 timeout; 397 }; 398 399 struct drm_amdgpu_gem_wait_idle_out { 400 /** BO status: 0 - BO is idle, 1 - BO is busy */ 401 __u32 status; 402 /** Returned current memory domain */ 403 __u32 domain; 404 }; 405 406 union drm_amdgpu_gem_wait_idle { 407 struct drm_amdgpu_gem_wait_idle_in in; 408 struct drm_amdgpu_gem_wait_idle_out out; 409 }; 410 411 struct drm_amdgpu_wait_cs_in { 412 /* Command submission handle 413 * handle equals 0 means none to wait for 414 * handle equals ~0ull means wait for the latest sequence number 415 */ 416 __u64 handle; 417 /** Absolute timeout to wait */ 418 __u64 timeout; 419 __u32 ip_type; 420 __u32 ip_instance; 421 __u32 ring; 422 __u32 ctx_id; 423 }; 424 425 struct drm_amdgpu_wait_cs_out { 426 /** CS status: 0 - CS completed, 1 - CS still busy */ 427 __u64 status; 428 }; 429 430 union drm_amdgpu_wait_cs { 431 struct drm_amdgpu_wait_cs_in in; 432 struct drm_amdgpu_wait_cs_out out; 433 }; 434 435 struct drm_amdgpu_fence { 436 __u32 ctx_id; 437 __u32 ip_type; 438 __u32 ip_instance; 439 __u32 ring; 440 __u64 seq_no; 441 }; 442 443 struct drm_amdgpu_wait_fences_in { 444 /** This points to uint64_t * which points to fences */ 445 __u64 fences; 446 __u32 fence_count; 447 __u32 wait_all; 448 __u64 timeout_ns; 449 }; 450 451 struct drm_amdgpu_wait_fences_out { 452 __u32 status; 453 __u32 first_signaled; 454 }; 455 456 union drm_amdgpu_wait_fences { 457 struct drm_amdgpu_wait_fences_in in; 458 struct drm_amdgpu_wait_fences_out out; 459 }; 460 461 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 462 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 463 464 /* Sets or returns a value associated with a buffer. */ 465 struct drm_amdgpu_gem_op { 466 /** GEM object handle */ 467 __u32 handle; 468 /** AMDGPU_GEM_OP_* */ 469 __u32 op; 470 /** Input or return value */ 471 __u64 value; 472 }; 473 474 #define AMDGPU_VA_OP_MAP 1 475 #define AMDGPU_VA_OP_UNMAP 2 476 #define AMDGPU_VA_OP_CLEAR 3 477 #define AMDGPU_VA_OP_REPLACE 4 478 479 /* Delay the page table update till the next CS */ 480 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 481 482 /* Mapping flags */ 483 /* readable mapping */ 484 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 485 /* writable mapping */ 486 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 487 /* executable mapping, new for VI */ 488 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 489 /* partially resident texture */ 490 #define AMDGPU_VM_PAGE_PRT (1 << 4) 491 /* MTYPE flags use bit 5 to 8 */ 492 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 493 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 494 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 495 /* Use NC MTYPE instead of default MTYPE */ 496 #define AMDGPU_VM_MTYPE_NC (1 << 5) 497 /* Use WC MTYPE instead of default MTYPE */ 498 #define AMDGPU_VM_MTYPE_WC (2 << 5) 499 /* Use CC MTYPE instead of default MTYPE */ 500 #define AMDGPU_VM_MTYPE_CC (3 << 5) 501 /* Use UC MTYPE instead of default MTYPE */ 502 #define AMDGPU_VM_MTYPE_UC (4 << 5) 503 504 struct drm_amdgpu_gem_va { 505 /** GEM object handle */ 506 __u32 handle; 507 __u32 _pad; 508 /** AMDGPU_VA_OP_* */ 509 __u32 operation; 510 /** AMDGPU_VM_PAGE_* */ 511 __u32 flags; 512 /** va address to assign . Must be correctly aligned.*/ 513 __u64 va_address; 514 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 515 __u64 offset_in_bo; 516 /** Specify mapping size. Must be correctly aligned. */ 517 __u64 map_size; 518 }; 519 520 #define AMDGPU_HW_IP_GFX 0 521 #define AMDGPU_HW_IP_COMPUTE 1 522 #define AMDGPU_HW_IP_DMA 2 523 #define AMDGPU_HW_IP_UVD 3 524 #define AMDGPU_HW_IP_VCE 4 525 #define AMDGPU_HW_IP_UVD_ENC 5 526 #define AMDGPU_HW_IP_VCN_DEC 6 527 #define AMDGPU_HW_IP_VCN_ENC 7 528 #define AMDGPU_HW_IP_VCN_JPEG 8 529 #define AMDGPU_HW_IP_NUM 9 530 531 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 532 533 #define AMDGPU_CHUNK_ID_IB 0x01 534 #define AMDGPU_CHUNK_ID_FENCE 0x02 535 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 536 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 537 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 538 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 539 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 540 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 541 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 542 543 struct drm_amdgpu_cs_chunk { 544 __u32 chunk_id; 545 __u32 length_dw; 546 __u64 chunk_data; 547 }; 548 549 struct drm_amdgpu_cs_in { 550 /** Rendering context id */ 551 __u32 ctx_id; 552 /** Handle of resource list associated with CS */ 553 __u32 bo_list_handle; 554 __u32 num_chunks; 555 __u32 _pad; 556 /** this points to __u64 * which point to cs chunks */ 557 __u64 chunks; 558 }; 559 560 struct drm_amdgpu_cs_out { 561 __u64 handle; 562 }; 563 564 union drm_amdgpu_cs { 565 struct drm_amdgpu_cs_in in; 566 struct drm_amdgpu_cs_out out; 567 }; 568 569 /* Specify flags to be used for IB */ 570 571 /* This IB should be submitted to CE */ 572 #define AMDGPU_IB_FLAG_CE (1<<0) 573 574 /* Preamble flag, which means the IB could be dropped if no context switch */ 575 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 576 577 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 578 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 579 580 /* The IB fence should do the L2 writeback but not invalidate any shader 581 * caches (L2/vL1/sL1/I$). */ 582 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 583 584 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 585 * This will reset wave ID counters for the IB. 586 */ 587 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 588 589 struct drm_amdgpu_cs_chunk_ib { 590 __u32 _pad; 591 /** AMDGPU_IB_FLAG_* */ 592 __u32 flags; 593 /** Virtual address to begin IB execution */ 594 __u64 va_start; 595 /** Size of submission */ 596 __u32 ib_bytes; 597 /** HW IP to submit to */ 598 __u32 ip_type; 599 /** HW IP index of the same type to submit to */ 600 __u32 ip_instance; 601 /** Ring index to submit to */ 602 __u32 ring; 603 }; 604 605 struct drm_amdgpu_cs_chunk_dep { 606 __u32 ip_type; 607 __u32 ip_instance; 608 __u32 ring; 609 __u32 ctx_id; 610 __u64 handle; 611 }; 612 613 struct drm_amdgpu_cs_chunk_fence { 614 __u32 handle; 615 __u32 offset; 616 }; 617 618 struct drm_amdgpu_cs_chunk_sem { 619 __u32 handle; 620 }; 621 622 struct drm_amdgpu_cs_chunk_syncobj { 623 __u32 handle; 624 __u32 flags; 625 __u64 point; 626 }; 627 628 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 629 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 630 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 631 632 union drm_amdgpu_fence_to_handle { 633 struct { 634 struct drm_amdgpu_fence fence; 635 __u32 what; 636 __u32 pad; 637 } in; 638 struct { 639 __u32 handle; 640 } out; 641 }; 642 643 struct drm_amdgpu_cs_chunk_data { 644 union { 645 struct drm_amdgpu_cs_chunk_ib ib_data; 646 struct drm_amdgpu_cs_chunk_fence fence_data; 647 }; 648 }; 649 650 /** 651 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 652 * 653 */ 654 #define AMDGPU_IDS_FLAGS_FUSION 0x1 655 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 656 657 /* indicate if acceleration can be working */ 658 #define AMDGPU_INFO_ACCEL_WORKING 0x00 659 /* get the crtc_id from the mode object id? */ 660 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 661 /* query hw IP info */ 662 #define AMDGPU_INFO_HW_IP_INFO 0x02 663 /* query hw IP instance count for the specified type */ 664 #define AMDGPU_INFO_HW_IP_COUNT 0x03 665 /* timestamp for GL_ARB_timer_query */ 666 #define AMDGPU_INFO_TIMESTAMP 0x05 667 /* Query the firmware version */ 668 #define AMDGPU_INFO_FW_VERSION 0x0e 669 /* Subquery id: Query VCE firmware version */ 670 #define AMDGPU_INFO_FW_VCE 0x1 671 /* Subquery id: Query UVD firmware version */ 672 #define AMDGPU_INFO_FW_UVD 0x2 673 /* Subquery id: Query GMC firmware version */ 674 #define AMDGPU_INFO_FW_GMC 0x03 675 /* Subquery id: Query GFX ME firmware version */ 676 #define AMDGPU_INFO_FW_GFX_ME 0x04 677 /* Subquery id: Query GFX PFP firmware version */ 678 #define AMDGPU_INFO_FW_GFX_PFP 0x05 679 /* Subquery id: Query GFX CE firmware version */ 680 #define AMDGPU_INFO_FW_GFX_CE 0x06 681 /* Subquery id: Query GFX RLC firmware version */ 682 #define AMDGPU_INFO_FW_GFX_RLC 0x07 683 /* Subquery id: Query GFX MEC firmware version */ 684 #define AMDGPU_INFO_FW_GFX_MEC 0x08 685 /* Subquery id: Query SMC firmware version */ 686 #define AMDGPU_INFO_FW_SMC 0x0a 687 /* Subquery id: Query SDMA firmware version */ 688 #define AMDGPU_INFO_FW_SDMA 0x0b 689 /* Subquery id: Query PSP SOS firmware version */ 690 #define AMDGPU_INFO_FW_SOS 0x0c 691 /* Subquery id: Query PSP ASD firmware version */ 692 #define AMDGPU_INFO_FW_ASD 0x0d 693 /* Subquery id: Query VCN firmware version */ 694 #define AMDGPU_INFO_FW_VCN 0x0e 695 /* Subquery id: Query GFX RLC SRLC firmware version */ 696 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 697 /* Subquery id: Query GFX RLC SRLG firmware version */ 698 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 699 /* Subquery id: Query GFX RLC SRLS firmware version */ 700 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 701 /* Subquery id: Query DMCU firmware version */ 702 #define AMDGPU_INFO_FW_DMCU 0x12 703 #define AMDGPU_INFO_FW_TA 0x13 704 /* number of bytes moved for TTM migration */ 705 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 706 /* the used VRAM size */ 707 #define AMDGPU_INFO_VRAM_USAGE 0x10 708 /* the used GTT size */ 709 #define AMDGPU_INFO_GTT_USAGE 0x11 710 /* Information about GDS, etc. resource configuration */ 711 #define AMDGPU_INFO_GDS_CONFIG 0x13 712 /* Query information about VRAM and GTT domains */ 713 #define AMDGPU_INFO_VRAM_GTT 0x14 714 /* Query information about register in MMR address space*/ 715 #define AMDGPU_INFO_READ_MMR_REG 0x15 716 /* Query information about device: rev id, family, etc. */ 717 #define AMDGPU_INFO_DEV_INFO 0x16 718 /* visible vram usage */ 719 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 720 /* number of TTM buffer evictions */ 721 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 722 /* Query memory about VRAM and GTT domains */ 723 #define AMDGPU_INFO_MEMORY 0x19 724 /* Query vce clock table */ 725 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 726 /* Query vbios related information */ 727 #define AMDGPU_INFO_VBIOS 0x1B 728 /* Subquery id: Query vbios size */ 729 #define AMDGPU_INFO_VBIOS_SIZE 0x1 730 /* Subquery id: Query vbios image */ 731 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 732 /* Query UVD handles */ 733 #define AMDGPU_INFO_NUM_HANDLES 0x1C 734 /* Query sensor related information */ 735 #define AMDGPU_INFO_SENSOR 0x1D 736 /* Subquery id: Query GPU shader clock */ 737 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 738 /* Subquery id: Query GPU memory clock */ 739 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 740 /* Subquery id: Query GPU temperature */ 741 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 742 /* Subquery id: Query GPU load */ 743 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 744 /* Subquery id: Query average GPU power */ 745 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 746 /* Subquery id: Query northbridge voltage */ 747 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 748 /* Subquery id: Query graphics voltage */ 749 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 750 /* Subquery id: Query GPU stable pstate shader clock */ 751 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 752 /* Subquery id: Query GPU stable pstate memory clock */ 753 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 754 /* Number of VRAM page faults on CPU access. */ 755 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 756 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 757 /* query ras mask of enabled features*/ 758 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 759 760 /* RAS MASK: UMC (VRAM) */ 761 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 762 /* RAS MASK: SDMA */ 763 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 764 /* RAS MASK: GFX */ 765 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 766 /* RAS MASK: MMHUB */ 767 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 768 /* RAS MASK: ATHUB */ 769 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 770 /* RAS MASK: PCIE */ 771 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 772 /* RAS MASK: HDP */ 773 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 774 /* RAS MASK: XGMI */ 775 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 776 /* RAS MASK: DF */ 777 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 778 /* RAS MASK: SMN */ 779 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 780 /* RAS MASK: SEM */ 781 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 782 /* RAS MASK: MP0 */ 783 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 784 /* RAS MASK: MP1 */ 785 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 786 /* RAS MASK: FUSE */ 787 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 788 789 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 790 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 791 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 792 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 793 794 struct drm_amdgpu_query_fw { 795 /** AMDGPU_INFO_FW_* */ 796 __u32 fw_type; 797 /** 798 * Index of the IP if there are more IPs of 799 * the same type. 800 */ 801 __u32 ip_instance; 802 /** 803 * Index of the engine. Whether this is used depends 804 * on the firmware type. (e.g. MEC, SDMA) 805 */ 806 __u32 index; 807 __u32 _pad; 808 }; 809 810 /* Input structure for the INFO ioctl */ 811 struct drm_amdgpu_info { 812 /* Where the return value will be stored */ 813 __u64 return_pointer; 814 /* The size of the return value. Just like "size" in "snprintf", 815 * it limits how many bytes the kernel can write. */ 816 __u32 return_size; 817 /* The query request id. */ 818 __u32 query; 819 820 union { 821 struct { 822 __u32 id; 823 __u32 _pad; 824 } mode_crtc; 825 826 struct { 827 /** AMDGPU_HW_IP_* */ 828 __u32 type; 829 /** 830 * Index of the IP if there are more IPs of the same 831 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 832 */ 833 __u32 ip_instance; 834 } query_hw_ip; 835 836 struct { 837 __u32 dword_offset; 838 /** number of registers to read */ 839 __u32 count; 840 __u32 instance; 841 /** For future use, no flags defined so far */ 842 __u32 flags; 843 } read_mmr_reg; 844 845 struct drm_amdgpu_query_fw query_fw; 846 847 struct { 848 __u32 type; 849 __u32 offset; 850 } vbios_info; 851 852 struct { 853 __u32 type; 854 } sensor_info; 855 }; 856 }; 857 858 struct drm_amdgpu_info_gds { 859 /** GDS GFX partition size */ 860 __u32 gds_gfx_partition_size; 861 /** GDS compute partition size */ 862 __u32 compute_partition_size; 863 /** total GDS memory size */ 864 __u32 gds_total_size; 865 /** GWS size per GFX partition */ 866 __u32 gws_per_gfx_partition; 867 /** GSW size per compute partition */ 868 __u32 gws_per_compute_partition; 869 /** OA size per GFX partition */ 870 __u32 oa_per_gfx_partition; 871 /** OA size per compute partition */ 872 __u32 oa_per_compute_partition; 873 __u32 _pad; 874 }; 875 876 struct drm_amdgpu_info_vram_gtt { 877 __u64 vram_size; 878 __u64 vram_cpu_accessible_size; 879 __u64 gtt_size; 880 }; 881 882 struct drm_amdgpu_heap_info { 883 /** max. physical memory */ 884 __u64 total_heap_size; 885 886 /** Theoretical max. available memory in the given heap */ 887 __u64 usable_heap_size; 888 889 /** 890 * Number of bytes allocated in the heap. This includes all processes 891 * and private allocations in the kernel. It changes when new buffers 892 * are allocated, freed, and moved. It cannot be larger than 893 * heap_size. 894 */ 895 __u64 heap_usage; 896 897 /** 898 * Theoretical possible max. size of buffer which 899 * could be allocated in the given heap 900 */ 901 __u64 max_allocation; 902 }; 903 904 struct drm_amdgpu_memory_info { 905 struct drm_amdgpu_heap_info vram; 906 struct drm_amdgpu_heap_info cpu_accessible_vram; 907 struct drm_amdgpu_heap_info gtt; 908 }; 909 910 struct drm_amdgpu_info_firmware { 911 __u32 ver; 912 __u32 feature; 913 }; 914 915 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 916 #define AMDGPU_VRAM_TYPE_GDDR1 1 917 #define AMDGPU_VRAM_TYPE_DDR2 2 918 #define AMDGPU_VRAM_TYPE_GDDR3 3 919 #define AMDGPU_VRAM_TYPE_GDDR4 4 920 #define AMDGPU_VRAM_TYPE_GDDR5 5 921 #define AMDGPU_VRAM_TYPE_HBM 6 922 #define AMDGPU_VRAM_TYPE_DDR3 7 923 #define AMDGPU_VRAM_TYPE_DDR4 8 924 #define AMDGPU_VRAM_TYPE_GDDR6 9 925 926 struct drm_amdgpu_info_device { 927 /** PCI Device ID */ 928 __u32 device_id; 929 /** Internal chip revision: A0, A1, etc.) */ 930 __u32 chip_rev; 931 __u32 external_rev; 932 /** Revision id in PCI Config space */ 933 __u32 pci_rev; 934 __u32 family; 935 __u32 num_shader_engines; 936 __u32 num_shader_arrays_per_engine; 937 /* in KHz */ 938 __u32 gpu_counter_freq; 939 __u64 max_engine_clock; 940 __u64 max_memory_clock; 941 /* cu information */ 942 __u32 cu_active_number; 943 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 944 __u32 cu_ao_mask; 945 __u32 cu_bitmap[4][4]; 946 /** Render backend pipe mask. One render backend is CB+DB. */ 947 __u32 enabled_rb_pipes_mask; 948 __u32 num_rb_pipes; 949 __u32 num_hw_gfx_contexts; 950 __u32 _pad; 951 __u64 ids_flags; 952 /** Starting virtual address for UMDs. */ 953 __u64 virtual_address_offset; 954 /** The maximum virtual address */ 955 __u64 virtual_address_max; 956 /** Required alignment of virtual addresses. */ 957 __u32 virtual_address_alignment; 958 /** Page table entry - fragment size */ 959 __u32 pte_fragment_size; 960 __u32 gart_page_size; 961 /** constant engine ram size*/ 962 __u32 ce_ram_size; 963 /** video memory type info*/ 964 __u32 vram_type; 965 /** video memory bit width*/ 966 __u32 vram_bit_width; 967 /* vce harvesting instance */ 968 __u32 vce_harvest_config; 969 /* gfx double offchip LDS buffers */ 970 __u32 gc_double_offchip_lds_buf; 971 /* NGG Primitive Buffer */ 972 __u64 prim_buf_gpu_addr; 973 /* NGG Position Buffer */ 974 __u64 pos_buf_gpu_addr; 975 /* NGG Control Sideband */ 976 __u64 cntl_sb_buf_gpu_addr; 977 /* NGG Parameter Cache */ 978 __u64 param_buf_gpu_addr; 979 __u32 prim_buf_size; 980 __u32 pos_buf_size; 981 __u32 cntl_sb_buf_size; 982 __u32 param_buf_size; 983 /* wavefront size*/ 984 __u32 wave_front_size; 985 /* shader visible vgprs*/ 986 __u32 num_shader_visible_vgprs; 987 /* CU per shader array*/ 988 __u32 num_cu_per_sh; 989 /* number of tcc blocks*/ 990 __u32 num_tcc_blocks; 991 /* gs vgt table depth*/ 992 __u32 gs_vgt_table_depth; 993 /* gs primitive buffer depth*/ 994 __u32 gs_prim_buffer_depth; 995 /* max gs wavefront per vgt*/ 996 __u32 max_gs_waves_per_vgt; 997 __u32 _pad1; 998 /* always on cu bitmap */ 999 __u32 cu_ao_bitmap[4][4]; 1000 /** Starting high virtual address for UMDs. */ 1001 __u64 high_va_offset; 1002 /** The maximum high virtual address */ 1003 __u64 high_va_max; 1004 /* gfx10 pa_sc_tile_steering_override */ 1005 __u32 pa_sc_tile_steering_override; 1006 }; 1007 1008 struct drm_amdgpu_info_hw_ip { 1009 /** Version of h/w IP */ 1010 __u32 hw_ip_version_major; 1011 __u32 hw_ip_version_minor; 1012 /** Capabilities */ 1013 __u64 capabilities_flags; 1014 /** command buffer address start alignment*/ 1015 __u32 ib_start_alignment; 1016 /** command buffer size alignment*/ 1017 __u32 ib_size_alignment; 1018 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1019 __u32 available_rings; 1020 __u32 _pad; 1021 }; 1022 1023 struct drm_amdgpu_info_num_handles { 1024 /** Max handles as supported by firmware for UVD */ 1025 __u32 uvd_max_handles; 1026 /** Handles currently in use for UVD */ 1027 __u32 uvd_used_handles; 1028 }; 1029 1030 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1031 1032 struct drm_amdgpu_info_vce_clock_table_entry { 1033 /** System clock */ 1034 __u32 sclk; 1035 /** Memory clock */ 1036 __u32 mclk; 1037 /** VCE clock */ 1038 __u32 eclk; 1039 __u32 pad; 1040 }; 1041 1042 struct drm_amdgpu_info_vce_clock_table { 1043 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1044 __u32 num_valid_entries; 1045 __u32 pad; 1046 }; 1047 1048 /* 1049 * Supported GPU families 1050 */ 1051 #define AMDGPU_FAMILY_UNKNOWN 0 1052 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1053 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1054 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1055 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1056 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1057 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1058 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1059 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1060 1061 #if defined(__cplusplus) 1062 } 1063 #endif 1064 1065 #endif 1066