1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that allocating the BO should use linear VRAM */ 120 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 121 /* Flag that BO is always valid in this VM */ 122 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 123 /* Flag that BO sharing will be explicitly synchronized */ 124 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 125 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 126 * for the second page onward should be set to NC. It should never 127 * be used by user space applications. 128 */ 129 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 130 /* Flag that BO may contain sensitive data that must be wiped before 131 * releasing the memory 132 */ 133 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 134 /* Flag that BO will be encrypted and that the TMZ bit should be 135 * set in the PTEs when mapping this buffer via GPUVM or 136 * accessing it with various hw blocks 137 */ 138 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 139 /* Flag that BO will be used only in preemptible context, which does 140 * not require GTT memory accounting 141 */ 142 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 143 /* Flag that BO can be discarded under memory pressure without keeping the 144 * content. 145 */ 146 #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 147 /* Flag that BO is shared coherently between multiple devices or CPU threads. 148 * May depend on GPU instructions to flush caches explicitly 149 * 150 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 151 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 152 */ 153 #define AMDGPU_GEM_CREATE_COHERENT (1 << 13) 154 /* Flag that BO should not be cached by GPU. Coherent without having to flush 155 * GPU caches explicitly 156 * 157 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and 158 * may override the MTYPE selected in AMDGPU_VA_OP_MAP. 159 */ 160 #define AMDGPU_GEM_CREATE_UNCACHED (1 << 14) 161 162 struct drm_amdgpu_gem_create_in { 163 /** the requested memory size */ 164 __u64 bo_size; 165 /** physical start_addr alignment in bytes for some HW requirements */ 166 __u64 alignment; 167 /** the requested memory domains */ 168 __u64 domains; 169 /** allocation flags */ 170 __u64 domain_flags; 171 }; 172 173 struct drm_amdgpu_gem_create_out { 174 /** returned GEM object handle */ 175 __u32 handle; 176 __u32 _pad; 177 }; 178 179 union drm_amdgpu_gem_create { 180 struct drm_amdgpu_gem_create_in in; 181 struct drm_amdgpu_gem_create_out out; 182 }; 183 184 /** Opcode to create new residency list. */ 185 #define AMDGPU_BO_LIST_OP_CREATE 0 186 /** Opcode to destroy previously created residency list */ 187 #define AMDGPU_BO_LIST_OP_DESTROY 1 188 /** Opcode to update resource information in the list */ 189 #define AMDGPU_BO_LIST_OP_UPDATE 2 190 191 struct drm_amdgpu_bo_list_in { 192 /** Type of operation */ 193 __u32 operation; 194 /** Handle of list or 0 if we want to create one */ 195 __u32 list_handle; 196 /** Number of BOs in list */ 197 __u32 bo_number; 198 /** Size of each element describing BO */ 199 __u32 bo_info_size; 200 /** Pointer to array describing BOs */ 201 __u64 bo_info_ptr; 202 }; 203 204 struct drm_amdgpu_bo_list_entry { 205 /** Handle of BO */ 206 __u32 bo_handle; 207 /** New (if specified) BO priority to be used during migration */ 208 __u32 bo_priority; 209 }; 210 211 struct drm_amdgpu_bo_list_out { 212 /** Handle of resource list */ 213 __u32 list_handle; 214 __u32 _pad; 215 }; 216 217 union drm_amdgpu_bo_list { 218 struct drm_amdgpu_bo_list_in in; 219 struct drm_amdgpu_bo_list_out out; 220 }; 221 222 /* context related */ 223 #define AMDGPU_CTX_OP_ALLOC_CTX 1 224 #define AMDGPU_CTX_OP_FREE_CTX 2 225 #define AMDGPU_CTX_OP_QUERY_STATE 3 226 #define AMDGPU_CTX_OP_QUERY_STATE2 4 227 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 228 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 229 230 /* GPU reset status */ 231 #define AMDGPU_CTX_NO_RESET 0 232 /* this the context caused it */ 233 #define AMDGPU_CTX_GUILTY_RESET 1 234 /* some other context caused it */ 235 #define AMDGPU_CTX_INNOCENT_RESET 2 236 /* unknown cause */ 237 #define AMDGPU_CTX_UNKNOWN_RESET 3 238 239 /* indicate gpu reset occured after ctx created */ 240 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 241 /* indicate vram lost occured after ctx created */ 242 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 243 /* indicate some job from this context once cause gpu hang */ 244 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 245 /* indicate some errors are detected by RAS */ 246 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 247 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 248 249 /* Context priority level */ 250 #define AMDGPU_CTX_PRIORITY_UNSET -2048 251 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 252 #define AMDGPU_CTX_PRIORITY_LOW -512 253 #define AMDGPU_CTX_PRIORITY_NORMAL 0 254 /* 255 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 256 * CAP_SYS_NICE or DRM_MASTER 257 */ 258 #define AMDGPU_CTX_PRIORITY_HIGH 512 259 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 260 261 /* select a stable profiling pstate for perfmon tools */ 262 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 263 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 264 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 265 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 266 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 267 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 268 269 struct drm_amdgpu_ctx_in { 270 /** AMDGPU_CTX_OP_* */ 271 __u32 op; 272 /** Flags */ 273 __u32 flags; 274 __u32 ctx_id; 275 /** AMDGPU_CTX_PRIORITY_* */ 276 __s32 priority; 277 }; 278 279 union drm_amdgpu_ctx_out { 280 struct { 281 __u32 ctx_id; 282 __u32 _pad; 283 } alloc; 284 285 struct { 286 /** For future use, no flags defined so far */ 287 __u64 flags; 288 /** Number of resets caused by this context so far. */ 289 __u32 hangs; 290 /** Reset status since the last call of the ioctl. */ 291 __u32 reset_status; 292 } state; 293 294 struct { 295 __u32 flags; 296 __u32 _pad; 297 } pstate; 298 }; 299 300 union drm_amdgpu_ctx { 301 struct drm_amdgpu_ctx_in in; 302 union drm_amdgpu_ctx_out out; 303 }; 304 305 /* vm ioctl */ 306 #define AMDGPU_VM_OP_RESERVE_VMID 1 307 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 308 309 struct drm_amdgpu_vm_in { 310 /** AMDGPU_VM_OP_* */ 311 __u32 op; 312 __u32 flags; 313 }; 314 315 struct drm_amdgpu_vm_out { 316 /** For future use, no flags defined so far */ 317 __u64 flags; 318 }; 319 320 union drm_amdgpu_vm { 321 struct drm_amdgpu_vm_in in; 322 struct drm_amdgpu_vm_out out; 323 }; 324 325 /* sched ioctl */ 326 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 327 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 328 329 struct drm_amdgpu_sched_in { 330 /* AMDGPU_SCHED_OP_* */ 331 __u32 op; 332 __u32 fd; 333 /** AMDGPU_CTX_PRIORITY_* */ 334 __s32 priority; 335 __u32 ctx_id; 336 }; 337 338 union drm_amdgpu_sched { 339 struct drm_amdgpu_sched_in in; 340 }; 341 342 /* 343 * This is not a reliable API and you should expect it to fail for any 344 * number of reasons and have fallback path that do not use userptr to 345 * perform any operation. 346 */ 347 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 348 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 349 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 350 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 351 352 struct drm_amdgpu_gem_userptr { 353 __u64 addr; 354 __u64 size; 355 /* AMDGPU_GEM_USERPTR_* */ 356 __u32 flags; 357 /* Resulting GEM handle */ 358 __u32 handle; 359 }; 360 361 /* SI-CI-VI: */ 362 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 363 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 364 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 365 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 366 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 367 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 368 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 369 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 370 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 371 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 372 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 373 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 374 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 375 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 376 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 377 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 378 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 379 380 /* GFX9 and later: */ 381 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 382 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 383 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 384 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 385 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 386 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 387 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 388 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 389 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 390 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 391 #define AMDGPU_TILING_SCANOUT_SHIFT 63 392 #define AMDGPU_TILING_SCANOUT_MASK 0x1 393 394 /* Set/Get helpers for tiling flags. */ 395 #define AMDGPU_TILING_SET(field, value) \ 396 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 397 #define AMDGPU_TILING_GET(value, field) \ 398 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 399 400 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 401 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 402 403 /** The same structure is shared for input/output */ 404 struct drm_amdgpu_gem_metadata { 405 /** GEM Object handle */ 406 __u32 handle; 407 /** Do we want get or set metadata */ 408 __u32 op; 409 struct { 410 /** For future use, no flags defined so far */ 411 __u64 flags; 412 /** family specific tiling info */ 413 __u64 tiling_info; 414 __u32 data_size_bytes; 415 __u32 data[64]; 416 } data; 417 }; 418 419 struct drm_amdgpu_gem_mmap_in { 420 /** the GEM object handle */ 421 __u32 handle; 422 __u32 _pad; 423 }; 424 425 struct drm_amdgpu_gem_mmap_out { 426 /** mmap offset from the vma offset manager */ 427 __u64 addr_ptr; 428 }; 429 430 union drm_amdgpu_gem_mmap { 431 struct drm_amdgpu_gem_mmap_in in; 432 struct drm_amdgpu_gem_mmap_out out; 433 }; 434 435 struct drm_amdgpu_gem_wait_idle_in { 436 /** GEM object handle */ 437 __u32 handle; 438 /** For future use, no flags defined so far */ 439 __u32 flags; 440 /** Absolute timeout to wait */ 441 __u64 timeout; 442 }; 443 444 struct drm_amdgpu_gem_wait_idle_out { 445 /** BO status: 0 - BO is idle, 1 - BO is busy */ 446 __u32 status; 447 /** Returned current memory domain */ 448 __u32 domain; 449 }; 450 451 union drm_amdgpu_gem_wait_idle { 452 struct drm_amdgpu_gem_wait_idle_in in; 453 struct drm_amdgpu_gem_wait_idle_out out; 454 }; 455 456 struct drm_amdgpu_wait_cs_in { 457 /* Command submission handle 458 * handle equals 0 means none to wait for 459 * handle equals ~0ull means wait for the latest sequence number 460 */ 461 __u64 handle; 462 /** Absolute timeout to wait */ 463 __u64 timeout; 464 __u32 ip_type; 465 __u32 ip_instance; 466 __u32 ring; 467 __u32 ctx_id; 468 }; 469 470 struct drm_amdgpu_wait_cs_out { 471 /** CS status: 0 - CS completed, 1 - CS still busy */ 472 __u64 status; 473 }; 474 475 union drm_amdgpu_wait_cs { 476 struct drm_amdgpu_wait_cs_in in; 477 struct drm_amdgpu_wait_cs_out out; 478 }; 479 480 struct drm_amdgpu_fence { 481 __u32 ctx_id; 482 __u32 ip_type; 483 __u32 ip_instance; 484 __u32 ring; 485 __u64 seq_no; 486 }; 487 488 struct drm_amdgpu_wait_fences_in { 489 /** This points to uint64_t * which points to fences */ 490 __u64 fences; 491 __u32 fence_count; 492 __u32 wait_all; 493 __u64 timeout_ns; 494 }; 495 496 struct drm_amdgpu_wait_fences_out { 497 __u32 status; 498 __u32 first_signaled; 499 }; 500 501 union drm_amdgpu_wait_fences { 502 struct drm_amdgpu_wait_fences_in in; 503 struct drm_amdgpu_wait_fences_out out; 504 }; 505 506 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 507 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 508 509 /* Sets or returns a value associated with a buffer. */ 510 struct drm_amdgpu_gem_op { 511 /** GEM object handle */ 512 __u32 handle; 513 /** AMDGPU_GEM_OP_* */ 514 __u32 op; 515 /** Input or return value */ 516 __u64 value; 517 }; 518 519 #define AMDGPU_VA_OP_MAP 1 520 #define AMDGPU_VA_OP_UNMAP 2 521 #define AMDGPU_VA_OP_CLEAR 3 522 #define AMDGPU_VA_OP_REPLACE 4 523 524 /* Delay the page table update till the next CS */ 525 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 526 527 /* Mapping flags */ 528 /* readable mapping */ 529 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 530 /* writable mapping */ 531 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 532 /* executable mapping, new for VI */ 533 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 534 /* partially resident texture */ 535 #define AMDGPU_VM_PAGE_PRT (1 << 4) 536 /* MTYPE flags use bit 5 to 8 */ 537 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 538 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 539 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 540 /* Use Non Coherent MTYPE instead of default MTYPE */ 541 #define AMDGPU_VM_MTYPE_NC (1 << 5) 542 /* Use Write Combine MTYPE instead of default MTYPE */ 543 #define AMDGPU_VM_MTYPE_WC (2 << 5) 544 /* Use Cache Coherent MTYPE instead of default MTYPE */ 545 #define AMDGPU_VM_MTYPE_CC (3 << 5) 546 /* Use UnCached MTYPE instead of default MTYPE */ 547 #define AMDGPU_VM_MTYPE_UC (4 << 5) 548 /* Use Read Write MTYPE instead of default MTYPE */ 549 #define AMDGPU_VM_MTYPE_RW (5 << 5) 550 /* don't allocate MALL */ 551 #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 552 553 struct drm_amdgpu_gem_va { 554 /** GEM object handle */ 555 __u32 handle; 556 __u32 _pad; 557 /** AMDGPU_VA_OP_* */ 558 __u32 operation; 559 /** AMDGPU_VM_PAGE_* */ 560 __u32 flags; 561 /** va address to assign . Must be correctly aligned.*/ 562 __u64 va_address; 563 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 564 __u64 offset_in_bo; 565 /** Specify mapping size. Must be correctly aligned. */ 566 __u64 map_size; 567 }; 568 569 #define AMDGPU_HW_IP_GFX 0 570 #define AMDGPU_HW_IP_COMPUTE 1 571 #define AMDGPU_HW_IP_DMA 2 572 #define AMDGPU_HW_IP_UVD 3 573 #define AMDGPU_HW_IP_VCE 4 574 #define AMDGPU_HW_IP_UVD_ENC 5 575 #define AMDGPU_HW_IP_VCN_DEC 6 576 /* 577 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 578 * both encoding and decoding jobs. 579 */ 580 #define AMDGPU_HW_IP_VCN_ENC 7 581 #define AMDGPU_HW_IP_VCN_JPEG 8 582 #define AMDGPU_HW_IP_NUM 9 583 584 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 585 586 #define AMDGPU_CHUNK_ID_IB 0x01 587 #define AMDGPU_CHUNK_ID_FENCE 0x02 588 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 589 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 590 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 591 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 592 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 593 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 594 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 595 596 struct drm_amdgpu_cs_chunk { 597 __u32 chunk_id; 598 __u32 length_dw; 599 __u64 chunk_data; 600 }; 601 602 struct drm_amdgpu_cs_in { 603 /** Rendering context id */ 604 __u32 ctx_id; 605 /** Handle of resource list associated with CS */ 606 __u32 bo_list_handle; 607 __u32 num_chunks; 608 __u32 flags; 609 /** this points to __u64 * which point to cs chunks */ 610 __u64 chunks; 611 }; 612 613 struct drm_amdgpu_cs_out { 614 __u64 handle; 615 }; 616 617 union drm_amdgpu_cs { 618 struct drm_amdgpu_cs_in in; 619 struct drm_amdgpu_cs_out out; 620 }; 621 622 /* Specify flags to be used for IB */ 623 624 /* This IB should be submitted to CE */ 625 #define AMDGPU_IB_FLAG_CE (1<<0) 626 627 /* Preamble flag, which means the IB could be dropped if no context switch */ 628 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 629 630 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 631 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 632 633 /* The IB fence should do the L2 writeback but not invalidate any shader 634 * caches (L2/vL1/sL1/I$). */ 635 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 636 637 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 638 * This will reset wave ID counters for the IB. 639 */ 640 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 641 642 /* Flag the IB as secure (TMZ) 643 */ 644 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 645 646 /* Tell KMD to flush and invalidate caches 647 */ 648 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 649 650 struct drm_amdgpu_cs_chunk_ib { 651 __u32 _pad; 652 /** AMDGPU_IB_FLAG_* */ 653 __u32 flags; 654 /** Virtual address to begin IB execution */ 655 __u64 va_start; 656 /** Size of submission */ 657 __u32 ib_bytes; 658 /** HW IP to submit to */ 659 __u32 ip_type; 660 /** HW IP index of the same type to submit to */ 661 __u32 ip_instance; 662 /** Ring index to submit to */ 663 __u32 ring; 664 }; 665 666 struct drm_amdgpu_cs_chunk_dep { 667 __u32 ip_type; 668 __u32 ip_instance; 669 __u32 ring; 670 __u32 ctx_id; 671 __u64 handle; 672 }; 673 674 struct drm_amdgpu_cs_chunk_fence { 675 __u32 handle; 676 __u32 offset; 677 }; 678 679 struct drm_amdgpu_cs_chunk_sem { 680 __u32 handle; 681 }; 682 683 struct drm_amdgpu_cs_chunk_syncobj { 684 __u32 handle; 685 __u32 flags; 686 __u64 point; 687 }; 688 689 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 690 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 691 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 692 693 union drm_amdgpu_fence_to_handle { 694 struct { 695 struct drm_amdgpu_fence fence; 696 __u32 what; 697 __u32 pad; 698 } in; 699 struct { 700 __u32 handle; 701 } out; 702 }; 703 704 struct drm_amdgpu_cs_chunk_data { 705 union { 706 struct drm_amdgpu_cs_chunk_ib ib_data; 707 struct drm_amdgpu_cs_chunk_fence fence_data; 708 }; 709 }; 710 711 /* 712 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 713 * 714 */ 715 #define AMDGPU_IDS_FLAGS_FUSION 0x1 716 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 717 #define AMDGPU_IDS_FLAGS_TMZ 0x4 718 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 719 720 /* indicate if acceleration can be working */ 721 #define AMDGPU_INFO_ACCEL_WORKING 0x00 722 /* get the crtc_id from the mode object id? */ 723 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 724 /* query hw IP info */ 725 #define AMDGPU_INFO_HW_IP_INFO 0x02 726 /* query hw IP instance count for the specified type */ 727 #define AMDGPU_INFO_HW_IP_COUNT 0x03 728 /* timestamp for GL_ARB_timer_query */ 729 #define AMDGPU_INFO_TIMESTAMP 0x05 730 /* Query the firmware version */ 731 #define AMDGPU_INFO_FW_VERSION 0x0e 732 /* Subquery id: Query VCE firmware version */ 733 #define AMDGPU_INFO_FW_VCE 0x1 734 /* Subquery id: Query UVD firmware version */ 735 #define AMDGPU_INFO_FW_UVD 0x2 736 /* Subquery id: Query GMC firmware version */ 737 #define AMDGPU_INFO_FW_GMC 0x03 738 /* Subquery id: Query GFX ME firmware version */ 739 #define AMDGPU_INFO_FW_GFX_ME 0x04 740 /* Subquery id: Query GFX PFP firmware version */ 741 #define AMDGPU_INFO_FW_GFX_PFP 0x05 742 /* Subquery id: Query GFX CE firmware version */ 743 #define AMDGPU_INFO_FW_GFX_CE 0x06 744 /* Subquery id: Query GFX RLC firmware version */ 745 #define AMDGPU_INFO_FW_GFX_RLC 0x07 746 /* Subquery id: Query GFX MEC firmware version */ 747 #define AMDGPU_INFO_FW_GFX_MEC 0x08 748 /* Subquery id: Query SMC firmware version */ 749 #define AMDGPU_INFO_FW_SMC 0x0a 750 /* Subquery id: Query SDMA firmware version */ 751 #define AMDGPU_INFO_FW_SDMA 0x0b 752 /* Subquery id: Query PSP SOS firmware version */ 753 #define AMDGPU_INFO_FW_SOS 0x0c 754 /* Subquery id: Query PSP ASD firmware version */ 755 #define AMDGPU_INFO_FW_ASD 0x0d 756 /* Subquery id: Query VCN firmware version */ 757 #define AMDGPU_INFO_FW_VCN 0x0e 758 /* Subquery id: Query GFX RLC SRLC firmware version */ 759 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 760 /* Subquery id: Query GFX RLC SRLG firmware version */ 761 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 762 /* Subquery id: Query GFX RLC SRLS firmware version */ 763 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 764 /* Subquery id: Query DMCU firmware version */ 765 #define AMDGPU_INFO_FW_DMCU 0x12 766 #define AMDGPU_INFO_FW_TA 0x13 767 /* Subquery id: Query DMCUB firmware version */ 768 #define AMDGPU_INFO_FW_DMCUB 0x14 769 /* Subquery id: Query TOC firmware version */ 770 #define AMDGPU_INFO_FW_TOC 0x15 771 /* Subquery id: Query CAP firmware version */ 772 #define AMDGPU_INFO_FW_CAP 0x16 773 /* Subquery id: Query GFX RLCP firmware version */ 774 #define AMDGPU_INFO_FW_GFX_RLCP 0x17 775 /* Subquery id: Query GFX RLCV firmware version */ 776 #define AMDGPU_INFO_FW_GFX_RLCV 0x18 777 /* Subquery id: Query MES_KIQ firmware version */ 778 #define AMDGPU_INFO_FW_MES_KIQ 0x19 779 /* Subquery id: Query MES firmware version */ 780 #define AMDGPU_INFO_FW_MES 0x1a 781 /* Subquery id: Query IMU firmware version */ 782 #define AMDGPU_INFO_FW_IMU 0x1b 783 784 /* number of bytes moved for TTM migration */ 785 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 786 /* the used VRAM size */ 787 #define AMDGPU_INFO_VRAM_USAGE 0x10 788 /* the used GTT size */ 789 #define AMDGPU_INFO_GTT_USAGE 0x11 790 /* Information about GDS, etc. resource configuration */ 791 #define AMDGPU_INFO_GDS_CONFIG 0x13 792 /* Query information about VRAM and GTT domains */ 793 #define AMDGPU_INFO_VRAM_GTT 0x14 794 /* Query information about register in MMR address space*/ 795 #define AMDGPU_INFO_READ_MMR_REG 0x15 796 /* Query information about device: rev id, family, etc. */ 797 #define AMDGPU_INFO_DEV_INFO 0x16 798 /* visible vram usage */ 799 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 800 /* number of TTM buffer evictions */ 801 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 802 /* Query memory about VRAM and GTT domains */ 803 #define AMDGPU_INFO_MEMORY 0x19 804 /* Query vce clock table */ 805 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 806 /* Query vbios related information */ 807 #define AMDGPU_INFO_VBIOS 0x1B 808 /* Subquery id: Query vbios size */ 809 #define AMDGPU_INFO_VBIOS_SIZE 0x1 810 /* Subquery id: Query vbios image */ 811 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 812 /* Subquery id: Query vbios info */ 813 #define AMDGPU_INFO_VBIOS_INFO 0x3 814 /* Query UVD handles */ 815 #define AMDGPU_INFO_NUM_HANDLES 0x1C 816 /* Query sensor related information */ 817 #define AMDGPU_INFO_SENSOR 0x1D 818 /* Subquery id: Query GPU shader clock */ 819 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 820 /* Subquery id: Query GPU memory clock */ 821 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 822 /* Subquery id: Query GPU temperature */ 823 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 824 /* Subquery id: Query GPU load */ 825 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 826 /* Subquery id: Query average GPU power */ 827 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 828 /* Subquery id: Query northbridge voltage */ 829 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 830 /* Subquery id: Query graphics voltage */ 831 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 832 /* Subquery id: Query GPU stable pstate shader clock */ 833 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 834 /* Subquery id: Query GPU stable pstate memory clock */ 835 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 836 /* Subquery id: Query GPU peak pstate shader clock */ 837 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa 838 /* Subquery id: Query GPU peak pstate memory clock */ 839 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb 840 /* Number of VRAM page faults on CPU access. */ 841 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 842 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 843 /* query ras mask of enabled features*/ 844 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 845 /* RAS MASK: UMC (VRAM) */ 846 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 847 /* RAS MASK: SDMA */ 848 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 849 /* RAS MASK: GFX */ 850 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 851 /* RAS MASK: MMHUB */ 852 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 853 /* RAS MASK: ATHUB */ 854 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 855 /* RAS MASK: PCIE */ 856 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 857 /* RAS MASK: HDP */ 858 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 859 /* RAS MASK: XGMI */ 860 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 861 /* RAS MASK: DF */ 862 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 863 /* RAS MASK: SMN */ 864 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 865 /* RAS MASK: SEM */ 866 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 867 /* RAS MASK: MP0 */ 868 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 869 /* RAS MASK: MP1 */ 870 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 871 /* RAS MASK: FUSE */ 872 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 873 /* query video encode/decode caps */ 874 #define AMDGPU_INFO_VIDEO_CAPS 0x21 875 /* Subquery id: Decode */ 876 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 877 /* Subquery id: Encode */ 878 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 879 880 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 881 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 882 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 883 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 884 885 struct drm_amdgpu_query_fw { 886 /** AMDGPU_INFO_FW_* */ 887 __u32 fw_type; 888 /** 889 * Index of the IP if there are more IPs of 890 * the same type. 891 */ 892 __u32 ip_instance; 893 /** 894 * Index of the engine. Whether this is used depends 895 * on the firmware type. (e.g. MEC, SDMA) 896 */ 897 __u32 index; 898 __u32 _pad; 899 }; 900 901 /* Input structure for the INFO ioctl */ 902 struct drm_amdgpu_info { 903 /* Where the return value will be stored */ 904 __u64 return_pointer; 905 /* The size of the return value. Just like "size" in "snprintf", 906 * it limits how many bytes the kernel can write. */ 907 __u32 return_size; 908 /* The query request id. */ 909 __u32 query; 910 911 union { 912 struct { 913 __u32 id; 914 __u32 _pad; 915 } mode_crtc; 916 917 struct { 918 /** AMDGPU_HW_IP_* */ 919 __u32 type; 920 /** 921 * Index of the IP if there are more IPs of the same 922 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 923 */ 924 __u32 ip_instance; 925 } query_hw_ip; 926 927 struct { 928 __u32 dword_offset; 929 /** number of registers to read */ 930 __u32 count; 931 __u32 instance; 932 /** For future use, no flags defined so far */ 933 __u32 flags; 934 } read_mmr_reg; 935 936 struct drm_amdgpu_query_fw query_fw; 937 938 struct { 939 __u32 type; 940 __u32 offset; 941 } vbios_info; 942 943 struct { 944 __u32 type; 945 } sensor_info; 946 947 struct { 948 __u32 type; 949 } video_cap; 950 }; 951 }; 952 953 struct drm_amdgpu_info_gds { 954 /** GDS GFX partition size */ 955 __u32 gds_gfx_partition_size; 956 /** GDS compute partition size */ 957 __u32 compute_partition_size; 958 /** total GDS memory size */ 959 __u32 gds_total_size; 960 /** GWS size per GFX partition */ 961 __u32 gws_per_gfx_partition; 962 /** GSW size per compute partition */ 963 __u32 gws_per_compute_partition; 964 /** OA size per GFX partition */ 965 __u32 oa_per_gfx_partition; 966 /** OA size per compute partition */ 967 __u32 oa_per_compute_partition; 968 __u32 _pad; 969 }; 970 971 struct drm_amdgpu_info_vram_gtt { 972 __u64 vram_size; 973 __u64 vram_cpu_accessible_size; 974 __u64 gtt_size; 975 }; 976 977 struct drm_amdgpu_heap_info { 978 /** max. physical memory */ 979 __u64 total_heap_size; 980 981 /** Theoretical max. available memory in the given heap */ 982 __u64 usable_heap_size; 983 984 /** 985 * Number of bytes allocated in the heap. This includes all processes 986 * and private allocations in the kernel. It changes when new buffers 987 * are allocated, freed, and moved. It cannot be larger than 988 * heap_size. 989 */ 990 __u64 heap_usage; 991 992 /** 993 * Theoretical possible max. size of buffer which 994 * could be allocated in the given heap 995 */ 996 __u64 max_allocation; 997 }; 998 999 struct drm_amdgpu_memory_info { 1000 struct drm_amdgpu_heap_info vram; 1001 struct drm_amdgpu_heap_info cpu_accessible_vram; 1002 struct drm_amdgpu_heap_info gtt; 1003 }; 1004 1005 struct drm_amdgpu_info_firmware { 1006 __u32 ver; 1007 __u32 feature; 1008 }; 1009 1010 struct drm_amdgpu_info_vbios { 1011 __u8 name[64]; 1012 __u8 vbios_pn[64]; 1013 __u32 version; 1014 __u32 pad; 1015 __u8 vbios_ver_str[32]; 1016 __u8 date[32]; 1017 }; 1018 1019 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 1020 #define AMDGPU_VRAM_TYPE_GDDR1 1 1021 #define AMDGPU_VRAM_TYPE_DDR2 2 1022 #define AMDGPU_VRAM_TYPE_GDDR3 3 1023 #define AMDGPU_VRAM_TYPE_GDDR4 4 1024 #define AMDGPU_VRAM_TYPE_GDDR5 5 1025 #define AMDGPU_VRAM_TYPE_HBM 6 1026 #define AMDGPU_VRAM_TYPE_DDR3 7 1027 #define AMDGPU_VRAM_TYPE_DDR4 8 1028 #define AMDGPU_VRAM_TYPE_GDDR6 9 1029 #define AMDGPU_VRAM_TYPE_DDR5 10 1030 #define AMDGPU_VRAM_TYPE_LPDDR4 11 1031 #define AMDGPU_VRAM_TYPE_LPDDR5 12 1032 1033 struct drm_amdgpu_info_device { 1034 /** PCI Device ID */ 1035 __u32 device_id; 1036 /** Internal chip revision: A0, A1, etc.) */ 1037 __u32 chip_rev; 1038 __u32 external_rev; 1039 /** Revision id in PCI Config space */ 1040 __u32 pci_rev; 1041 __u32 family; 1042 __u32 num_shader_engines; 1043 __u32 num_shader_arrays_per_engine; 1044 /* in KHz */ 1045 __u32 gpu_counter_freq; 1046 __u64 max_engine_clock; 1047 __u64 max_memory_clock; 1048 /* cu information */ 1049 __u32 cu_active_number; 1050 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1051 __u32 cu_ao_mask; 1052 __u32 cu_bitmap[4][4]; 1053 /** Render backend pipe mask. One render backend is CB+DB. */ 1054 __u32 enabled_rb_pipes_mask; 1055 __u32 num_rb_pipes; 1056 __u32 num_hw_gfx_contexts; 1057 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */ 1058 __u32 pcie_gen; 1059 __u64 ids_flags; 1060 /** Starting virtual address for UMDs. */ 1061 __u64 virtual_address_offset; 1062 /** The maximum virtual address */ 1063 __u64 virtual_address_max; 1064 /** Required alignment of virtual addresses. */ 1065 __u32 virtual_address_alignment; 1066 /** Page table entry - fragment size */ 1067 __u32 pte_fragment_size; 1068 __u32 gart_page_size; 1069 /** constant engine ram size*/ 1070 __u32 ce_ram_size; 1071 /** video memory type info*/ 1072 __u32 vram_type; 1073 /** video memory bit width*/ 1074 __u32 vram_bit_width; 1075 /* vce harvesting instance */ 1076 __u32 vce_harvest_config; 1077 /* gfx double offchip LDS buffers */ 1078 __u32 gc_double_offchip_lds_buf; 1079 /* NGG Primitive Buffer */ 1080 __u64 prim_buf_gpu_addr; 1081 /* NGG Position Buffer */ 1082 __u64 pos_buf_gpu_addr; 1083 /* NGG Control Sideband */ 1084 __u64 cntl_sb_buf_gpu_addr; 1085 /* NGG Parameter Cache */ 1086 __u64 param_buf_gpu_addr; 1087 __u32 prim_buf_size; 1088 __u32 pos_buf_size; 1089 __u32 cntl_sb_buf_size; 1090 __u32 param_buf_size; 1091 /* wavefront size*/ 1092 __u32 wave_front_size; 1093 /* shader visible vgprs*/ 1094 __u32 num_shader_visible_vgprs; 1095 /* CU per shader array*/ 1096 __u32 num_cu_per_sh; 1097 /* number of tcc blocks*/ 1098 __u32 num_tcc_blocks; 1099 /* gs vgt table depth*/ 1100 __u32 gs_vgt_table_depth; 1101 /* gs primitive buffer depth*/ 1102 __u32 gs_prim_buffer_depth; 1103 /* max gs wavefront per vgt*/ 1104 __u32 max_gs_waves_per_vgt; 1105 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */ 1106 __u32 pcie_num_lanes; 1107 /* always on cu bitmap */ 1108 __u32 cu_ao_bitmap[4][4]; 1109 /** Starting high virtual address for UMDs. */ 1110 __u64 high_va_offset; 1111 /** The maximum high virtual address */ 1112 __u64 high_va_max; 1113 /* gfx10 pa_sc_tile_steering_override */ 1114 __u32 pa_sc_tile_steering_override; 1115 /* disabled TCCs */ 1116 __u64 tcc_disabled_mask; 1117 __u64 min_engine_clock; 1118 __u64 min_memory_clock; 1119 /* The following fields are only set on gfx11+, older chips set 0. */ 1120 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ 1121 __u32 num_sqc_per_wgp; 1122 __u32 sqc_data_cache_size; /* AKA SMEM cache */ 1123 __u32 sqc_inst_cache_size; 1124 __u32 gl1c_cache_size; 1125 __u32 gl2c_cache_size; 1126 __u64 mall_size; /* AKA infinity cache */ 1127 /* high 32 bits of the rb pipes mask */ 1128 __u32 enabled_rb_pipes_mask_hi; 1129 }; 1130 1131 struct drm_amdgpu_info_hw_ip { 1132 /** Version of h/w IP */ 1133 __u32 hw_ip_version_major; 1134 __u32 hw_ip_version_minor; 1135 /** Capabilities */ 1136 __u64 capabilities_flags; 1137 /** command buffer address start alignment*/ 1138 __u32 ib_start_alignment; 1139 /** command buffer size alignment*/ 1140 __u32 ib_size_alignment; 1141 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1142 __u32 available_rings; 1143 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */ 1144 __u32 ip_discovery_version; 1145 }; 1146 1147 struct drm_amdgpu_info_num_handles { 1148 /** Max handles as supported by firmware for UVD */ 1149 __u32 uvd_max_handles; 1150 /** Handles currently in use for UVD */ 1151 __u32 uvd_used_handles; 1152 }; 1153 1154 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1155 1156 struct drm_amdgpu_info_vce_clock_table_entry { 1157 /** System clock */ 1158 __u32 sclk; 1159 /** Memory clock */ 1160 __u32 mclk; 1161 /** VCE clock */ 1162 __u32 eclk; 1163 __u32 pad; 1164 }; 1165 1166 struct drm_amdgpu_info_vce_clock_table { 1167 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1168 __u32 num_valid_entries; 1169 __u32 pad; 1170 }; 1171 1172 /* query video encode/decode caps */ 1173 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1174 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1175 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1176 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1177 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1178 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1179 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1180 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1181 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1182 1183 struct drm_amdgpu_info_video_codec_info { 1184 __u32 valid; 1185 __u32 max_width; 1186 __u32 max_height; 1187 __u32 max_pixels_per_frame; 1188 __u32 max_level; 1189 __u32 pad; 1190 }; 1191 1192 struct drm_amdgpu_info_video_caps { 1193 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1194 }; 1195 1196 /* 1197 * Supported GPU families 1198 */ 1199 #define AMDGPU_FAMILY_UNKNOWN 0 1200 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1201 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1202 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1203 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1204 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1205 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1206 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1207 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1208 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1209 #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 1210 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1211 #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1212 #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1213 #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 1214 1215 #if defined(__cplusplus) 1216 } 1217 #endif 1218 1219 #endif 1220