181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 5481629cbaSAlex Deucher 5581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5681629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 5781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6334b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6681629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 67eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 6881629cbaSAlex Deucher 6981629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 7081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 7181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 7281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 7381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 7481629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 7581629cbaSAlex Deucher 7681629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 7781629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 7881629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 7981629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 8081629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 8188671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 824fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 834fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 84e7893c4bSChunming Zhou /* Flag that create shadow bo(GTT) while allocating vram bo */ 85e7893c4bSChunming Zhou #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 8603f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 8703f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 8881629cbaSAlex Deucher 8981629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 9081629cbaSAlex Deucher /** the requested memory size */ 912ce9dde0SMikko Rapeli __u64 bo_size; 9281629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 932ce9dde0SMikko Rapeli __u64 alignment; 9481629cbaSAlex Deucher /** the requested memory domains */ 952ce9dde0SMikko Rapeli __u64 domains; 9681629cbaSAlex Deucher /** allocation flags */ 972ce9dde0SMikko Rapeli __u64 domain_flags; 9881629cbaSAlex Deucher }; 9981629cbaSAlex Deucher 10081629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 10181629cbaSAlex Deucher /** returned GEM object handle */ 1022ce9dde0SMikko Rapeli __u32 handle; 1032ce9dde0SMikko Rapeli __u32 _pad; 10481629cbaSAlex Deucher }; 10581629cbaSAlex Deucher 10681629cbaSAlex Deucher union drm_amdgpu_gem_create { 10781629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 10881629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 10981629cbaSAlex Deucher }; 11081629cbaSAlex Deucher 11181629cbaSAlex Deucher /** Opcode to create new residency list. */ 11281629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 11381629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 11481629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 11581629cbaSAlex Deucher /** Opcode to update resource information in the list */ 11681629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 11781629cbaSAlex Deucher 11881629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 11981629cbaSAlex Deucher /** Type of operation */ 1202ce9dde0SMikko Rapeli __u32 operation; 12181629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 1222ce9dde0SMikko Rapeli __u32 list_handle; 12381629cbaSAlex Deucher /** Number of BOs in list */ 1242ce9dde0SMikko Rapeli __u32 bo_number; 12581629cbaSAlex Deucher /** Size of each element describing BO */ 1262ce9dde0SMikko Rapeli __u32 bo_info_size; 12781629cbaSAlex Deucher /** Pointer to array describing BOs */ 1282ce9dde0SMikko Rapeli __u64 bo_info_ptr; 12981629cbaSAlex Deucher }; 13081629cbaSAlex Deucher 13181629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 13281629cbaSAlex Deucher /** Handle of BO */ 1332ce9dde0SMikko Rapeli __u32 bo_handle; 13481629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 1352ce9dde0SMikko Rapeli __u32 bo_priority; 13681629cbaSAlex Deucher }; 13781629cbaSAlex Deucher 13881629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 13981629cbaSAlex Deucher /** Handle of resource list */ 1402ce9dde0SMikko Rapeli __u32 list_handle; 1412ce9dde0SMikko Rapeli __u32 _pad; 14281629cbaSAlex Deucher }; 14381629cbaSAlex Deucher 14481629cbaSAlex Deucher union drm_amdgpu_bo_list { 14581629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 14681629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 14781629cbaSAlex Deucher }; 14881629cbaSAlex Deucher 14981629cbaSAlex Deucher /* context related */ 15081629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 15181629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 15281629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 15381629cbaSAlex Deucher 154d94aed5aSMarek Olšák /* GPU reset status */ 155d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 156675da0ddSChristian König /* this the context caused it */ 157675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 158675da0ddSChristian König /* some other context caused it */ 159675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 160675da0ddSChristian König /* unknown cause */ 161675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 162d94aed5aSMarek Olšák 16381629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 164675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 1652ce9dde0SMikko Rapeli __u32 op; 166675da0ddSChristian König /** For future use, no flags defined so far */ 1672ce9dde0SMikko Rapeli __u32 flags; 1682ce9dde0SMikko Rapeli __u32 ctx_id; 1692ce9dde0SMikko Rapeli __u32 _pad; 17081629cbaSAlex Deucher }; 17181629cbaSAlex Deucher 17281629cbaSAlex Deucher union drm_amdgpu_ctx_out { 17381629cbaSAlex Deucher struct { 1742ce9dde0SMikko Rapeli __u32 ctx_id; 1752ce9dde0SMikko Rapeli __u32 _pad; 17681629cbaSAlex Deucher } alloc; 17781629cbaSAlex Deucher 17881629cbaSAlex Deucher struct { 179675da0ddSChristian König /** For future use, no flags defined so far */ 1802ce9dde0SMikko Rapeli __u64 flags; 181d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 1822ce9dde0SMikko Rapeli __u32 hangs; 183d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 1842ce9dde0SMikko Rapeli __u32 reset_status; 18581629cbaSAlex Deucher } state; 18681629cbaSAlex Deucher }; 18781629cbaSAlex Deucher 18881629cbaSAlex Deucher union drm_amdgpu_ctx { 18981629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 19081629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 19181629cbaSAlex Deucher }; 19281629cbaSAlex Deucher 19381629cbaSAlex Deucher /* 19481629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 19581629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 19681629cbaSAlex Deucher * perform any operation. 19781629cbaSAlex Deucher */ 19881629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 19981629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 20081629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 20181629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 20281629cbaSAlex Deucher 20381629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 2042ce9dde0SMikko Rapeli __u64 addr; 2052ce9dde0SMikko Rapeli __u64 size; 206675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 2072ce9dde0SMikko Rapeli __u32 flags; 208675da0ddSChristian König /* Resulting GEM handle */ 2092ce9dde0SMikko Rapeli __u32 handle; 21081629cbaSAlex Deucher }; 21181629cbaSAlex Deucher 21200ac6f6bSAlex Deucher /* SI-CI-VI: */ 213fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 214fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 215fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 216fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 217fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 218fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 219fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 220fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 221fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 222fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 223fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 224fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 225fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 226fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 227fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 228fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 229fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 230fbd76d59SMarek Olšák 23100ac6f6bSAlex Deucher /* GFX9 and later: */ 23200ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 23300ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 23400ac6f6bSAlex Deucher 23500ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 236fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 23700ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 238fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 23900ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 24081629cbaSAlex Deucher 24181629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 24281629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 24381629cbaSAlex Deucher 24481629cbaSAlex Deucher /** The same structure is shared for input/output */ 24581629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 246675da0ddSChristian König /** GEM Object handle */ 2472ce9dde0SMikko Rapeli __u32 handle; 248675da0ddSChristian König /** Do we want get or set metadata */ 2492ce9dde0SMikko Rapeli __u32 op; 25081629cbaSAlex Deucher struct { 251675da0ddSChristian König /** For future use, no flags defined so far */ 2522ce9dde0SMikko Rapeli __u64 flags; 253675da0ddSChristian König /** family specific tiling info */ 2542ce9dde0SMikko Rapeli __u64 tiling_info; 2552ce9dde0SMikko Rapeli __u32 data_size_bytes; 2562ce9dde0SMikko Rapeli __u32 data[64]; 25781629cbaSAlex Deucher } data; 25881629cbaSAlex Deucher }; 25981629cbaSAlex Deucher 26081629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 261675da0ddSChristian König /** the GEM object handle */ 2622ce9dde0SMikko Rapeli __u32 handle; 2632ce9dde0SMikko Rapeli __u32 _pad; 26481629cbaSAlex Deucher }; 26581629cbaSAlex Deucher 26681629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 267675da0ddSChristian König /** mmap offset from the vma offset manager */ 2682ce9dde0SMikko Rapeli __u64 addr_ptr; 26981629cbaSAlex Deucher }; 27081629cbaSAlex Deucher 27181629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 27281629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 27381629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 27481629cbaSAlex Deucher }; 27581629cbaSAlex Deucher 27681629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 277675da0ddSChristian König /** GEM object handle */ 2782ce9dde0SMikko Rapeli __u32 handle; 279675da0ddSChristian König /** For future use, no flags defined so far */ 2802ce9dde0SMikko Rapeli __u32 flags; 281675da0ddSChristian König /** Absolute timeout to wait */ 2822ce9dde0SMikko Rapeli __u64 timeout; 28381629cbaSAlex Deucher }; 28481629cbaSAlex Deucher 28581629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 286675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 2872ce9dde0SMikko Rapeli __u32 status; 288675da0ddSChristian König /** Returned current memory domain */ 2892ce9dde0SMikko Rapeli __u32 domain; 29081629cbaSAlex Deucher }; 29181629cbaSAlex Deucher 29281629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 29381629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 29481629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 29581629cbaSAlex Deucher }; 29681629cbaSAlex Deucher 29781629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 298675da0ddSChristian König /** Command submission handle */ 2992ce9dde0SMikko Rapeli __u64 handle; 300675da0ddSChristian König /** Absolute timeout to wait */ 3012ce9dde0SMikko Rapeli __u64 timeout; 3022ce9dde0SMikko Rapeli __u32 ip_type; 3032ce9dde0SMikko Rapeli __u32 ip_instance; 3042ce9dde0SMikko Rapeli __u32 ring; 3052ce9dde0SMikko Rapeli __u32 ctx_id; 30681629cbaSAlex Deucher }; 30781629cbaSAlex Deucher 30881629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 309675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 3102ce9dde0SMikko Rapeli __u64 status; 31181629cbaSAlex Deucher }; 31281629cbaSAlex Deucher 31381629cbaSAlex Deucher union drm_amdgpu_wait_cs { 31481629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 31581629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 31681629cbaSAlex Deucher }; 31781629cbaSAlex Deucher 318eef18a82SJunwei Zhang struct drm_amdgpu_fence { 319eef18a82SJunwei Zhang __u32 ctx_id; 320eef18a82SJunwei Zhang __u32 ip_type; 321eef18a82SJunwei Zhang __u32 ip_instance; 322eef18a82SJunwei Zhang __u32 ring; 323eef18a82SJunwei Zhang __u64 seq_no; 324eef18a82SJunwei Zhang }; 325eef18a82SJunwei Zhang 326eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 327eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 328eef18a82SJunwei Zhang __u64 fences; 329eef18a82SJunwei Zhang __u32 fence_count; 330eef18a82SJunwei Zhang __u32 wait_all; 331eef18a82SJunwei Zhang __u64 timeout_ns; 332eef18a82SJunwei Zhang }; 333eef18a82SJunwei Zhang 334eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 335eef18a82SJunwei Zhang __u32 status; 336eef18a82SJunwei Zhang __u32 first_signaled; 337eef18a82SJunwei Zhang }; 338eef18a82SJunwei Zhang 339eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 340eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 341eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 342eef18a82SJunwei Zhang }; 343eef18a82SJunwei Zhang 34481629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 345d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 34681629cbaSAlex Deucher 347675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 348675da0ddSChristian König struct drm_amdgpu_gem_op { 349675da0ddSChristian König /** GEM object handle */ 3502ce9dde0SMikko Rapeli __u32 handle; 351675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 3522ce9dde0SMikko Rapeli __u32 op; 353675da0ddSChristian König /** Input or return value */ 3542ce9dde0SMikko Rapeli __u64 value; 355675da0ddSChristian König }; 356675da0ddSChristian König 35781629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 35881629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 359dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 36080f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 36181629cbaSAlex Deucher 362fc220f65SChristian König /* Delay the page table update till the next CS */ 363fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 364fc220f65SChristian König 36581629cbaSAlex Deucher /* Mapping flags */ 36681629cbaSAlex Deucher /* readable mapping */ 36781629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 36881629cbaSAlex Deucher /* writable mapping */ 36981629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 37081629cbaSAlex Deucher /* executable mapping, new for VI */ 37181629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 372b85891bdSJunwei Zhang /* partially resident texture */ 373b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 37466e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 37566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 37666e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 37766e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 37866e02bc3SAlex Xie /* Use NC MTYPE instead of default MTYPE */ 37966e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 38066e02bc3SAlex Xie /* Use WC MTYPE instead of default MTYPE */ 38166e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 38266e02bc3SAlex Xie /* Use CC MTYPE instead of default MTYPE */ 38366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 38466e02bc3SAlex Xie /* Use UC MTYPE instead of default MTYPE */ 38566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 38681629cbaSAlex Deucher 38734b5f6a6SChristian König struct drm_amdgpu_gem_va { 388675da0ddSChristian König /** GEM object handle */ 3892ce9dde0SMikko Rapeli __u32 handle; 3902ce9dde0SMikko Rapeli __u32 _pad; 391675da0ddSChristian König /** AMDGPU_VA_OP_* */ 3922ce9dde0SMikko Rapeli __u32 operation; 393675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 3942ce9dde0SMikko Rapeli __u32 flags; 395675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 3962ce9dde0SMikko Rapeli __u64 va_address; 397675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 3982ce9dde0SMikko Rapeli __u64 offset_in_bo; 399675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 4002ce9dde0SMikko Rapeli __u64 map_size; 40181629cbaSAlex Deucher }; 40281629cbaSAlex Deucher 40381629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 40481629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 40581629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 40681629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 40781629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 408a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 409a50798b6SLeo Liu #define AMDGPU_HW_IP_NUM 6 41081629cbaSAlex Deucher 41181629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 41281629cbaSAlex Deucher 41381629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 41481629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 4152b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 416675da0ddSChristian König 41781629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 4182ce9dde0SMikko Rapeli __u32 chunk_id; 4192ce9dde0SMikko Rapeli __u32 length_dw; 4202ce9dde0SMikko Rapeli __u64 chunk_data; 42181629cbaSAlex Deucher }; 42281629cbaSAlex Deucher 42381629cbaSAlex Deucher struct drm_amdgpu_cs_in { 42481629cbaSAlex Deucher /** Rendering context id */ 4252ce9dde0SMikko Rapeli __u32 ctx_id; 42681629cbaSAlex Deucher /** Handle of resource list associated with CS */ 4272ce9dde0SMikko Rapeli __u32 bo_list_handle; 4282ce9dde0SMikko Rapeli __u32 num_chunks; 4292ce9dde0SMikko Rapeli __u32 _pad; 4302ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 4312ce9dde0SMikko Rapeli __u64 chunks; 43281629cbaSAlex Deucher }; 43381629cbaSAlex Deucher 43481629cbaSAlex Deucher struct drm_amdgpu_cs_out { 4352ce9dde0SMikko Rapeli __u64 handle; 43681629cbaSAlex Deucher }; 43781629cbaSAlex Deucher 43881629cbaSAlex Deucher union drm_amdgpu_cs { 43981629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 44081629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 44181629cbaSAlex Deucher }; 44281629cbaSAlex Deucher 44381629cbaSAlex Deucher /* Specify flags to be used for IB */ 44481629cbaSAlex Deucher 44581629cbaSAlex Deucher /* This IB should be submitted to CE */ 44681629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 44781629cbaSAlex Deucher 448ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 449cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 450aa2bdb24SJammy Zhou 45181629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 4522ce9dde0SMikko Rapeli __u32 _pad; 453675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 4542ce9dde0SMikko Rapeli __u32 flags; 455675da0ddSChristian König /** Virtual address to begin IB execution */ 4562ce9dde0SMikko Rapeli __u64 va_start; 457675da0ddSChristian König /** Size of submission */ 4582ce9dde0SMikko Rapeli __u32 ib_bytes; 459675da0ddSChristian König /** HW IP to submit to */ 4602ce9dde0SMikko Rapeli __u32 ip_type; 461675da0ddSChristian König /** HW IP index of the same type to submit to */ 4622ce9dde0SMikko Rapeli __u32 ip_instance; 463675da0ddSChristian König /** Ring index to submit to */ 4642ce9dde0SMikko Rapeli __u32 ring; 46581629cbaSAlex Deucher }; 46681629cbaSAlex Deucher 4672b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 4682ce9dde0SMikko Rapeli __u32 ip_type; 4692ce9dde0SMikko Rapeli __u32 ip_instance; 4702ce9dde0SMikko Rapeli __u32 ring; 4712ce9dde0SMikko Rapeli __u32 ctx_id; 4722ce9dde0SMikko Rapeli __u64 handle; 4732b48d323SChristian König }; 4742b48d323SChristian König 47581629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 4762ce9dde0SMikko Rapeli __u32 handle; 4772ce9dde0SMikko Rapeli __u32 offset; 47881629cbaSAlex Deucher }; 47981629cbaSAlex Deucher 48081629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 48181629cbaSAlex Deucher union { 48281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 48381629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 48481629cbaSAlex Deucher }; 48581629cbaSAlex Deucher }; 48681629cbaSAlex Deucher 48781629cbaSAlex Deucher /** 48881629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 48981629cbaSAlex Deucher * 49081629cbaSAlex Deucher */ 49181629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 492aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 49381629cbaSAlex Deucher 49481629cbaSAlex Deucher /* indicate if acceleration can be working */ 49581629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 49681629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 49781629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 49881629cbaSAlex Deucher /* query hw IP info */ 49981629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 50081629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 50181629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 50281629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 50381629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 50481629cbaSAlex Deucher /* Query the firmware version */ 50581629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 50681629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 50781629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 50881629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 50981629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 51081629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 51181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 51281629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 51381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 51481629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 51581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 51681629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 51781629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 51881629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 51981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 52081629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 52181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 52281629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 52381629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 52481629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 52581629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 5266a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 5276a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 5286a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 5296a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 53081629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 53181629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 53281629cbaSAlex Deucher /* the used VRAM size */ 53381629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 53481629cbaSAlex Deucher /* the used GTT size */ 53581629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 53681629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 53781629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 53881629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 53981629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 54081629cbaSAlex Deucher /* Query information about register in MMR address space*/ 54181629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 54281629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 54381629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 54481629cbaSAlex Deucher /* visible vram usage */ 54581629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 54683a59b63SMarek Olšák /* number of TTM buffer evictions */ 54783a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 548e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 549e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 550bbe87974SAlex Deucher /* Query vce clock table */ 551bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 55240ee5888SEvan Quan /* Query vbios related information */ 55340ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 55440ee5888SEvan Quan /* Subquery id: Query vbios size */ 55540ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 55640ee5888SEvan Quan /* Subquery id: Query vbios image */ 55740ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 55844879b62SArindam Nath /* Query UVD handles */ 55944879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 5605ebbac4bSAlex Deucher /* Query sensor related information */ 5615ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 5625ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 5635ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 5645ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 5655ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 5665ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 5675ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 5685ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 5695ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 5705ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 5715ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 5725ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 5735ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 5745ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 5755ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 57681629cbaSAlex Deucher 57781629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 57881629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 57981629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 58081629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 58181629cbaSAlex Deucher 582000cab9aSHuang Rui struct drm_amdgpu_query_fw { 583000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 584000cab9aSHuang Rui __u32 fw_type; 585000cab9aSHuang Rui /** 586000cab9aSHuang Rui * Index of the IP if there are more IPs of 587000cab9aSHuang Rui * the same type. 588000cab9aSHuang Rui */ 589000cab9aSHuang Rui __u32 ip_instance; 590000cab9aSHuang Rui /** 591000cab9aSHuang Rui * Index of the engine. Whether this is used depends 592000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 593000cab9aSHuang Rui */ 594000cab9aSHuang Rui __u32 index; 595000cab9aSHuang Rui __u32 _pad; 596000cab9aSHuang Rui }; 597000cab9aSHuang Rui 59881629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 59981629cbaSAlex Deucher struct drm_amdgpu_info { 60081629cbaSAlex Deucher /* Where the return value will be stored */ 6012ce9dde0SMikko Rapeli __u64 return_pointer; 60281629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 60381629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 6042ce9dde0SMikko Rapeli __u32 return_size; 60581629cbaSAlex Deucher /* The query request id. */ 6062ce9dde0SMikko Rapeli __u32 query; 60781629cbaSAlex Deucher 60881629cbaSAlex Deucher union { 60981629cbaSAlex Deucher struct { 6102ce9dde0SMikko Rapeli __u32 id; 6112ce9dde0SMikko Rapeli __u32 _pad; 61281629cbaSAlex Deucher } mode_crtc; 61381629cbaSAlex Deucher 61481629cbaSAlex Deucher struct { 61581629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 6162ce9dde0SMikko Rapeli __u32 type; 61781629cbaSAlex Deucher /** 618675da0ddSChristian König * Index of the IP if there are more IPs of the same 619675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 62081629cbaSAlex Deucher */ 6212ce9dde0SMikko Rapeli __u32 ip_instance; 62281629cbaSAlex Deucher } query_hw_ip; 62381629cbaSAlex Deucher 62481629cbaSAlex Deucher struct { 6252ce9dde0SMikko Rapeli __u32 dword_offset; 626675da0ddSChristian König /** number of registers to read */ 6272ce9dde0SMikko Rapeli __u32 count; 6282ce9dde0SMikko Rapeli __u32 instance; 629675da0ddSChristian König /** For future use, no flags defined so far */ 6302ce9dde0SMikko Rapeli __u32 flags; 63181629cbaSAlex Deucher } read_mmr_reg; 63281629cbaSAlex Deucher 633000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 63440ee5888SEvan Quan 63540ee5888SEvan Quan struct { 63640ee5888SEvan Quan __u32 type; 63740ee5888SEvan Quan __u32 offset; 63840ee5888SEvan Quan } vbios_info; 6395ebbac4bSAlex Deucher 6405ebbac4bSAlex Deucher struct { 6415ebbac4bSAlex Deucher __u32 type; 6425ebbac4bSAlex Deucher } sensor_info; 64381629cbaSAlex Deucher }; 64481629cbaSAlex Deucher }; 64581629cbaSAlex Deucher 64681629cbaSAlex Deucher struct drm_amdgpu_info_gds { 64781629cbaSAlex Deucher /** GDS GFX partition size */ 6482ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 64981629cbaSAlex Deucher /** GDS compute partition size */ 6502ce9dde0SMikko Rapeli __u32 compute_partition_size; 65181629cbaSAlex Deucher /** total GDS memory size */ 6522ce9dde0SMikko Rapeli __u32 gds_total_size; 65381629cbaSAlex Deucher /** GWS size per GFX partition */ 6542ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 65581629cbaSAlex Deucher /** GSW size per compute partition */ 6562ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 65781629cbaSAlex Deucher /** OA size per GFX partition */ 6582ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 65981629cbaSAlex Deucher /** OA size per compute partition */ 6602ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 6612ce9dde0SMikko Rapeli __u32 _pad; 66281629cbaSAlex Deucher }; 66381629cbaSAlex Deucher 66481629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 6652ce9dde0SMikko Rapeli __u64 vram_size; 6662ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 6672ce9dde0SMikko Rapeli __u64 gtt_size; 66881629cbaSAlex Deucher }; 66981629cbaSAlex Deucher 670e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 671e0adf6c8SJunwei Zhang /** max. physical memory */ 672e0adf6c8SJunwei Zhang __u64 total_heap_size; 673e0adf6c8SJunwei Zhang 674e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 675e0adf6c8SJunwei Zhang __u64 usable_heap_size; 676e0adf6c8SJunwei Zhang 677e0adf6c8SJunwei Zhang /** 678e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 679e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 680e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 681e0adf6c8SJunwei Zhang * heap_size. 682e0adf6c8SJunwei Zhang */ 683e0adf6c8SJunwei Zhang __u64 heap_usage; 684e0adf6c8SJunwei Zhang 685e0adf6c8SJunwei Zhang /** 686e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 687e0adf6c8SJunwei Zhang * could be allocated in the given heap 688e0adf6c8SJunwei Zhang */ 689e0adf6c8SJunwei Zhang __u64 max_allocation; 6909f6163e7SJunwei Zhang }; 6919f6163e7SJunwei Zhang 692e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 693e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 694e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 695e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 696cfa32556SJunwei Zhang }; 697cfa32556SJunwei Zhang 69881629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 6992ce9dde0SMikko Rapeli __u32 ver; 7002ce9dde0SMikko Rapeli __u32 feature; 70181629cbaSAlex Deucher }; 70281629cbaSAlex Deucher 70381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 70481c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 70581c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 70681c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 70781c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 70881c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 70981c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 71081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 71181c59f54SKen Wang 71281629cbaSAlex Deucher struct drm_amdgpu_info_device { 71381629cbaSAlex Deucher /** PCI Device ID */ 7142ce9dde0SMikko Rapeli __u32 device_id; 71581629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 7162ce9dde0SMikko Rapeli __u32 chip_rev; 7172ce9dde0SMikko Rapeli __u32 external_rev; 71881629cbaSAlex Deucher /** Revision id in PCI Config space */ 7192ce9dde0SMikko Rapeli __u32 pci_rev; 7202ce9dde0SMikko Rapeli __u32 family; 7212ce9dde0SMikko Rapeli __u32 num_shader_engines; 7222ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 723675da0ddSChristian König /* in KHz */ 7242ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 7252ce9dde0SMikko Rapeli __u64 max_engine_clock; 7262ce9dde0SMikko Rapeli __u64 max_memory_clock; 72781629cbaSAlex Deucher /* cu information */ 7282ce9dde0SMikko Rapeli __u32 cu_active_number; 7292ce9dde0SMikko Rapeli __u32 cu_ao_mask; 7302ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 73181629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 7322ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 7332ce9dde0SMikko Rapeli __u32 num_rb_pipes; 7342ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 7352ce9dde0SMikko Rapeli __u32 _pad; 7362ce9dde0SMikko Rapeli __u64 ids_flags; 73781629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 7382ce9dde0SMikko Rapeli __u64 virtual_address_offset; 73902b70c8cSJammy Zhou /** The maximum virtual address */ 7402ce9dde0SMikko Rapeli __u64 virtual_address_max; 74181629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 7422ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 74381629cbaSAlex Deucher /** Page table entry - fragment size */ 7442ce9dde0SMikko Rapeli __u32 pte_fragment_size; 7452ce9dde0SMikko Rapeli __u32 gart_page_size; 746a101a899SKen Wang /** constant engine ram size*/ 7472ce9dde0SMikko Rapeli __u32 ce_ram_size; 748cab6d57cSJammy Zhou /** video memory type info*/ 7492ce9dde0SMikko Rapeli __u32 vram_type; 75081c59f54SKen Wang /** video memory bit width*/ 7512ce9dde0SMikko Rapeli __u32 vram_bit_width; 752fa92754eSLeo Liu /* vce harvesting instance */ 7532ce9dde0SMikko Rapeli __u32 vce_harvest_config; 754df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 755df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 756bce23e00SAlex Deucher /* NGG Primitive Buffer */ 757bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 758bce23e00SAlex Deucher /* NGG Position Buffer */ 759bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 760bce23e00SAlex Deucher /* NGG Control Sideband */ 761bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 762bce23e00SAlex Deucher /* NGG Parameter Cache */ 763bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 76481629cbaSAlex Deucher }; 76581629cbaSAlex Deucher 76681629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 76781629cbaSAlex Deucher /** Version of h/w IP */ 7682ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 7692ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 77081629cbaSAlex Deucher /** Capabilities */ 7712ce9dde0SMikko Rapeli __u64 capabilities_flags; 77271062f43SKen Wang /** command buffer address start alignment*/ 7732ce9dde0SMikko Rapeli __u32 ib_start_alignment; 77471062f43SKen Wang /** command buffer size alignment*/ 7752ce9dde0SMikko Rapeli __u32 ib_size_alignment; 77681629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 7772ce9dde0SMikko Rapeli __u32 available_rings; 7782ce9dde0SMikko Rapeli __u32 _pad; 77981629cbaSAlex Deucher }; 78081629cbaSAlex Deucher 78144879b62SArindam Nath struct drm_amdgpu_info_num_handles { 78244879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 78344879b62SArindam Nath __u32 uvd_max_handles; 78444879b62SArindam Nath /** Handles currently in use for UVD */ 78544879b62SArindam Nath __u32 uvd_used_handles; 78644879b62SArindam Nath }; 78744879b62SArindam Nath 788bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 789bbe87974SAlex Deucher 790bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 791bbe87974SAlex Deucher /** System clock */ 792bbe87974SAlex Deucher __u32 sclk; 793bbe87974SAlex Deucher /** Memory clock */ 794bbe87974SAlex Deucher __u32 mclk; 795bbe87974SAlex Deucher /** VCE clock */ 796bbe87974SAlex Deucher __u32 eclk; 797bbe87974SAlex Deucher __u32 pad; 798bbe87974SAlex Deucher }; 799bbe87974SAlex Deucher 800bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 801bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 802bbe87974SAlex Deucher __u32 num_valid_entries; 803bbe87974SAlex Deucher __u32 pad; 804bbe87974SAlex Deucher }; 805bbe87974SAlex Deucher 80681629cbaSAlex Deucher /* 80781629cbaSAlex Deucher * Supported GPU families 80881629cbaSAlex Deucher */ 80981629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 810295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 81181629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 81281629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 81381629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 81439bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 815a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 81681629cbaSAlex Deucher 817cfa7152fSEmil Velikov #if defined(__cplusplus) 818cfa7152fSEmil Velikov } 819cfa7152fSEmil Velikov #endif 820cfa7152fSEmil Velikov 82181629cbaSAlex Deucher #endif 822